initial commit of new design for ddrctrl

applications/lofar2/designs/lofar2_unb2c_ddrctrl/hdllib.cfg

...signs/lofar2_unb2c_ddrctrl/lofar2_unb2c_ddrctrl.fpga.yaml

...unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_avs2_eth_coe_0.ip

...s_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_clk_0.ip

...r2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_jtag_uart_0.ip

...2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_nios2_gen2_0.ip

...b2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_onchip_memory2_0.ip

...lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_pio_pps.ip

...nb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_pio_system_info.ip

...lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_pio_wdi.ip

...far2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_ram_scrap.ip

..._unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl.ip

..._unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data.ip

...ofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_epcs.ip

...c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens.ip

...drctrl/qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens.ip

..._unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl.ip

..._unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data.ip

...ofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_remu.ip

...lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_wdi.ip