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Commit 5a8443b1 authored by Priest's avatar Priest
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hdl_lib_name = compaan_io_test_fn
hdl_library_clause_name = compaan_io_test_fn_lib
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag tr_10GbE mm io_test compaan_io_test_bn
hdl_lib_technology = ip_stratixiv
synth_files =
src/vhdl/mmm_compaan_io_test_fn.vhd
src/vhdl/compaan_wrapper.vhd
src/vhdl/compaan_io_test_fn.vhd
$RADIOHDL/applications/compaan/designs/compaan_unb1_10g_bg_db/src/vhdl/mmm_compaan_unb1_10g_bg_db.vhd
$RADIOHDL/applications/compaan/designs/compaan_unb1_10g_bg_db/src/vhdl/compaan_unb1_10g_bg_db.vhd
test_bench_files =
tb/vhdl/tb_io_test_fn.vhd
[modelsim_project_file]
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files = quartus/qsys_compaan_io_test_fn.qsys .
quartus_qsf_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/compaan_io_test_fn_pins.tcl
quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/compaan_io_test_fn/qsys_compaan_io_test_fn/synthesis/qsys_compaan_io_test_fn.qip
quartus_sdc_files =
$RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
mmm_name = compaan_io_test_fn
board_select = unb1
custom_peripherals =
reg_dp_offload_tx 1 1
reg_dp_offload_tx_hdr_dat 1 6
reg_dp_offload_tx_hdr_ovr 1 5
reg_dp_offload_rx_hdr_dat 1 7
reg_mdio_0 1 3
reg_mdio_1 1 3
reg_mdio_2 1 3
reg_tr_10gbe 1 15
reg_tr_xaui 1 11
reg_diagnostics 1 6
reg_tr_nonbonded 1 4
reg_compaan 1 19
input_clks = mm_clk
synth_master = qsys
vhdl_output_path = src/vhdl/
###############################################################################
#
# Copyright (C) 2014
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_mesh_tr_clk_pin.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_mesh_tr_nocmu_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/pins_tr_front_pcs_clk.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/pins_tr_front_pcs_0.tcl
------------------------------------------------------------------
-- Wrapper between ASTRON and Compaan
------------------------------------------------------------------
LIBRARY IEEE, dp_lib, unb1_board_lib, io_test_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
ENTITY compaan_wrapper IS
GENERIC (
g_blocks_per_sync : NATURAL := 10
);
PORT (
-- Streaming sink (RX: ASTRON -> Compaan)
snk_out_arr : OUT t_dp_siso_arr(14 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
snk_in_arr : IN t_dp_sosi_arr(14 DOWNTO 0);
-- Streaming src (TX: Compaan -> ASTRON)
src_in_arr : IN t_dp_siso_arr(14 DOWNTO 0);
src_out_arr : OUT t_dp_sosi_arr(14 DOWNTO 0);
-- Compaan: Other
TEST_STOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0 );
TEST_ERROR : OUT STD_LOGIC_VECTOR(2 DOWNTO 0 );
TEST_FIFO_FULL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0 );
TEST_BLOCK_RD : OUT STD_LOGIC_VECTOR(2 DOWNTO 0 );
address : IN STD_LOGIC_VECTOR(18 DOWNTO 0 );
read_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0 );
read_en : IN STD_LOGIC;
write_en : IN STD_LOGIC;
write_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0 );
MM_CLK : IN STD_LOGIC;
KPN_CLK : IN STD_LOGIC;
KPN_RST : IN STD_LOGIC
);
END compaan_wrapper;
ARCHITECTURE STRUCTURE OF compaan_wrapper IS
-- Array without SOP and EOP to be send to a dp_block_gen
SIGNAL src_out_arr_nop : t_dp_sosi_arr(14 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
SIGNAL compaan_snk_out_arr : t_dp_siso_arr(14 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
SIGNAL compaan_snk_in_arr : t_dp_sosi_arr(14 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL compaan_src_in_arr : t_dp_siso_arr(14 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
SIGNAL compaan_src_out_arr : t_dp_sosi_arr(14 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL control_vector_in : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL control_vector_out : STD_LOGIC_VECTOR(14 DOWNTO 0);
SIGNAL i_compaan_src_in_rdy: STD_LOGIC_VECTOR(14 DOWNTO 0);
BEGIN
gen_i_src_in_ready: FOR i IN 0 TO 14 GENERATE
i_compaan_src_in_rdy(i) <= NOT compaan_src_in_arr(i).ready;
END GENERATE;
-- Compaan ipcore
u_compaan_design: ENTITY io_test_lib.times_two_fn0
PORT MAP (
-- 10G XAUI 0
-- . RX
port0_in_Data => compaan_snk_in_arr(0).data(63 DOWNTO 0),
port0_in_Control => control_vector_in(0),
port0_in_Read => compaan_snk_out_arr(0).ready,
port0_in_Exists => compaan_snk_in_arr(0).valid,
-- . TX
port0_out_Data => compaan_src_out_arr(0).data(63 DOWNTO 0),
port0_out_Control => control_vector_out(0),
port0_out_Full => i_compaan_src_in_rdy(0),
port0_out_Write => compaan_src_out_arr(0).valid,
-- Terminal FN/BN0 Lane 0
-- . RX
port3_in_Data => compaan_snk_in_arr(3).data(63 DOWNTO 0),
port3_in_Control => control_vector_in(3),
port3_in_Read => compaan_snk_out_arr(3).ready,
port3_in_Exists => compaan_snk_in_arr(3).valid,
-- . TX
port3_out_Data => compaan_src_out_arr(3).data(63 DOWNTO 0),
port3_out_Control => control_vector_out(3),
port3_out_Full => i_compaan_src_in_rdy(3),
port3_out_Write => compaan_src_out_arr(3).valid,
-- Terminal FN/BN1 Lane 0
-- . RX
port6_in_Data => compaan_snk_in_arr(6).data(63 DOWNTO 0),
port6_in_Control => control_vector_in(6),
port6_in_Read => compaan_snk_out_arr(6).ready,
port6_in_Exists => compaan_snk_in_arr(6).valid,
-- . TX
port6_out_Data => compaan_src_out_arr(6).data(63 DOWNTO 0),
port6_out_Control => control_vector_out(6),
port6_out_Full => i_compaan_src_in_rdy(6),
port6_out_Write => compaan_src_out_arr(6).valid,
-- Compaan other
TEST_STOP => open,
TEST_ERROR => open,
TEST_FIFO_FULL => open,
TEST_BLOCK_RD => open,
address => address,
read_data => read_data,
read_en => read_en,
write_en => write_en,
write_data => write_data,
-- Compaan clocks
pci_clk => MM_CLK,
KPN_CLK => KPN_CLK,
KPN_RST => KPN_RST
);
-----------------------------------------------------------------------------
-- FIFO IN (ASTRON -> Compaan)
-----------------------------------------------------------------------------
gen_fifo_in: FOR i IN 0 TO 14 GENERATE
g_fifo_in: ENTITY dp_lib.dp_fifo_sc
GENERIC MAP(
g_data_w => 64,
g_bsn_w => 1,
g_empty_w => 1,
g_channel_w => 1,
g_error_w => 1,
g_use_bsn => FALSE,
g_use_empty => FALSE,
g_use_channel => FALSE,
g_use_error => FALSE,
g_use_sync => FALSE,
g_use_ctrl => TRUE,
g_use_complex => FALSE,
g_fifo_size => 4*g_blocks_per_sync,
g_fifo_af_margin => 4,
g_fifo_rl => 0
)
PORT MAP(
rst => KPN_RST,
clk => KPN_CLK,
-- Monitor FIFO filling
wr_ful => open,
usedw => open,
rd_emp => open,
-- ST Sink
snk_out => snk_out_arr(i),
snk_in => snk_in_arr(i),
-- ST Source
src_in => compaan_snk_out_arr(i),
src_out => compaan_snk_in_arr(i)
);
END GENERATE;
-----------------------------------------------------------------------------
-- FIFO OUT (Compaan -> ASTRON)
-----------------------------------------------------------------------------
gen_fifo_out: FOR i IN 0 TO 14 GENERATE
g_fifo_out: ENTITY dp_lib.dp_fifo_sc
GENERIC MAP(
g_data_w => 64,
g_bsn_w => 1,
g_empty_w => 1,
g_channel_w => 1,
g_error_w => 1,
g_use_bsn => FALSE,
g_use_empty => FALSE,
g_use_channel => FALSE,
g_use_error => FALSE,
g_use_sync => FALSE,
g_use_ctrl => TRUE,
g_use_complex => FALSE,
g_fifo_size => 4*g_blocks_per_sync,
g_fifo_af_margin => 4,
g_fifo_rl => 0
)
PORT MAP(
rst => KPN_RST,
clk => KPN_CLK,
-- Monitor FIFO filling
wr_ful => open,
usedw => open,
rd_emp => open,
-- ST Sink
snk_out => compaan_src_in_arr(i),
snk_in => compaan_src_out_arr(i),
-- ST Source
src_in => c_dp_siso_rdy,
src_out => src_out_arr_nop(i)
);
END GENERATE;
-- Generate SOP, EOP for ASTRON
gen_pkg_signals: FOR i IN 0 TO 14 GENERATE
u_gen_signals : ENTITY dp_lib.dp_block_gen
GENERIC MAP(
g_use_src_in => FALSE,
g_nof_data => g_blocks_per_sync
)
PORT MAP(
rst => KPN_RST,
clk => KPN_CLK,
-- Streaming sink
snk_in => src_out_arr_nop(i),
-- Streaming source
src_in => src_in_arr(i),
src_out => src_out_arr(i),
-- MM control
en => '1'
);
END GENERATE;
END ARCHITECTURE STRUCTURE;
#! /usr/bin/env python
###############################################################################
#
# Copyright (dC) 2015
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
# Purpose:
# . Test Compaan's capability to send data to a terminal
from common import *
import sys
import test_case
import node_io
import pi_diag_block_gen
import pi_diag_data_buffer
import pi_dp_offload_tx_hdr_dat_compaan_unb1_10g_terminal
import pi_eth
import pi_compaan
from eth import *
################################################################################
## Constants and variables
################################################################################
# System definitions
c_10g_data_w = 32 # <= 32 for terminal
c_blocksize = 8 # = frame_len
c_nof_blocks_per_sync = 8
c_test_loopback = True
c_only_set_dpotx = False
# Block gen definitions
c_bg_ram_size = 32
c_bg_nof_streams = 1
c_bg_gap_size = 3000
c_write_block_gen = True
# UDP header definitions
eth_src_mac = 0x2286080008 # 10G MAC base address for UniBoard
eth_dst_mac = 0x074306C700 #0x00074306C700 # 10G MAC address DOP36
ip_src_addr_fn0 = 0xc0a80164 # 0xc0a80164 = 192.168.1.100
ip_src_addr_fn1 = 0xc0a80165 # 0xc0a80165 = 192.168.1.101
ip_src_addr_fn2 = 0xc0a80166 # 0xc0a80164 = 192.168.1.102
ip_src_addr_fn3 = 0xc0a80167 # 0xc0a80165 = 192.168.1.103
ip_dst_addr = 0xc0a80102 # 0xc0a80102 = 192.168.1.2 = IP-address 10G in DOP36
# Instantiate testcase and IO
tc = test_case.Testcase('TB -', '')
io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
# Instantiate compaan
ca = pi_compaan.PiCompaan(tc, io, nof_inst=1)
# Create block generator/data buffer instance
bg = pi_diag_block_gen.PiDiagBlockGen(tc, io, c_bg_nof_streams, c_bg_ram_size, tc.nodeFn1Nrs )
db = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, instanceName = '', nofStreams=c_bg_nof_streams, ramSizePerStream=c_bg_ram_size, nodeNr = tc.nodeFn1Nrs )
# Create dp_offload_tx instance
dpotx_hdr_dat = pi_dp_offload_tx_hdr_dat_compaan_unb1_10g_terminal.PiDpOffloadTxHdrDatCompaanUnb110GTerminal(tc, io, nof_inst=1, node_nrs=tc.nodeFn0Nrs)
###############################################################################
# Calculate and print the IP header checksum for FN0
###############################################################################
# Fixed header constants
IP_HEADER_LENGTH = 20
UDP_HEADER_LENGTH = 8
USR_HEADER_LENGTH = 20
USR_HDR_WORD_ALIGN = 2
NOF_PAYLOAD_BYTES = c_blocksize * 8
ip_version = 4
ip_header_length = 5 # 5 32b words
ip_services = 0
ip_total_length = IP_HEADER_LENGTH+UDP_HEADER_LENGTH+USR_HEADER_LENGTH+USR_HDR_WORD_ALIGN+NOF_PAYLOAD_BYTES - 7 # 6196B
ip_identification = 0
ip_flags = 2
ip_fragment_offset = 0
ip_time_to_live = 127
ip_protocol = 17
ip_header_checksum = 0 # to be calculated
hdr_bits_common = CommonBits(ip_version ,4) & \
CommonBits(ip_header_length ,4) & \
CommonBits(ip_services ,8) & \
CommonBits(ip_total_length ,16) & \
CommonBits(ip_identification ,16) & \
CommonBits(ip_flags ,3) & \
CommonBits(ip_fragment_offset ,13) & \
CommonBits(ip_time_to_live ,8) & \
CommonBits(ip_protocol ,8) & \
CommonBits(ip_header_checksum ,16)
hdr_bits_fn0 = hdr_bits_common & \
CommonBits(ip_src_addr_fn0 ,32) & \
CommonBits(ip_dst_addr ,32)
hdr_bits_fn1 = hdr_bits_common & \
CommonBits(ip_src_addr_fn1 ,32) & \
CommonBits(ip_dst_addr ,32)
hdr_bits_fn2 = hdr_bits_common & \
CommonBits(ip_src_addr_fn2 ,32) & \
CommonBits(ip_dst_addr ,32)
hdr_bits_fn3 = hdr_bits_common & \
CommonBits(ip_src_addr_fn3 ,32) & \
CommonBits(ip_dst_addr ,32)
hdr_bytes_fn0 = CommonBytes(hdr_bits_fn0.data, IP_HEADER_LENGTH)
hdr_bytes_fn1 = CommonBytes(hdr_bits_fn1.data, IP_HEADER_LENGTH)
hdr_bytes_fn2 = CommonBytes(hdr_bits_fn2.data, IP_HEADER_LENGTH)
hdr_bytes_fn3 = CommonBytes(hdr_bits_fn3.data, IP_HEADER_LENGTH)
tc.append_log(3, 'IP header checksum FN0: %d' % ip_hdr_checksum(hdr_bytes_fn0))
tc.append_log(3, 'IP header checksum FN1: %d' % ip_hdr_checksum(hdr_bytes_fn1))
tc.append_log(3, 'IP header checksum FN2: %d' % ip_hdr_checksum(hdr_bytes_fn2))
tc.append_log(3, 'IP header checksum FN3: %d' % ip_hdr_checksum(hdr_bytes_fn3))
################################################################################
## Write settings
################################################################################
tc.append_log(3, 'Setting DPOTX for node FN0')
dpotx_hdr_dat.write(node_nrs=tc.nodeFn0Nrs, inst_nrs=tc.gpNumbers, registers=[('eth_src_mac', eth_src_mac + 0)], regmap=dpotx_hdr_dat.regmap)
dpotx_hdr_dat.write(node_nrs=tc.nodeFn0Nrs, inst_nrs=tc.gpNumbers, registers=[('eth_dst_mac', eth_dst_mac)], regmap=dpotx_hdr_dat.regmap)
dpotx_hdr_dat.write(node_nrs=tc.nodeFn0Nrs, inst_nrs=tc.gpNumbers, registers=[('ip_src_addr', ip_src_addr_fn0)], regmap=dpotx_hdr_dat.regmap)
dpotx_hdr_dat.write(node_nrs=tc.nodeFn0Nrs, inst_nrs=tc.gpNumbers, registers=[('ip_dst_addr', ip_dst_addr)], regmap=dpotx_hdr_dat.regmap)
dpotx_hdr_dat.write(node_nrs=tc.nodeFn0Nrs, inst_nrs=tc.gpNumbers, registers=[('ip_header_checksum', ip_hdr_checksum(hdr_bytes_fn0))], regmap=dpotx_hdr_dat.regmap)
dpotx_hdr_dat.read(node_nrs=tc.nodeFn0Nrs, inst_nrs=tc.gpNumbers, regmap=dpotx_hdr_dat.regmap)
tc.append_log(3, 'Setting BG for node BN0')
bg.write_block_gen_settings(samplesPerPacket=c_blocksize, blocksPerSync=c_nof_blocks_per_sync, gapSize=c_bg_gap_size, memLowAddr=0, memHighAddr=c_bg_ram_size-1, BSNInit=10)
################################################################################
## Write data to the block generator
################################################################################
bg_data=[]
tc.append_log(3, 'Writing data to BG RAM')
for i in range(c_bg_ram_size):
bg_data.append(i)
if c_write_block_gen:
for i in range(c_bg_nof_streams):
bg.write_waveform_ram(data=bg_data, channelNr=i)
bg.write_enable()
################################################################################
## Read data from the databuffer
################################################################################
db_out = []
do_until_ge(db.read_nof_words, ms_retry=1000, val=c_blocksize, s_timeout=3600)
bg.write_disable()
for i in range(1):
db_out.append(flatten(db.read_data_buffer(streamNr=i, n=c_blocksize*3, radix='uns', width=c_10g_data_w, nofColumns=1)))
print db_out
\ No newline at end of file
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib, compaan_io_test_bn_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
ENTITY tb_io_test_fn IS
END tb_io_test_fn;
ARCHITECTURE tb OF tb_io_test_fn IS
-----------------------------------------------------------------------------
-- CONSTANTS
-----------------------------------------------------------------------------
-- System
CONSTANT c_sim : BOOLEAN := TRUE;
CONSTANT c_unb1_board_nr : NATURAL := 0;
CONSTANT c_node_nr_dut_fn : NATURAL := 0;
CONSTANT c_node_nr_dut_bn : NATURAL := 4;
CONSTANT c_node_nr_10G_lcu : NATURAL := 1;
CONSTANT c_id_dut_fn : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb1_board_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr_dut_fn, c_unb1_board_nof_chip_w);
CONSTANT c_id_dut_bn : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb1_board_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr_dut_bn, c_unb1_board_nof_chip_w);
CONSTANT c_id_10g_lcu : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb1_board_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr_10g_lcu, c_unb1_board_nof_chip_w);
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
-- Clock periods
CONSTANT c_eth_clk_period : TIME := 40 ns;
CONSTANT c_sa_clk_period : TIME := 6.4 ns;
CONSTANT c_clk_period : TIME := 5 ns;
CONSTANT c_cable_delay : TIME := 12 ns;
CONSTANT c_pps_period : NATURAL := 1000;
-- UNB1 Sensors
CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW
CONSTANT c_eth_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0101001"; -- MAX1618 address MID LOW
CONSTANT c_hot_swap_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1000100"; -- LTC4260 address L L L
CONSTANT c_fpga_temp : INTEGER := 60;
CONSTANT c_eth_temp : INTEGER := 40;
CONSTANT c_hot_swap_R_sense : REAL := 0.01;
CONSTANT c_uniboard_current : REAL := 5.0; -- = assume 5.0 A on UniBoard
CONSTANT c_uniboard_supply : REAL := 48.0; -- = assume 48.0 V on UniBoard
CONSTANT c_uniboard_adin : REAL := -1.0; -- = NC on UniBoard
------------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------------
-- System
SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version;
SIGNAL ID_DUT_FN : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_id_dut_fn;
SIGNAL ID_DUT_BN : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_id_dut_bn;
SIGNAL ID_10G_LCU : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_id_10g_lcu;
SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
-- Clocks
SIGNAL clk : STD_LOGIC := '0';
SIGNAL sa_clk : STD_LOGIC := '1';
SIGNAL eth_clk : STD_LOGIC := '0';
SIGNAL pps : STD_LOGIC := '0';
SIGNAL pps_rst : STD_LOGIC := '0';
SIGNAL eth_rxp : STD_LOGIC;
SIGNAL eth_txp : STD_LOGIC;
SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC;
SIGNAL WDI : STD_LOGIC;
SIGNAL INTA : STD_LOGIC;
SIGNAL INTB : STD_LOGIC;
-- Serial I/O: Terminal
SIGNAL FN_BN_0_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL FN_BN_0_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL FN_BN_1_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL FN_BN_1_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL FN_BN_2_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL FN_BN_2_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL FN_BN_3_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
SIGNAL FN_BN_3_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
-- Serial I/O: 10GbE Interface
SIGNAL SI_FN_0_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL SI_FN_0_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL SI_FN_1_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL SI_FN_1_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL SI_FN_2_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL SI_FN_2_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL SI_FN_3_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL SI_FN_3_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BEGIN
----------------------------------------------------------------------------
-- Externally generated clocks
----------------------------------------------------------------------------
clk <= NOT clk AFTER c_clk_period/2;
eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;
sa_clk <= NOT sa_clk AFTER c_sa_clk_period/2;
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
sens_scl <= 'H'; -- pull up
sens_sda <= 'H'; -- pull up
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
------------------------------------------------------------------------------
-- 1GbE Loopback model
------------------------------------------------------------------------------
eth_rxp <= TRANSPORT eth_txp AFTER c_cable_delay;
------------------------------------------------------------------------------
-- DUT Fn
------------------------------------------------------------------------------
u_dut_fn: ENTITY work.compaan_io_test_fn
GENERIC MAP(
g_sim => c_sim,
g_sim_unb_nr => c_unb1_board_nr,
g_sim_node_nr => c_node_nr_dut_fn
)
PORT MAP(
CLK => clk,
PPS => pps,
VERSION => VERSION,
ID => ID_DUT_FN,
ETH_clk => eth_clk,
ETH_SGIN => eth_rxp,
ETH_SGOUT => eth_txp,
SA_CLK => sa_clk,
SB_CLK => sa_clk,
FN_BN_0_TX => FN_BN_0_TX,
FN_BN_0_RX => FN_BN_0_RX,
FN_BN_1_TX => FN_BN_1_TX,
FN_BN_1_RX => FN_BN_1_RX,
FN_BN_2_TX => FN_BN_2_TX,
FN_BN_2_RX => FN_BN_2_RX,
FN_BN_3_TX => FN_BN_3_TX,
FN_BN_3_RX => FN_BN_3_RX,
SI_FN_0_TX => SI_FN_0_TX,
SI_FN_0_RX => SI_FN_0_RX,
SI_FN_1_TX => SI_FN_1_TX,
SI_FN_1_RX => SI_FN_1_RX,
SI_FN_2_TX => SI_FN_2_TX,
SI_FN_2_RX => SI_FN_2_RX,
SI_FN_3_TX => SI_FN_3_TX,
SI_FN_3_RX => SI_FN_3_RX
);
-----------------------------------------------------------------------------
-- DUT Bn
-----------------------------------------------------------------------------
u_dut_bn: ENTITY compaan_io_test_bn_lib.compaan_io_test_bn
GENERIC MAP(
g_sim => c_sim,
g_sim_unb_nr => c_unb1_board_nr,
g_sim_node_nr => c_node_nr_dut_bn
)
PORT MAP(
CLK => clk,
PPS => pps,
VERSION => VERSION,
ID => ID_DUT_BN,
ETH_clk => eth_clk,
ETH_SGIN => eth_rxp,
ETH_SGOUT => eth_txp,
SB_CLK => sa_clk,
FN_BN_0_TX => FN_BN_0_RX,
FN_BN_0_RX => FN_BN_0_TX,
FN_BN_1_TX => FN_BN_1_RX,
FN_BN_1_RX => FN_BN_1_TX,
FN_BN_2_TX => FN_BN_2_RX,
FN_BN_2_RX => FN_BN_2_TX,
FN_BN_3_TX => FN_BN_3_RX,
FN_BN_3_RX => FN_BN_3_TX
);
-----------------------------------------------------------------------------
-- 10G LCU
-----------------------------------------------------------------------------
u_10g_lcu: ENTITY work.compaan_unb1_10g_bg_db
GENERIC MAP(
g_sim => c_sim,
g_sim_unb_nr => c_unb1_board_nr,
g_sim_node_nr => c_node_nr_10g_lcu
)
PORT MAP(
CLK => clk,
PPS => pps,
VERSION => VERSION,
ID => ID_10G_LCU,
ETH_clk => eth_clk,
ETH_SGIN => eth_rxp,
ETH_SGOUT => eth_txp,
SA_CLK => sa_clk,
SI_FN_0_TX => SI_FN_0_RX,
SI_FN_0_RX => SI_FN_0_TX,
SI_FN_1_TX => SI_FN_1_RX,
SI_FN_1_RX => SI_FN_1_TX,
SI_FN_2_TX => SI_FN_2_RX,
SI_FN_2_RX => SI_FN_2_TX,
SI_FN_3_TX => SI_FN_3_RX,
SI_FN_3_RX => SI_FN_3_TX
);
------------------------------------------------------------------------------
-- UniBoard sensors
------------------------------------------------------------------------------
-- I2C slaves that are available for each FPGA
u_fpga_temp : ENTITY i2c_lib.dev_max1618
GENERIC MAP (
g_address => c_fpga_temp_address
)
PORT MAP (
scl => sens_scl,
sda => sens_sda,
temp => c_fpga_temp
);
-- I2C slaves that are available only via FPGA back node 3
u_eth_temp : ENTITY i2c_lib.dev_max1618
GENERIC MAP (
g_address => c_eth_temp_address
)
PORT MAP (
scl => sens_scl,
sda => sens_sda,
temp => c_eth_temp
);
u_power : ENTITY i2c_lib.dev_ltc4260
GENERIC MAP (
g_address => c_hot_swap_address,
g_R_sense => c_hot_swap_R_sense
)
PORT MAP (
scl => sens_scl,
sda => sens_sda,
ana_current_sense => c_uniboard_current,
ana_volt_source => c_uniboard_supply,
ana_volt_adin => c_uniboard_adin
);
END tb;
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