diff --git a/applications/compaan/designs/compaan_io_test_fn/hdllib.cfg b/applications/compaan/designs/compaan_io_test_fn/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..8287132848ef8003a95bdba875ad3acd4d6b7da3
--- /dev/null
+++ b/applications/compaan/designs/compaan_io_test_fn/hdllib.cfg
@@ -0,0 +1,36 @@
+hdl_lib_name = compaan_io_test_fn
+hdl_library_clause_name = compaan_io_test_fn_lib
+hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag tr_10GbE mm io_test compaan_io_test_bn
+hdl_lib_technology = ip_stratixiv
+
+synth_files =
+ src/vhdl/mmm_compaan_io_test_fn.vhd
+ src/vhdl/compaan_wrapper.vhd
+ src/vhdl/compaan_io_test_fn.vhd
+
+ $RADIOHDL/applications/compaan/designs/compaan_unb1_10g_bg_db/src/vhdl/mmm_compaan_unb1_10g_bg_db.vhd
+ $RADIOHDL/applications/compaan/designs/compaan_unb1_10g_bg_db/src/vhdl/compaan_unb1_10g_bg_db.vhd
+
+
+test_bench_files =
+ tb/vhdl/tb_io_test_fn.vhd
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files = quartus/qsys_compaan_io_test_fn.qsys .
+
+quartus_qsf_files =
+ $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+
+quartus_tcl_files =
+ quartus/compaan_io_test_fn_pins.tcl
+
+quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/compaan_io_test_fn/qsys_compaan_io_test_fn/synthesis/qsys_compaan_io_test_fn.qip
+
+quartus_sdc_files =
+ $RADIOHDL/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+
diff --git a/applications/compaan/designs/compaan_io_test_fn/mmm.cfg b/applications/compaan/designs/compaan_io_test_fn/mmm.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..7a9272ffc7cc58ae0cf031534104dbf685212fe1
--- /dev/null
+++ b/applications/compaan/designs/compaan_io_test_fn/mmm.cfg
@@ -0,0 +1,25 @@
+mmm_name = compaan_io_test_fn
+
+board_select = unb1
+
+custom_peripherals =
+ reg_dp_offload_tx 1 1
+ reg_dp_offload_tx_hdr_dat 1 6
+ reg_dp_offload_tx_hdr_ovr 1 5
+ reg_dp_offload_rx_hdr_dat 1 7
+ reg_mdio_0 1 3
+ reg_mdio_1 1 3
+ reg_mdio_2 1 3
+ reg_tr_10gbe 1 15
+ reg_tr_xaui 1 11
+ reg_diagnostics 1 6
+ reg_tr_nonbonded 1 4
+ reg_compaan 1 19
+
+input_clks = mm_clk
+
+synth_master = qsys
+
+vhdl_output_path = src/vhdl/
+
+
diff --git a/applications/compaan/designs/compaan_io_test_fn/quartus/compaan_io_test_fn_pins.tcl b/applications/compaan/designs/compaan_io_test_fn/quartus/compaan_io_test_fn_pins.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3f7525ef7f1abbcc92e19575497bc440a10d471d
--- /dev/null
+++ b/applications/compaan/designs/compaan_io_test_fn/quartus/compaan_io_test_fn_pins.tcl
@@ -0,0 +1,31 @@
+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_mesh_tr_clk_pin.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_mesh_tr_nocmu_pins.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/pins_tr_front_pcs_clk.tcl
+source $::env(UNB)/Firmware/designs/unb_common/src/tcl/pins_tr_front_pcs_0.tcl
+
+
diff --git a/applications/compaan/designs/compaan_io_test_fn/quartus/qsys_compaan_io_test_fn.qsys b/applications/compaan/designs/compaan_io_test_fn/quartus/qsys_compaan_io_test_fn.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..bb32e7a0e8abd2e7f082949a7c6a268bd5ff0e0c
--- /dev/null
+++ b/applications/compaan/designs/compaan_io_test_fn/quartus/qsys_compaan_io_test_fn.qsys
@@ -0,0 +1,2209 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="System" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element $${FILENAME}
+ {
+ }
+ element jtag_uart_0.avalon_jtag_slave
+ {
+ datum baseAddress
+ {
+ value = "1600";
+ type = "long";
+ }
+ }
+ element avs_eth_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element clk_input
+ {
+ datum _sortIndex
+ {
+ value = "18";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element cpu_0
+ {
+ datum _sortIndex
+ {
+ value = "2";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element cpu_0.jtag_debug_module
+ {
+ datum baseAddress
+ {
+ value = "14336";
+ type = "long";
+ }
+ }
+ element jtag_uart_0
+ {
+ datum _sortIndex
+ {
+ value = "5";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_tr_10GbE.mem
+ {
+ datum _tags
+ {
+ value = "";
+ type = "String";
+ }
+ datum baseAddress
+ {
+ value = "262144";
+ type = "long";
+ }
+ }
+ element reg_dp_offload_tx_hdr_dat.mem
+ {
+ datum baseAddress
+ {
+ value = "256";
+ type = "long";
+ }
+ }
+ element pio_pps.mem
+ {
+ datum baseAddress
+ {
+ value = "1608";
+ type = "long";
+ }
+ }
+ element reg_unb_sens.mem
+ {
+ datum baseAddress
+ {
+ value = "1536";
+ type = "long";
+ }
+ }
+ element pio_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "0";
+ type = "long";
+ }
+ }
+ element reg_diagnostics.mem
+ {
+ datum baseAddress
+ {
+ value = "1024";
+ type = "long";
+ }
+ }
+ element reg_tr_nonbonded.mem
+ {
+ datum baseAddress
+ {
+ value = "1344";
+ type = "long";
+ }
+ }
+ element reg_mdio_0.mem
+ {
+ datum baseAddress
+ {
+ value = "1504";
+ type = "long";
+ }
+ }
+ element reg_tr_xaui.mem
+ {
+ datum baseAddress
+ {
+ value = "16384";
+ type = "long";
+ }
+ }
+ element reg_mdio_2.mem
+ {
+ datum baseAddress
+ {
+ value = "1472";
+ type = "long";
+ }
+ }
+ element reg_dp_offload_tx_hdr_ovr.mem
+ {
+ datum baseAddress
+ {
+ value = "128";
+ type = "long";
+ }
+ }
+ element reg_mdio_1.mem
+ {
+ datum baseAddress
+ {
+ value = "1440";
+ type = "long";
+ }
+ }
+ element reg_compaan.mem
+ {
+ datum baseAddress
+ {
+ value = "2097152";
+ type = "long";
+ }
+ }
+ element rom_system_info.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "4096";
+ type = "long";
+ }
+ }
+ element reg_dp_offload_tx.mem
+ {
+ datum baseAddress
+ {
+ value = "1616";
+ type = "long";
+ }
+ }
+ element reg_dp_offload_rx_hdr_dat.mem
+ {
+ datum baseAddress
+ {
+ value = "512";
+ type = "long";
+ }
+ }
+ element reg_wdi.mem
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "12288";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_ram
+ {
+ datum baseAddress
+ {
+ value = "24576";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_reg
+ {
+ datum baseAddress
+ {
+ value = "1280";
+ type = "long";
+ }
+ }
+ element avs_eth_0.mms_tse
+ {
+ datum baseAddress
+ {
+ value = "8192";
+ type = "long";
+ }
+ }
+ element onchip_memory2_0
+ {
+ datum _sortIndex
+ {
+ value = "4";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{output_language=VHDL, output_directory=D:\\svnroot\\UniBoard_FP7\\UniBoard\\trunk\\Firmware\\designs\\unb_unb1_minimal\\build\\synth\\quartus}";
+ type = "String";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_debug_wave
+ {
+ datum _sortIndex
+ {
+ value = "3";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_pps
+ {
+ datum _sortIndex
+ {
+ value = "13";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_system_info
+ {
+ datum _sortIndex
+ {
+ value = "1";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element pio_wdi
+ {
+ datum _sortIndex
+ {
+ value = "6";
+ type = "int";
+ }
+ datum megawizard_uipreferences
+ {
+ value = "{}";
+ type = "String";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element avs_eth_0.ram_write
+ {
+ datum _tags
+ {
+ value = "";
+ type = "String";
+ }
+ }
+ element reg_compaan
+ {
+ datum _sortIndex
+ {
+ value = "24";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_diagnostics
+ {
+ datum _sortIndex
+ {
+ value = "21";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_dp_offload_rx_hdr_dat
+ {
+ datum _sortIndex
+ {
+ value = "11";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_dp_offload_tx
+ {
+ datum _sortIndex
+ {
+ value = "20";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_dp_offload_tx_hdr_dat
+ {
+ datum _sortIndex
+ {
+ value = "19";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_dp_offload_tx_hdr_ovr
+ {
+ datum _sortIndex
+ {
+ value = "22";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_mdio_0
+ {
+ datum _sortIndex
+ {
+ value = "8";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_mdio_1
+ {
+ datum _sortIndex
+ {
+ value = "9";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_mdio_2
+ {
+ datum _sortIndex
+ {
+ value = "10";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_tr_10GbE
+ {
+ datum _sortIndex
+ {
+ value = "16";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_tr_nonbonded
+ {
+ datum _sortIndex
+ {
+ value = "23";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_tr_xaui
+ {
+ datum _sortIndex
+ {
+ value = "17";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_unb_sens
+ {
+ datum _sortIndex
+ {
+ value = "12";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_wdi
+ {
+ datum _sortIndex
+ {
+ value = "14";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element rom_system_info
+ {
+ datum _sortIndex
+ {
+ value = "15";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element onchip_memory2_0.s1
+ {
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
+ datum baseAddress
+ {
+ value = "131072";
+ type = "long";
+ }
+ }
+ element pio_wdi.s1
+ {
+ datum baseAddress
+ {
+ value = "1584";
+ type = "long";
+ }
+ }
+ element pio_debug_wave.s1
+ {
+ datum baseAddress
+ {
+ value = "1568";
+ type = "long";
+ }
+ }
+ element timer_0.s1
+ {
+ datum baseAddress
+ {
+ value = "1408";
+ type = "long";
+ }
+ }
+ element reg_wdi.system_reset
+ {
+ datum _tags
+ {
+ value = "";
+ type = "String";
+ }
+ }
+ element timer_0
+ {
+ datum _sortIndex
+ {
+ value = "7";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element reg_wdi.writedata
+ {
+ datum _tags
+ {
+ value = "";
+ type = "String";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="EP4SGX230KF40C2" />
+ <parameter name="deviceFamily" value="STRATIXIV" />
+ <parameter name="deviceSpeedGrade" value="" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VHDL" />
+ <parameter name="maxAdditionalLatency" value="0" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="1" />
+ <parameter name="timeStamp" value="1475832231911" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="pio_debug_wave_external_connection"
+ internal="pio_debug_wave.external_connection"
+ type="conduit"
+ dir="end">
+ <port name="out_port_from_the_pio_debug_wave" internal="out_port" />
+ </interface>
+ <interface
+ name="pio_wdi_external_connection"
+ internal="pio_wdi.external_connection"
+ type="conduit"
+ dir="end">
+ <port name="out_port_from_the_pio_wdi" internal="out_port" />
+ </interface>
+ <interface
+ name="reg_mdio_0_reset"
+ internal="reg_mdio_0.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_0_clk"
+ internal="reg_mdio_0.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_0_address"
+ internal="reg_mdio_0.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_0_write"
+ internal="reg_mdio_0.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_0_read"
+ internal="reg_mdio_0.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_0_writedata"
+ internal="reg_mdio_0.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_0_readdata"
+ internal="reg_mdio_0.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_1_reset"
+ internal="reg_mdio_1.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_1_readdata"
+ internal="reg_mdio_1.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_1_clk"
+ internal="reg_mdio_1.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_1_address"
+ internal="reg_mdio_1.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_1_write"
+ internal="reg_mdio_1.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_1_writedata"
+ internal="reg_mdio_1.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_1_read"
+ internal="reg_mdio_1.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_2_reset"
+ internal="reg_mdio_2.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_2_clk"
+ internal="reg_mdio_2.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_2_address"
+ internal="reg_mdio_2.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_2_write"
+ internal="reg_mdio_2.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_2_writedata"
+ internal="reg_mdio_2.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_2_read"
+ internal="reg_mdio_2.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_mdio_2_readdata"
+ internal="reg_mdio_2.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_hdr_dat_reset"
+ internal="reg_dp_offload_rx_hdr_dat.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_hdr_dat_clk"
+ internal="reg_dp_offload_rx_hdr_dat.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_hdr_dat_address"
+ internal="reg_dp_offload_rx_hdr_dat.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_hdr_dat_write"
+ internal="reg_dp_offload_rx_hdr_dat.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_hdr_dat_writedata"
+ internal="reg_dp_offload_rx_hdr_dat.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_hdr_dat_read"
+ internal="reg_dp_offload_rx_hdr_dat.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_rx_hdr_dat_readdata"
+ internal="reg_dp_offload_rx_hdr_dat.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_mm_rst"
+ internal="avs_eth_0.reset"
+ type="conduit"
+ dir="end" />
+ <interface name="eth1g_mm_clk" internal="avs_eth_0.clk" type="conduit" dir="end" />
+ <interface
+ name="eth1g_tse_address"
+ internal="avs_eth_0.tse_address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_tse_write"
+ internal="avs_eth_0.tse_write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_tse_read"
+ internal="avs_eth_0.tse_read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_tse_writedata"
+ internal="avs_eth_0.tse_writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_tse_readdata"
+ internal="avs_eth_0.tse_readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_tse_waitrequest"
+ internal="avs_eth_0.tse_waitrequest"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_reg_address"
+ internal="avs_eth_0.reg_address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_reg_write"
+ internal="avs_eth_0.reg_write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_reg_read"
+ internal="avs_eth_0.reg_read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_reg_writedata"
+ internal="avs_eth_0.reg_writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_reg_readdata"
+ internal="avs_eth_0.reg_readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_ram_address"
+ internal="avs_eth_0.ram_address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_ram_write"
+ internal="avs_eth_0.ram_write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_ram_read"
+ internal="avs_eth_0.ram_read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_ram_writedata"
+ internal="avs_eth_0.ram_writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth1g_ram_readdata"
+ internal="avs_eth_0.ram_readdata"
+ type="conduit"
+ dir="end" />
+ <interface name="eth1g_irq" internal="avs_eth_0.irq" type="conduit" dir="end" />
+ <interface
+ name="reg_unb_sens_reset"
+ internal="reg_unb_sens.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_clk"
+ internal="reg_unb_sens.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_address"
+ internal="reg_unb_sens.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_write"
+ internal="reg_unb_sens.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_writedata"
+ internal="reg_unb_sens.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_read"
+ internal="reg_unb_sens.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_unb_sens_readdata"
+ internal="reg_unb_sens.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_reset"
+ internal="pio_system_info.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_clk"
+ internal="pio_system_info.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_address"
+ internal="pio_system_info.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_write"
+ internal="pio_system_info.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_writedata"
+ internal="pio_system_info.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_read"
+ internal="pio_system_info.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_system_info_readdata"
+ internal="pio_system_info.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_pps_reset"
+ internal="pio_pps.reset"
+ type="conduit"
+ dir="end" />
+ <interface name="pio_pps_clk" internal="pio_pps.clk" type="conduit" dir="end" />
+ <interface
+ name="pio_pps_address"
+ internal="pio_pps.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_pps_write"
+ internal="pio_pps.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="pio_pps_writedata"
+ internal="pio_pps.writedata"
+ type="conduit"
+ dir="end" />
+ <interface name="pio_pps_read" internal="pio_pps.read" type="conduit" dir="end" />
+ <interface
+ name="pio_pps_readdata"
+ internal="pio_pps.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_reset"
+ internal="reg_wdi.reset"
+ type="conduit"
+ dir="end" />
+ <interface name="reg_wdi_clk" internal="reg_wdi.clk" type="conduit" dir="end" />
+ <interface
+ name="reg_wdi_address"
+ internal="reg_wdi.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_write"
+ internal="reg_wdi.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_wdi_writedata"
+ internal="reg_wdi.writedata"
+ type="conduit"
+ dir="end" />
+ <interface name="reg_wdi_read" internal="reg_wdi.read" type="conduit" dir="end" />
+ <interface
+ name="reg_wdi_readdata"
+ internal="reg_wdi.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_reset"
+ internal="rom_system_info.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_clk"
+ internal="rom_system_info.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_address"
+ internal="rom_system_info.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_write"
+ internal="rom_system_info.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_writedata"
+ internal="rom_system_info.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_read"
+ internal="rom_system_info.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="rom_system_info_readdata"
+ internal="rom_system_info.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_reset"
+ internal="reg_tr_10GbE.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_clk"
+ internal="reg_tr_10GbE.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_address"
+ internal="reg_tr_10GbE.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_write"
+ internal="reg_tr_10GbE.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_writedata"
+ internal="reg_tr_10GbE.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_read"
+ internal="reg_tr_10GbE.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_readdata"
+ internal="reg_tr_10GbE.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_10gbe_waitrequest"
+ internal="reg_tr_10GbE.waitrequest"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_xaui_reset"
+ internal="reg_tr_xaui.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_xaui_clk"
+ internal="reg_tr_xaui.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_xaui_address"
+ internal="reg_tr_xaui.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_xaui_write"
+ internal="reg_tr_xaui.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_xaui_read"
+ internal="reg_tr_xaui.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_xaui_writedata"
+ internal="reg_tr_xaui.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_xaui_readdata"
+ internal="reg_tr_xaui.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_xaui_waitrequest"
+ internal="reg_tr_xaui.waitrequest"
+ type="conduit"
+ dir="end" />
+ <interface name="clk_in" internal="clk_input.clk_in" type="clock" dir="end" />
+ <interface
+ name="reset_in"
+ internal="clk_input.clk_in_reset"
+ type="reset"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_reset"
+ internal="reg_dp_offload_tx_hdr_dat.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_clk"
+ internal="reg_dp_offload_tx_hdr_dat.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_address"
+ internal="reg_dp_offload_tx_hdr_dat.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_write"
+ internal="reg_dp_offload_tx_hdr_dat.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_writedata"
+ internal="reg_dp_offload_tx_hdr_dat.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_read"
+ internal="reg_dp_offload_tx_hdr_dat.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_dat_readdata"
+ internal="reg_dp_offload_tx_hdr_dat.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_reset"
+ internal="reg_dp_offload_tx.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_clk"
+ internal="reg_dp_offload_tx.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_address"
+ internal="reg_dp_offload_tx.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_write"
+ internal="reg_dp_offload_tx.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_writedata"
+ internal="reg_dp_offload_tx.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_read"
+ internal="reg_dp_offload_tx.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_readdata"
+ internal="reg_dp_offload_tx.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_reset"
+ internal="reg_dp_offload_tx_hdr_ovr.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_clk"
+ internal="reg_dp_offload_tx_hdr_ovr.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_address"
+ internal="reg_dp_offload_tx_hdr_ovr.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_write"
+ internal="reg_dp_offload_tx_hdr_ovr.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_writedata"
+ internal="reg_dp_offload_tx_hdr_ovr.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_read"
+ internal="reg_dp_offload_tx_hdr_ovr.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_dp_offload_tx_hdr_ovr_readdata"
+ internal="reg_dp_offload_tx_hdr_ovr.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_compaan_reset"
+ internal="reg_compaan.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_compaan_clk"
+ internal="reg_compaan.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_compaan_address"
+ internal="reg_compaan.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_compaan_write"
+ internal="reg_compaan.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_compaan_writedata"
+ internal="reg_compaan.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_compaan_read"
+ internal="reg_compaan.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_compaan_readdata"
+ internal="reg_compaan.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diagnostics_reset"
+ internal="reg_diagnostics.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diagnostics_clk"
+ internal="reg_diagnostics.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diagnostics_address"
+ internal="reg_diagnostics.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diagnostics_write"
+ internal="reg_diagnostics.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diagnostics_writedata"
+ internal="reg_diagnostics.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diagnostics_read"
+ internal="reg_diagnostics.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_diagnostics_readdata"
+ internal="reg_diagnostics.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_nonbonded_reset"
+ internal="reg_tr_nonbonded.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_nonbonded_clk"
+ internal="reg_tr_nonbonded.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_nonbonded_address"
+ internal="reg_tr_nonbonded.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_nonbonded_write"
+ internal="reg_tr_nonbonded.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_nonbonded_writedata"
+ internal="reg_tr_nonbonded.writedata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_nonbonded_read"
+ internal="reg_tr_nonbonded.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reg_tr_nonbonded_readdata"
+ internal="reg_tr_nonbonded.readdata"
+ type="conduit"
+ dir="end" />
+ <module
+ kind="altera_avalon_onchip_memory2"
+ version="11.1"
+ enabled="1"
+ name="onchip_memory2_0">
+ <parameter name="allowInSystemMemoryContentEditor" value="false" />
+ <parameter name="autoInitializationFileName">qsys_compaan_io_test_onchip_memory2_0</parameter>
+ <parameter name="blockType" value="M144K" />
+ <parameter name="dataWidth" value="32" />
+ <parameter name="deviceFamily" value="Stratix IV" />
+ <parameter name="dualPort" value="false" />
+ <parameter name="initMemContent" value="true" />
+ <parameter name="initializationFileName" value="onchip_memory2_0" />
+ <parameter name="instanceID" value="NONE" />
+ <parameter name="memorySize" value="131072" />
+ <parameter name="readDuringWriteMode" value="DONT_CARE" />
+ <parameter name="simAllowMRAMContentsFile" value="false" />
+ <parameter name="simMemInitOnlyFilename" value="0" />
+ <parameter name="singleClockOperation" value="false" />
+ <parameter name="slave1Latency" value="1" />
+ <parameter name="slave2Latency" value="1" />
+ <parameter name="useNonDefaultInitFile" value="true" />
+ <parameter name="useShallowMemBlocks" value="false" />
+ <parameter name="writable" value="true" />
+ </module>
+ <module
+ kind="altera_avalon_jtag_uart"
+ version="11.1"
+ enabled="1"
+ name="jtag_uart_0">
+ <parameter name="allowMultipleConnections" value="false" />
+ <parameter name="hubInstanceID" value="0" />
+ <parameter name="readBufferDepth" value="64" />
+ <parameter name="readIRQThreshold" value="8" />
+ <parameter name="simInputCharacterStream"><![CDATA[a
+q]]></parameter>
+ <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
+ <parameter name="useRegistersForReadBuffer" value="false" />
+ <parameter name="useRegistersForWriteBuffer" value="false" />
+ <parameter name="useRelativePathForSimFile" value="false" />
+ <parameter name="writeBufferDepth" value="64" />
+ <parameter name="writeIRQThreshold" value="8" />
+ </module>
+ <module
+ kind="altera_avalon_pio"
+ version="11.1"
+ enabled="1"
+ name="pio_debug_wave">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="25000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="32" />
+ </module>
+ <module kind="altera_avalon_pio" version="11.1" enabled="1" name="pio_wdi">
+ <parameter name="bitClearingEdgeCapReg" value="false" />
+ <parameter name="bitModifyingOutReg" value="false" />
+ <parameter name="captureEdge" value="false" />
+ <parameter name="clockRate" value="25000000" />
+ <parameter name="direction" value="Output" />
+ <parameter name="edgeType" value="RISING" />
+ <parameter name="generateIRQ" value="false" />
+ <parameter name="irqType" value="LEVEL" />
+ <parameter name="resetValue" value="0" />
+ <parameter name="simDoTestBenchWiring" value="false" />
+ <parameter name="simDrivenValue" value="0" />
+ <parameter name="width" value="1" />
+ </module>
+ <module kind="altera_avalon_timer" version="11.1" enabled="1" name="timer_0">
+ <parameter name="alwaysRun" value="true" />
+ <parameter name="counterSize" value="32" />
+ <parameter name="fixedPeriod" value="true" />
+ <parameter name="period" value="1" />
+ <parameter name="periodUnits" value="MSEC" />
+ <parameter name="resetOutput" value="false" />
+ <parameter name="snapshot" value="false" />
+ <parameter name="systemFrequency" value="25000000" />
+ <parameter name="timeoutPulseOutput" value="false" />
+ <parameter name="timerPreset">SIMPLE_PERIODIC_INTERRUPT</parameter>
+ </module>
+ <module kind="altera_nios2_qsys" version="11.1" enabled="1" name="cpu_0">
+ <parameter name="setting_showUnpublishedSettings" value="false" />
+ <parameter name="setting_showInternalSettings" value="false" />
+ <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
+ <parameter name="setting_preciseIllegalMemAccessException" value="false" />
+ <parameter name="setting_preciseDivisionErrorException" value="false" />
+ <parameter name="setting_performanceCounter" value="false" />
+ <parameter name="setting_illegalMemAccessDetection" value="false" />
+ <parameter name="setting_illegalInstructionsTrap" value="false" />
+ <parameter name="setting_fullWaveformSignals" value="false" />
+ <parameter name="setting_extraExceptionInfo" value="false" />
+ <parameter name="setting_exportPCB" value="false" />
+ <parameter name="setting_debugSimGen" value="false" />
+ <parameter name="setting_clearXBitsLDNonBypass" value="true" />
+ <parameter name="setting_bit31BypassDCache" value="true" />
+ <parameter name="setting_bigEndian" value="false" />
+ <parameter name="setting_bhtIndexPcOnly" value="false" />
+ <parameter name="setting_avalonDebugPortPresent" value="false" />
+ <parameter name="setting_alwaysEncrypt" value="true" />
+ <parameter name="setting_allowFullAddressRange" value="false" />
+ <parameter name="setting_activateTrace" value="true" />
+ <parameter name="setting_activateTestEndChecker" value="false" />
+ <parameter name="setting_activateMonitors" value="true" />
+ <parameter name="setting_activateModelChecker" value="false" />
+ <parameter name="setting_HDLSimCachesCleared" value="true" />
+ <parameter name="setting_HBreakTest" value="false" />
+ <parameter name="muldiv_divider" value="false" />
+ <parameter name="mpu_useLimit" value="false" />
+ <parameter name="mpu_enabled" value="false" />
+ <parameter name="mmu_enabled" value="false" />
+ <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
+ <parameter name="manuallyAssignCpuID" value="false" />
+ <parameter name="debug_triggerArming" value="true" />
+ <parameter name="debug_embeddedPLL" value="true" />
+ <parameter name="debug_debugReqSignals" value="false" />
+ <parameter name="debug_assignJtagInstanceID" value="false" />
+ <parameter name="dcache_omitDataMaster" value="false" />
+ <parameter name="cpuReset" value="false" />
+ <parameter name="is_hardcopy_compatible" value="false" />
+ <parameter name="setting_shadowRegisterSets" value="0" />
+ <parameter name="mpu_numOfInstRegion" value="8" />
+ <parameter name="mpu_numOfDataRegion" value="8" />
+ <parameter name="mmu_TLBMissExcOffset" value="0" />
+ <parameter name="debug_jtagInstanceID" value="0" />
+ <parameter name="resetOffset" value="0" />
+ <parameter name="exceptionOffset" value="32" />
+ <parameter name="cpuID" value="0" />
+ <parameter name="cpuID_stored" value="0" />
+ <parameter name="breakOffset" value="32" />
+ <parameter name="userDefinedSettings" value="" />
+ <parameter name="resetSlave" value="onchip_memory2_0.s1" />
+ <parameter name="mmu_TLBMissExcSlave" value="" />
+ <parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
+ <parameter name="breakSlave">cpu_0.jtag_debug_module</parameter>
+ <parameter name="setting_perfCounterWidth" value="32" />
+ <parameter name="setting_interruptControllerType" value="Internal" />
+ <parameter name="setting_branchPredictionType" value="Automatic" />
+ <parameter name="setting_bhtPtrSz" value="8" />
+ <parameter name="muldiv_multiplierType" value="DSPBlock" />
+ <parameter name="mpu_minInstRegionSize" value="12" />
+ <parameter name="mpu_minDataRegionSize" value="12" />
+ <parameter name="mmu_uitlbNumEntries" value="4" />
+ <parameter name="mmu_udtlbNumEntries" value="6" />
+ <parameter name="mmu_tlbPtrSz" value="7" />
+ <parameter name="mmu_tlbNumWays" value="16" />
+ <parameter name="mmu_processIDNumBits" value="8" />
+ <parameter name="impl" value="Small" />
+ <parameter name="icache_size" value="4096" />
+ <parameter name="icache_ramBlockType" value="Automatic" />
+ <parameter name="icache_numTCIM" value="0" />
+ <parameter name="icache_burstType" value="None" />
+ <parameter name="dcache_bursts" value="false" />
+ <parameter name="debug_level" value="Level1" />
+ <parameter name="debug_OCIOnchipTrace" value="_128" />
+ <parameter name="dcache_size" value="2048" />
+ <parameter name="dcache_ramBlockType" value="Automatic" />
+ <parameter name="dcache_numTCDM" value="0" />
+ <parameter name="dcache_lineSize" value="32" />
+ <parameter name="instAddrWidth" value="18" />
+ <parameter name="dataAddrWidth" value="22" />
+ <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
+ <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
+ <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_dp_offload_tx_hdr_ovr.mem' start='0x80' end='0x100' /><slave name='reg_dp_offload_tx_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_rx_hdr_dat.mem' start='0x200' end='0x400' /><slave name='reg_diagnostics.mem' start='0x400' end='0x500' /><slave name='avs_eth_0.mms_reg' start='0x500' end='0x540' /><slave name='reg_tr_nonbonded.mem' start='0x540' end='0x580' /><slave name='timer_0.s1' start='0x580' end='0x5A0' /><slave name='reg_mdio_1.mem' start='0x5A0' end='0x5C0' /><slave name='reg_mdio_2.mem' start='0x5C0' end='0x5E0' /><slave name='reg_mdio_0.mem' start='0x5E0' end='0x600' /><slave name='reg_unb_sens.mem' start='0x600' end='0x620' /><slave name='pio_debug_wave.s1' start='0x620' end='0x630' /><slave name='pio_wdi.s1' start='0x630' end='0x640' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x640' end='0x648' /><slave name='pio_pps.mem' start='0x648' end='0x650' /><slave name='reg_dp_offload_tx.mem' start='0x650' end='0x658' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='reg_compaan.mem' start='0x200000' end='0x400000' /></address-map>]]></parameter>
+ <parameter name="clockFrequency" value="25000000" />
+ <parameter name="deviceFamilyName" value="Stratix IV" />
+ <parameter name="internalIrqMaskSystemInfo" value="7" />
+ <parameter name="customInstSlavesSystemInfo" value="<info/>" />
+ <parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 1 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 1 HARDCOPY 0 HAS_18_BIT_MULTS 1 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 1 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 1 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 1 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 1 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 1 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 1 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 1 TRANSCEIVER_6G_BLOCK 1 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 1 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1</parameter>
+ <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
+ <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mdio_0">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mdio_1">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_mdio_2">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_dp_offload_rx_hdr_dat">
+ <parameter name="g_adr_w" value="7" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs2_eth_coe" version="1.0" enabled="1" name="avs_eth_0">
+ <parameter name="AUTO_MM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_unb_sens">
+ <parameter name="g_adr_w" value="3" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_system_info">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="pio_pps">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_wdi">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="rom_system_info">
+ <parameter name="g_adr_w" value="10" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module
+ kind="avs_common_mm_readlatency0"
+ version="1.0"
+ enabled="1"
+ name="reg_tr_10GbE">
+ <parameter name="g_adr_w" value="15" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module
+ kind="avs_common_mm_readlatency0"
+ version="1.0"
+ enabled="1"
+ name="reg_tr_xaui">
+ <parameter name="g_adr_w" value="11" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="clock_source" version="11.1" enabled="1" name="clk_input">
+ <parameter name="clockFrequency" value="25000000" />
+ <parameter name="clockFrequencyKnown" value="true" />
+ <parameter name="inputClockFrequency" value="0" />
+ <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_dp_offload_tx_hdr_dat">
+ <parameter name="g_adr_w" value="6" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_dp_offload_tx">
+ <parameter name="g_adr_w" value="1" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_dp_offload_tx_hdr_ovr">
+ <parameter name="g_adr_w" value="5" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_compaan">
+ <parameter name="g_adr_w" value="19" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module kind="avs_common_mm" version="1.0" enabled="1" name="reg_diagnostics">
+ <parameter name="g_adr_w" value="6" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <module
+ kind="avs_common_mm"
+ version="1.0"
+ enabled="1"
+ name="reg_tr_nonbonded">
+ <parameter name="g_adr_w" value="4" />
+ <parameter name="g_dat_w" value="32" />
+ <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="25000000" />
+ </module>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.instruction_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3800" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="cpu_0.jtag_debug_module">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3800" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.instruction_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="onchip_memory2_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00020000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="jtag_uart_0.avalon_jtag_slave">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0640" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="11.1"
+ start="cpu_0.d_irq"
+ end="jtag_uart_0.irq">
+ <parameter name="irqNumber" value="0" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_debug_wave.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0620" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_wdi.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0630" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="timer_0.s1">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0580" />
+ </connection>
+ <connection kind="interrupt" version="11.1" start="cpu_0.d_irq" end="timer_0.irq">
+ <parameter name="irqNumber" value="1" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="onchip_memory2_0.reset1" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="jtag_uart_0.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="pio_debug_wave.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="pio_wdi.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="timer_0.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="cpu_0.reset_n" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_mdio_0.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_mdio_1.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x05a0" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_mdio_1.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_mdio_2.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_mdio_2.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x05c0" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_dp_offload_rx_hdr_dat.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dp_offload_rx_hdr_dat.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0200" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_mdio_0.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x05e0" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_tse">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x2000" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_reg">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0500" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="avs_eth_0.mms_ram">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x6000" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_unb_sens.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_unb_sens.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0600" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="pio_system_info.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="pio_pps.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="pio_pps.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0648" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_wdi.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_wdi.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x3000" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="rom_system_info.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="rom_system_info.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x1000" />
+ </connection>
+ <connection
+ kind="interrupt"
+ version="11.1"
+ start="cpu_0.d_irq"
+ end="avs_eth_0.interrupt">
+ <parameter name="irqNumber" value="2" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_tr_10GbE.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_tr_10GbE.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00040000" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_tr_xaui.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_tr_xaui.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x4000" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="avs_eth_0.mm_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_mdio_0.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_mdio_1.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_mdio_2.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_dp_offload_rx_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_unb_sens.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="pio_pps.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_wdi.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="rom_system_info.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_tr_10GbE.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_tr_xaui.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="timer_0.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="pio_wdi.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="jtag_uart_0.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="onchip_memory2_0.reset1" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="pio_debug_wave.reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="cpu_0.reset_n" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="pio_system_info.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="avs_eth_0.mm_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_dp_offload_tx_hdr_dat.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_dp_offload_tx_hdr_dat.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dp_offload_tx_hdr_dat.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0100" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_dp_offload_tx_hdr_dat.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_mdio_2.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_tr_xaui.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_tr_10GbE.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="rom_system_info.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_wdi.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="pio_pps.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_unb_sens.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_dp_offload_rx_hdr_dat.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_mdio_1.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_mdio_0.system" />
+ <connection kind="clock" version="11.1" start="clk_input.clk" end="timer_0.clk" />
+ <connection kind="clock" version="11.1" start="clk_input.clk" end="pio_wdi.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="jtag_uart_0.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="onchip_memory2_0.clk1" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="pio_debug_wave.clk" />
+ <connection kind="clock" version="11.1" start="clk_input.clk" end="cpu_0.clk" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="pio_system_info.system" />
+ <connection kind="clock" version="11.1" start="clk_input.clk" end="avs_eth_0.mm" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_dp_offload_tx.system" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_dp_offload_tx_hdr_ovr.system" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_dp_offload_tx.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_dp_offload_tx.system_reset" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_dp_offload_tx_hdr_ovr.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dp_offload_tx_hdr_ovr.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0080" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_dp_offload_tx.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0650" />
+ </connection>
+ <connection
+ kind="reset"
+ version="11.1"
+ start="cpu_0.jtag_debug_module_reset"
+ end="reg_dp_offload_tx_hdr_ovr.system_reset" />
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_compaan.system" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_compaan.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_compaan.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x00200000" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_diagnostics.system" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_diagnostics.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_diagnostics.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0400" />
+ </connection>
+ <connection
+ kind="clock"
+ version="11.1"
+ start="clk_input.clk"
+ end="reg_tr_nonbonded.system" />
+ <connection
+ kind="reset"
+ version="11.1"
+ start="clk_input.clk_reset"
+ end="reg_tr_nonbonded.system_reset" />
+ <connection
+ kind="avalon"
+ version="11.1"
+ start="cpu_0.data_master"
+ end="reg_tr_nonbonded.mem">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0540" />
+ </connection>
+</system>
diff --git a/applications/compaan/designs/compaan_io_test_fn/src/vhdl/compaan_io_test_fn.vhd b/applications/compaan/designs/compaan_io_test_fn/src/vhdl/compaan_io_test_fn.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5a07acb3672b64c8a0fb77b5c2e3514ca9eb43cd
--- /dev/null
+++ b/applications/compaan/designs/compaan_io_test_fn/src/vhdl/compaan_io_test_fn.vhd
@@ -0,0 +1,789 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2013
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose:
+-- . Test Compaan's capability of inter-FPGA communication
+
+LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib, diag_lib, tr_10GbE_lib, technology_lib;
+use IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+ENTITY compaan_io_test_fn IS
+ GENERIC (
+ g_design_name : STRING := "compaan_unb1_10g_plus_one";
+ g_design_note : STRING := "revision info";
+ g_technology : NATURAL := c_tech_stratixiv;
+ g_sim : BOOLEAN := FALSE; -- set by ModelSim
+ g_sim_unb_nr : NATURAL := 0; -- set by ModelSim
+ g_sim_node_nr : NATURAL := 0; -- set by ModelSim
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- dp_clk is generated by SOPC altpll
+ PPS : IN STD_LOGIC;
+ WDI : OUT STD_LOGIC;
+ INTA : INOUT STD_LOGIC;
+ INTB : INOUT STD_LOGIC;
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ sens_sc : INOUT STD_LOGIC;
+ sens_sd : INOUT STD_LOGIC;
+
+ -- 1GbE Control Interface
+ ETH_clk : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC;
+ ETH_SGOUT : OUT STD_LOGIC;
+
+ -- Transceiver clocks
+ SA_CLK : IN STD_LOGIC := '0'; -- SerDes Clock BN-BI / SI_FN
+ SB_CLK : IN STD_LOGIC := '0';
+
+ -- Serial I/O: Terminal
+ FN_BN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+
+ -- Serial I/O: 10GbE receivers
+ SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+
+ SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_RSTN : OUT STD_LOGIC := '1' -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
+ -- So we need to assign a '1' to it.
+ );
+END compaan_io_test_fn;
+
+
+ARCHITECTURE str OF compaan_io_test_fn IS
+
+ -----------------------------------------------------------------------------
+ -- CONSTANTS
+ -----------------------------------------------------------------------------
+ -- General
+ CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 0);
+ CONSTANT c_block_size : NATURAL := 8;
+ CONSTANT c_use_1GbE : BOOLEAN := TRUE;
+ CONSTANT c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(g_sim, 0, 1), 0, 0, 0, 0, 0, 0, 1);
+ -- Terminal
+ CONSTANT c_nof_bus : NATURAL := 4;
+ CONSTANT c_term_data_w : NATURAL := 32;
+ CONSTANT c_nof_streams : NATURAL := 1;
+
+ CONSTANT c_phy_nof_serial : NATURAL := 3;
+ CONSTANT c_phy_gx_mbps : NATURAL := 6250;
+ CONSTANT c_phy_rx_fifo_size : NATURAL := c_bram_m9k_fifo_depth;
+ CONSTANT c_phy_ena_reorder : BOOLEAN := NOT g_sim;
+
+ CONSTANT c_term_use_tx : BOOLEAN := TRUE;
+ CONSTANT c_term_tx_use_fifo : BOOLEAN := TRUE;
+ CONSTANT c_term_tx_fifo_size : NATURAL := c_bram_m9k_fifo_depth;
+ CONSTANT c_term_tx_fifo_fill : NATURAL := 0;
+
+ CONSTANT c_term_use_rx : BOOLEAN := TRUE;
+ CONSTANT c_term_rx_use_fifo : BOOLEAN := TRUE;
+ CONSTANT c_term_rx_fifo_size : NATURAL := c_bram_m9k_fifo_depth;
+ CONSTANT c_term_rx_fifo_fill : NATURAL := 0;
+ CONSTANT c_term_rx_timeout_w : NATURAL := 0;
+ -- 10GbE
+ CONSTANT c_nof_10G_streams : NATURAL := 1;
+ CONSTANT c_10G_data_w : NATURAL := 64;
+ CONSTANT c_nof_crc_words : NATURAL := 0;
+ CONSTANT c_nof_blocks_per_packet : NATURAL := 1;
+ -- Offloads
+ CONSTANT c_ip_length : NATURAL := c_block_size*8 + 50;
+ CONSTANT c_udp_length : NATURAL := c_block_size*8 + 30;
+ CONSTANT c_nof_hdr_fields : NATURAL := 3+12+4+10;
+ CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "111"&"111111111111"&"0011"&"101111111"&"0";
+ CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), " ", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), " ", 16, field_default(c_ip_length) ), --1508) ),
+ ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(0) ),
+ ( field_name_pad("udp_src_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), " ", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), " ", 16, field_default(c_udp_length) ), --1488) ),
+ ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
+ ( field_name_pad("usr_sync" ), " ", 1, field_default(1) ),
+ ( field_name_pad("usr_bsn" ), " ", 60, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_0" ), " ", 7, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_1" ), " ", 9, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_2" ), " ", 10, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_3" ), " ", 33, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_4" ), " ", 5, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_5" ), " ", 8, field_default(0) ),
+ ( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ),
+ ( field_name_pad("usr_hdr_word_align" ), " ", 16, field_default(0) ) );
+
+
+ -----------------------------------------------------------------------------
+ -- SIGNALS
+ -----------------------------------------------------------------------------
+
+ SIGNAL block_gen_src_out_arr : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);
+
+ -- System
+ -- . Clocks and resets
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+ SIGNAL dp_clk : STD_LOGIC;
+ SIGNAL dp_rst : STD_LOGIC;
+ SIGNAL dp_pps : STD_LOGIC;
+ SIGNAL tr_clk : STD_LOGIC;
+ SIGNAL cal_clk : STD_LOGIC;
+ SIGNAL sa_rst : STD_LOGIC := '0';
+
+ SIGNAL mm_locked : STD_LOGIC;
+ SIGNAL epcs_clk : STD_LOGIC;
+ -- . Others
+ SIGNAL this_chip_id : STD_LOGIC_VECTOR( c_unb1_board_nof_chip_w-1 DOWNTO 0);
+ SIGNAL pout_wdi : STD_LOGIC;
+ SIGNAL eth1g_tse_clk : STD_LOGIC;
+ SIGNAL eth1g_mm_rst : STD_LOGIC;
+ SIGNAL eth1g_reg_interrupt : STD_LOGIC;
+
+ -- 10GbE
+ -- . FIFO
+ SIGNAL dp_fifo_sc_snk_in_arr : t_dp_sosi_arr(c_nof_10G_streams-1 DOWNTO 0);
+ SIGNAL dp_fifo_sc_snk_out_arr : t_dp_siso_arr(c_nof_10G_streams-1 DOWNTO 0);
+ -- . Header
+ SIGNAL hdr_fields_out_arr : t_slv_1024_arr(c_nof_10G_streams-1 DOWNTO 0);
+ SIGNAL hdr_fields_in_arr : t_slv_1024_arr(c_nof_10G_streams-1 DOWNTO 0);
+ -- . XAUI
+ SIGNAL xaui_tx_arr : t_xaui_arr(c_nof_10G_streams-1 DOWNTO 0);
+ SIGNAL xaui_rx_arr : t_xaui_arr(c_nof_10G_streams-1 DOWNTO 0);
+ SIGNAL front_xaui_tx_arr : t_unb1_board_xaui_sl_2arr(c_nof_10G_streams-1 DOWNTO 0);
+ SIGNAL front_xaui_rx_arr : t_unb1_board_xaui_sl_2arr(c_nof_10G_streams-1 DOWNTO 0);
+ -- . MDIO
+ SIGNAL mdio_mdc_arr : STD_LOGIC_VECTOR(c_nof_10G_streams-1 DOWNTO 0);
+ SIGNAL mdio_mdat_in_arr : STD_LOGIC_VECTOR(c_nof_10G_streams-1 DOWNTO 0);
+ SIGNAL mdio_mdat_oen_arr : STD_LOGIC_VECTOR(c_nof_10G_streams-1 DOWNTO 0);
+ -- . Offload: RX
+ SIGNAL dp_offload_rx_snk_in_arr : t_dp_sosi_arr(c_nof_10G_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_snk_out_arr : t_dp_siso_arr(c_nof_10G_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_src_in_arr : t_dp_siso_arr(c_nof_10G_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_src_out_arr : t_dp_sosi_arr(c_nof_10G_streams-1 DOWNTO 0);
+ -- . Offload: TX
+ SIGNAL dp_offload_tx_snk_in_arr : t_dp_sosi_arr(c_nof_10G_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_tx_snk_out_arr : t_dp_siso_arr(c_nof_10G_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(c_nof_10G_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(c_nof_10G_streams-1 DOWNTO 0);
+
+ -- Terminal
+ SIGNAL term_tx_usr_siso_2arr : t_unb1_board_mesh_siso_2arr;
+ SIGNAL term_tx_usr_sosi_2arr : t_unb1_board_mesh_sosi_2arr;
+ SIGNAL term_rx_usr_siso_2arr : t_unb1_board_mesh_siso_2arr;
+ SIGNAL term_rx_usr_sosi_2arr : t_unb1_board_mesh_sosi_2arr;
+ SIGNAL term_tx_serial_2arr : t_unb1_board_mesh_sl_2arr;
+ SIGNAL term_rx_serial_2arr : t_unb1_board_mesh_sl_2arr;
+
+ -- Compaan
+ SIGNAL compaan_snk_out_arr : t_dp_siso_arr(14 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+ SIGNAL compaan_snk_in_arr : t_dp_sosi_arr(14 DOWNTO 0);
+ SIGNAL compaan_src_in_arr : t_dp_siso_arr(14 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+ SIGNAL compaan_src_out_arr : t_dp_sosi_arr(14 DOWNTO 0);
+ SIGNAL TEST_STOP : STD_LOGIC_VECTOR(2 DOWNTO 0);
+ SIGNAL TEST_ERROR : STD_LOGIC_VECTOR(2 DOWNTO 0);
+ SIGNAL TEST_FIFO_FULL : STD_LOGIC_VECTOR(1 DOWNTO 0);
+ SIGNAL TEST_BLOCK_RD : STD_LOGIC_VECTOR(2 DOWNTO 0);
+
+ -- MM interface
+ -- . 10GbE
+ SIGNAL reg_tr_10GbE_mosi : t_mem_mosi;
+ SIGNAL reg_tr_10GbE_miso : t_mem_miso;
+ SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
+ SIGNAL reg_tr_xaui_miso : t_mem_miso;
+ SIGNAL reg_mdio_mosi_arr : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
+ SIGNAL reg_mdio_miso_arr : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
+ SIGNAL reg_mdio_0_mosi : t_mem_mosi;
+ SIGNAL reg_mdio_0_miso : t_mem_miso;
+ SIGNAL reg_mdio_1_mosi : t_mem_mosi;
+ SIGNAL reg_mdio_1_miso : t_mem_miso;
+ SIGNAL reg_mdio_2_mosi : t_mem_mosi;
+ SIGNAL reg_mdio_2_miso : t_mem_miso;
+ -- . Terminal
+ SIGNAL reg_tr_nonbonded_mosi : t_mem_mosi;
+ SIGNAL reg_tr_nonbonded_miso : t_mem_miso;
+ SIGNAL reg_diagnostics_mosi : t_mem_mosi;
+ SIGNAL reg_diagnostics_miso : t_mem_miso;
+ -- . Compaan
+ SIGNAL reg_compaan_mosi : t_mem_mosi;
+ SIGNAL reg_compaan_miso : t_mem_miso;
+ -- . UNB1 Cntrl
+ SIGNAL reg_wdi_mosi : t_mem_mosi;
+ SIGNAL reg_wdi_miso : t_mem_miso;
+ SIGNAL reg_ppsh_mosi : t_mem_mosi;
+ SIGNAL reg_ppsh_miso : t_mem_miso;
+ SIGNAL eth1g_tse_mosi : t_mem_mosi;
+ SIGNAL eth1g_tse_miso : t_mem_miso;
+ SIGNAL eth1g_reg_mosi : t_mem_mosi;
+ SIGNAL eth1g_reg_miso : t_mem_miso;
+ SIGNAL eth1g_ram_mosi : t_mem_mosi;
+ SIGNAL eth1g_ram_miso : t_mem_miso;
+ SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL reg_unb_system_info_miso : t_mem_miso;
+ SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL rom_unb_system_info_miso : t_mem_miso;
+ SIGNAL reg_unb_sens_mosi : t_mem_mosi;
+ SIGNAL reg_unb_sens_miso : t_mem_miso;
+ SIGNAL reg_epcs_mosi : t_mem_mosi;
+ SIGNAL reg_epcs_miso : t_mem_miso;
+ SIGNAL reg_remu_mosi : t_mem_mosi;
+ SIGNAL reg_remu_miso : t_mem_miso;
+ SIGNAL reg_dp_offload_tx_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_tx_miso : t_mem_miso;
+ SIGNAL reg_dp_offload_tx_hdr_ovr_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_tx_hdr_ovr_miso : t_mem_miso;
+ -- . Offload: RX
+ SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
+ -- . Offload: TX
+ SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- Interface: 10GbE
+ -----------------------------------------------------------------------------
+ -- Wire together different types
+ gen_wire: FOR i IN 0 TO c_nof_10G_streams-1 GENERATE
+ front_xaui_tx_arr(i) <= xaui_tx_arr(i);
+ xaui_rx_arr(i) <= front_xaui_rx_arr(i);
+ END GENERATE;
+
+ u_front_io: ENTITY unb1_board_lib.unb1_board_front_io
+ GENERIC MAP(
+ g_nof_xaui => c_nof_10G_streams
+ )
+ PORT MAP(
+ xaui_tx_arr => front_xaui_tx_arr,
+ xaui_rx_arr => front_xaui_rx_arr,
+
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr,
+
+ -- Serial I/O
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL
+ );
+
+ u_areset_sa_rst: ENTITY common_lib.common_areset
+ GENERIC MAP(
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ PORT MAP(
+ clk => SA_CLK,
+ in_rst => '0',
+ out_rst => sa_rst
+ );
+
+ u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_10G_streams,
+ g_use_mdio => TRUE
+ )
+ PORT MAP(
+ -- Transceiver PLL reference clock
+ tr_ref_clk_156 => SA_CLK,
+ tr_ref_rst_156 => sa_rst,
+ -- Calibration & reconfig clock
+ cal_rec_clk => mm_clk,
+ -- MM Interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mosi,
+ reg_mac_miso => reg_tr_10GbE_miso,
+
+ xaui_mosi => reg_tr_xaui_mosi,
+ xaui_miso => reg_tr_xaui_miso,
+
+ mdio_mosi_arr => reg_mdio_mosi_arr(c_nof_10G_streams-1 DOWNTO 0),
+ mdio_miso_arr => reg_mdio_miso_arr(c_nof_10G_streams-1 DOWNTO 0),
+ -- DP Interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- Data received by 10G
+ src_out_arr => dp_offload_rx_snk_in_arr,
+ src_in_arr => dp_offload_rx_snk_out_arr,
+ -- Data to be send by 10G
+ snk_out_arr => dp_offload_tx_src_in_arr,
+ snk_in_arr => dp_offload_tx_src_out_arr,
+ -- Serial XAUI I/O
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr,
+ -- MDIO Interface
+ mdio_rst => SI_FN_RSTN,
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr
+ );
+
+ gen_dp_fifo_sc: FOR i IN 0 TO c_nof_10G_streams-1 GENERATE
+ u_dp_fifo_sc: ENTITY dp_lib.dp_fifo_sc
+ GENERIC MAP(
+ g_data_w => c_10G_data_w,
+ g_fifo_size => 3*c_block_size
+ )
+ PORT MAP(
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => dp_fifo_sc_snk_out_arr(i),
+ snk_in => dp_fifo_sc_snk_in_arr(i),
+
+ src_in => dp_offload_tx_snk_out_arr(i),
+ src_out => dp_offload_tx_snk_in_arr(i)
+ );
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- Offload: RX
+ -----------------------------------------------------------------------------
+ u_dp_offload_rx: ENTITY dp_lib.dp_offload_rx
+ GENERIC MAP(
+ g_nof_streams => c_nof_10G_streams,
+ g_data_w => c_10G_data_w,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_remove_crc => c_use_1GbE,
+ g_crc_nof_words => c_nof_crc_words
+ )
+ PORT MAP(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
+
+ -----------------------------------------------------------------------------
+ -- Terminal
+ -----------------------------------------------------------------------------
+ u_unb1_board_terminals_mesh: ENTITY unb1_board_lib.unb1_board_terminals_mesh
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_level => 1,
+ -- System
+ g_node_type => e_any,
+ g_nof_bus => c_nof_bus,
+ -- User
+ g_usr_use_complex => FALSE,
+ g_usr_data_w => c_term_data_w,
+ g_usr_frame_len => c_block_size,
+ g_usr_nof_streams => c_nof_streams,
+ -- Phy
+ g_phy_nof_serial => c_phy_nof_serial,
+ g_phy_gx_mbps => c_phy_gx_mbps,
+ g_phy_rx_fifo_size => c_phy_rx_fifo_size,
+ g_phy_ena_reorder => NOT g_sim,
+ -- Tx
+ g_use_tx => c_term_use_tx,
+ g_tx_input_use_fifo => c_term_tx_use_fifo,
+ g_tx_input_fifo_size => c_term_tx_fifo_size,
+ g_tx_input_fifo_fill => c_term_tx_fifo_fill,
+ -- Rx
+ g_use_rx => c_term_use_rx,
+ g_rx_output_use_fifo => c_term_rx_use_fifo,
+ g_rx_output_fifo_size => c_term_rx_fifo_size,
+ g_rx_output_fifo_fill => c_term_rx_fifo_fill,
+ g_rx_timeout_w => c_term_rx_timeout_w
+ )
+ PORT MAP(
+ chip_id => this_chip_id,
+ -- Clocks
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_sync => dp_pps,
+ tr_clk => SB_CLK,
+ cal_clk => cal_clk,
+ -- User Interface (4 nodes)(4 lanes)
+ tx_usr_siso_2arr => term_tx_usr_siso_2arr,
+ tx_usr_sosi_2arr => term_tx_usr_sosi_2arr,
+ rx_usr_siso_2arr => term_rx_usr_siso_2arr,
+ rx_usr_sosi_2arr => term_rx_usr_sosi_2arr,
+ -- Serial (tr_nonbonded)
+ tx_serial_2arr => term_tx_serial_2arr,
+ rx_serial_2arr => term_rx_serial_2arr,
+ -- MM Control
+ -- . tr_nonbonded
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+ -- . Monitor databuffer
+ ram_diag_data_buf_mosi => open,
+ ram_diag_data_buf_miso => open
+ );
+
+ u_unb1_board_mesh_io: ENTITY unb1_board_lib.unb1_board_mesh_io
+ PORT MAP(
+ tx_serial_2arr => term_tx_serial_2arr,
+ rx_serial_2arr => term_rx_serial_2arr,
+ -- Serial I/O
+ FN_BN_0_TX => FN_BN_0_TX,
+ FN_BN_0_RX => FN_BN_0_RX,
+ FN_BN_1_TX => FN_BN_1_TX,
+ FN_BN_1_RX => FN_BN_1_RX,
+ FN_BN_2_TX => FN_BN_2_TX,
+ FN_BN_2_RX => FN_BN_2_RX,
+ FN_BN_3_TX => FN_BN_3_TX,
+ FN_BN_3_RX => FN_BN_3_RX
+ );
+
+ -----------------------------------------------------------------------------
+ -- Compaan
+ -----------------------------------------------------------------------------
+ u_compaan_design: ENTITY work.compaan_wrapper
+ GENERIC MAP(
+ g_blocks_per_sync => c_block_size
+ )
+ PORT MAP(
+ -- Streaming sink
+ snk_out_arr => compaan_snk_out_arr,
+ snk_in_arr => compaan_snk_in_arr,
+ -- Streaming source
+ src_in_arr => compaan_src_in_arr,
+ src_out_arr => compaan_src_out_arr,
+ -- Compaan: Other
+ TEST_STOP => TEST_STOP,
+ TEST_ERROR => TEST_ERROR,
+ TEST_FIFO_FULL => TEST_FIFO_FULL,
+ TEST_BLOCK_RD => TEST_BLOCK_RD,
+ address => reg_compaan_mosi.address(18 DOWNTO 0),
+ read_data => reg_compaan_miso.rddata(c_word_w-1 DOWNTO 0),
+ read_en => reg_compaan_mosi.rd,
+ write_en => reg_compaan_mosi.wr,
+ write_data => reg_compaan_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ -- Compaan: Clocks
+ MM_CLK => mm_clk,
+ KPN_CLK => dp_clk,
+ KPN_RST => dp_rst
+ );
+
+ -- Connect the compaan streaming sink and source to ASTRON
+ wire_compaan_10G: FOR i IN 0 TO c_nof_10G_streams-1 GENERATE
+ compaan_src_in_arr(i) <= dp_fifo_sc_snk_out_arr(i);
+ dp_fifo_sc_snk_in_arr(i) <= compaan_src_out_arr(i);
+
+ compaan_snk_in_arr(i) <= dp_offload_rx_src_out_arr(i);
+ dp_offload_rx_src_in_arr(i) <= compaan_snk_out_arr(i);
+ END GENERATE;
+
+ wire_compaan_term_node: FOR i IN 0 TO 3 GENERATE
+ wire_compaan_term_lane: FOR j IN 0 TO 2 GENERATE
+ term_tx_usr_sosi_2arr(i)(j) <= compaan_src_out_arr(3+(i*3)+j);
+ compaan_src_in_arr(3+(i*3)+j) <= term_tx_usr_siso_2arr(i)(j);
+
+ term_rx_usr_siso_2arr(i)(j) <= compaan_snk_out_arr(3+(i*3)+j);
+ compaan_snk_in_arr(3+(i*3)+j) <= term_rx_usr_sosi_2arr(i)(j);
+ END GENERATE;
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- Offload: TX
+ -----------------------------------------------------------------------------
+ u_dp_offload_tx: ENTITY dp_lib.dp_offload_tx
+ GENERIC MAP(
+ g_nof_streams => c_nof_10G_streams,
+ g_data_w => c_10G_data_w,
+ g_use_complex => FALSE,
+ g_nof_words_per_block => c_block_size,
+ g_nof_blocks_per_packet => c_nof_blocks_per_packet,
+ g_hdr_field_arr => c_hdr_field_arr,
+ g_hdr_field_sel => c_hdr_field_ovr_init,
+ g_use_post_split_fifo => FALSE
+ )
+ PORT MAP(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_tx_snk_in_arr,
+ snk_out_arr => dp_offload_tx_snk_out_arr,
+
+ src_out_arr => dp_offload_tx_src_out_arr,
+ src_in_arr => dp_offload_tx_src_in_arr,
+
+ hdr_fields_in_arr => hdr_fields_in_arr
+ );
+
+ gen_hdr_in_fields: FOR i IN 0 TO c_nof_10G_streams-1 GENERATE
+ -- dst = src
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_src_mac" )) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_dst_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_dst_mac" )) <= x"00228608" & B"000"&ID(7 DOWNTO 3) & RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
+
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_src_addr" )) <= x"0A63" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_dst_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_dst_addr" )) <= x"0A63" & B"000"&ID(7 DOWNTO 3) & INCR_UVEC(RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w), 1);
+
+ -- dst port goes through 4000,4001,4002
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_src_port" ) DOWNTO field_lo(c_hdr_field_arr, "udp_src_port" )) <= TO_UVEC(4000+i, 16);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_dst_port" ) DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port" )) <= TO_UVEC(4000+i, 16);
+
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_sync" ) DOWNTO field_lo(c_hdr_field_arr, "usr_sync" )) <= slv(block_gen_src_out_arr(i).sync);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) DOWNTO field_lo(c_hdr_field_arr, "usr_bsn" )) <= block_gen_src_out_arr(i).bsn(59 DOWNTO 0);
+
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_hdr_word_align") DOWNTO field_lo(c_hdr_field_arr, "usr_hdr_word_align" )) <= TO_UVEC(0, 16);
+ hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_total_length" ) DOWNTO field_lo(c_hdr_field_arr, "ip_total_length" )) <= TO_UVEC(c_ip_length, 16);
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- UNB1 Control
+ -----------------------------------------------------------------------------
+ u_ctrl_unb1_board: ENTITY unb1_board_lib.ctrl_unb1_board
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_flash_model => FALSE,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_fw_version => c_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_use_phy => c_use_phy,
+ g_aux => c_unb1_board_aux,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_udp_offload => FALSE,
+ g_udp_offload_nof_streams => c_nof_10G_streams,
+ g_dp_clk_use_pll => TRUE,
+ g_xo_clk_use_pll => TRUE
+ )
+ PORT MAP(
+ mm_clk_out => mm_clk,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mm_locked => mm_locked,
+ mm_locked_out => mm_locked,
+
+ epcs_clk => epcs_clk,
+ epcs_clk_out => epcs_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => OPEN,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ cal_rec_clk => cal_clk,
+
+ this_chip_id => this_chip_id,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_tse_clk_out => eth1g_tse_clk,
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- System Info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- Uniboard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- UniBoard FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
+
+ -----------------------------------------------------------------------------
+ -- MM master
+ -----------------------------------------------------------------------------
+ u_inst_mmm_compaan_io_test_fn : ENTITY work.mmm_compaan_io_test_fn
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ PORT MAP(
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ pout_wdi => pout_wdi,
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+ reg_dp_offload_tx_mosi => reg_dp_offload_tx_mosi,
+ reg_dp_offload_tx_miso => reg_dp_offload_tx_miso,
+ reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+ reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+ reg_dp_offload_tx_hdr_ovr_mosi => reg_dp_offload_tx_hdr_ovr_mosi,
+ reg_dp_offload_tx_hdr_ovr_miso => reg_dp_offload_tx_hdr_ovr_miso,
+ reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+ reg_mdio_0_mosi => reg_mdio_0_mosi,
+ reg_mdio_0_miso => reg_mdio_0_miso,
+ reg_mdio_1_mosi => reg_mdio_1_mosi,
+ reg_mdio_1_miso => reg_mdio_1_miso,
+ reg_mdio_2_mosi => reg_mdio_2_mosi,
+ reg_mdio_2_miso => reg_mdio_2_miso,
+ reg_tr_10gbe_mosi => reg_tr_10gbe_mosi,
+ reg_tr_10gbe_miso => reg_tr_10gbe_miso,
+ reg_tr_xaui_mosi => reg_tr_xaui_mosi,
+ reg_tr_xaui_miso => reg_tr_xaui_miso,
+ reg_diagnostics_mosi => reg_diagnostics_mosi,
+ reg_diagnostics_miso => reg_diagnostics_miso,
+ reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+ reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+ reg_compaan_mosi => reg_compaan_mosi,
+ reg_compaan_miso => reg_compaan_miso
+ );
+
+ reg_mdio_mosi_arr(0) <= reg_mdio_0_mosi;
+ reg_mdio_mosi_arr(1) <= reg_mdio_1_mosi;
+ reg_mdio_mosi_arr(2) <= reg_mdio_2_mosi;
+
+ reg_mdio_0_miso <= reg_mdio_miso_arr(0);
+ reg_mdio_1_miso <= reg_mdio_miso_arr(1);
+ reg_mdio_2_miso <= reg_mdio_miso_arr(2);
+
+END str;
+
+
diff --git a/applications/compaan/designs/compaan_io_test_fn/src/vhdl/compaan_wrapper.vhd b/applications/compaan/designs/compaan_io_test_fn/src/vhdl/compaan_wrapper.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4ec85c47e29ba87cce4ed734f31b11a78cc7d13b
--- /dev/null
+++ b/applications/compaan/designs/compaan_io_test_fn/src/vhdl/compaan_wrapper.vhd
@@ -0,0 +1,212 @@
+------------------------------------------------------------------
+-- Wrapper between ASTRON and Compaan
+------------------------------------------------------------------
+LIBRARY IEEE, dp_lib, unb1_board_lib, io_test_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+
+ENTITY compaan_wrapper IS
+ GENERIC (
+ g_blocks_per_sync : NATURAL := 10
+ );
+ PORT (
+ -- Streaming sink (RX: ASTRON -> Compaan)
+ snk_out_arr : OUT t_dp_siso_arr(14 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ snk_in_arr : IN t_dp_sosi_arr(14 DOWNTO 0);
+
+ -- Streaming src (TX: Compaan -> ASTRON)
+ src_in_arr : IN t_dp_siso_arr(14 DOWNTO 0);
+ src_out_arr : OUT t_dp_sosi_arr(14 DOWNTO 0);
+
+ -- Compaan: Other
+ TEST_STOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0 );
+ TEST_ERROR : OUT STD_LOGIC_VECTOR(2 DOWNTO 0 );
+ TEST_FIFO_FULL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0 );
+ TEST_BLOCK_RD : OUT STD_LOGIC_VECTOR(2 DOWNTO 0 );
+ address : IN STD_LOGIC_VECTOR(18 DOWNTO 0 );
+ read_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0 );
+ read_en : IN STD_LOGIC;
+ write_en : IN STD_LOGIC;
+ write_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0 );
+
+ MM_CLK : IN STD_LOGIC;
+
+ KPN_CLK : IN STD_LOGIC;
+ KPN_RST : IN STD_LOGIC
+ );
+END compaan_wrapper;
+
+ARCHITECTURE STRUCTURE OF compaan_wrapper IS
+ -- Array without SOP and EOP to be send to a dp_block_gen
+ SIGNAL src_out_arr_nop : t_dp_sosi_arr(14 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
+
+ SIGNAL compaan_snk_out_arr : t_dp_siso_arr(14 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL compaan_snk_in_arr : t_dp_sosi_arr(14 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL compaan_src_in_arr : t_dp_siso_arr(14 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL compaan_src_out_arr : t_dp_sosi_arr(14 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+
+ SIGNAL control_vector_in : STD_LOGIC_VECTOR(14 DOWNTO 0);
+ SIGNAL control_vector_out : STD_LOGIC_VECTOR(14 DOWNTO 0);
+
+ SIGNAL i_compaan_src_in_rdy: STD_LOGIC_VECTOR(14 DOWNTO 0);
+
+BEGIN
+ gen_i_src_in_ready: FOR i IN 0 TO 14 GENERATE
+ i_compaan_src_in_rdy(i) <= NOT compaan_src_in_arr(i).ready;
+ END GENERATE;
+
+ -- Compaan ipcore
+ u_compaan_design: ENTITY io_test_lib.times_two_fn0
+ PORT MAP (
+ -- 10G XAUI 0
+ -- . RX
+ port0_in_Data => compaan_snk_in_arr(0).data(63 DOWNTO 0),
+ port0_in_Control => control_vector_in(0),
+ port0_in_Read => compaan_snk_out_arr(0).ready,
+ port0_in_Exists => compaan_snk_in_arr(0).valid,
+ -- . TX
+ port0_out_Data => compaan_src_out_arr(0).data(63 DOWNTO 0),
+ port0_out_Control => control_vector_out(0),
+ port0_out_Full => i_compaan_src_in_rdy(0),
+ port0_out_Write => compaan_src_out_arr(0).valid,
+
+ -- Terminal FN/BN0 Lane 0
+ -- . RX
+ port3_in_Data => compaan_snk_in_arr(3).data(63 DOWNTO 0),
+ port3_in_Control => control_vector_in(3),
+ port3_in_Read => compaan_snk_out_arr(3).ready,
+ port3_in_Exists => compaan_snk_in_arr(3).valid,
+ -- . TX
+ port3_out_Data => compaan_src_out_arr(3).data(63 DOWNTO 0),
+ port3_out_Control => control_vector_out(3),
+ port3_out_Full => i_compaan_src_in_rdy(3),
+ port3_out_Write => compaan_src_out_arr(3).valid,
+
+ -- Terminal FN/BN1 Lane 0
+ -- . RX
+ port6_in_Data => compaan_snk_in_arr(6).data(63 DOWNTO 0),
+ port6_in_Control => control_vector_in(6),
+ port6_in_Read => compaan_snk_out_arr(6).ready,
+ port6_in_Exists => compaan_snk_in_arr(6).valid,
+ -- . TX
+ port6_out_Data => compaan_src_out_arr(6).data(63 DOWNTO 0),
+ port6_out_Control => control_vector_out(6),
+ port6_out_Full => i_compaan_src_in_rdy(6),
+ port6_out_Write => compaan_src_out_arr(6).valid,
+
+ -- Compaan other
+ TEST_STOP => open,
+ TEST_ERROR => open,
+ TEST_FIFO_FULL => open,
+ TEST_BLOCK_RD => open,
+ address => address,
+ read_data => read_data,
+ read_en => read_en,
+ write_en => write_en,
+ write_data => write_data,
+
+ -- Compaan clocks
+ pci_clk => MM_CLK,
+ KPN_CLK => KPN_CLK,
+ KPN_RST => KPN_RST
+ );
+
+ -----------------------------------------------------------------------------
+ -- FIFO IN (ASTRON -> Compaan)
+ -----------------------------------------------------------------------------
+ gen_fifo_in: FOR i IN 0 TO 14 GENERATE
+ g_fifo_in: ENTITY dp_lib.dp_fifo_sc
+ GENERIC MAP(
+ g_data_w => 64,
+ g_bsn_w => 1,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_bsn => FALSE,
+ g_use_empty => FALSE,
+ g_use_channel => FALSE,
+ g_use_error => FALSE,
+ g_use_sync => FALSE,
+ g_use_ctrl => TRUE,
+ g_use_complex => FALSE,
+ g_fifo_size => 4*g_blocks_per_sync,
+ g_fifo_af_margin => 4,
+ g_fifo_rl => 0
+ )
+ PORT MAP(
+ rst => KPN_RST,
+ clk => KPN_CLK,
+ -- Monitor FIFO filling
+ wr_ful => open,
+ usedw => open,
+ rd_emp => open,
+ -- ST Sink
+ snk_out => snk_out_arr(i),
+ snk_in => snk_in_arr(i),
+ -- ST Source
+ src_in => compaan_snk_out_arr(i),
+ src_out => compaan_snk_in_arr(i)
+ );
+ END GENERATE;
+
+ -----------------------------------------------------------------------------
+ -- FIFO OUT (Compaan -> ASTRON)
+ -----------------------------------------------------------------------------
+ gen_fifo_out: FOR i IN 0 TO 14 GENERATE
+ g_fifo_out: ENTITY dp_lib.dp_fifo_sc
+ GENERIC MAP(
+ g_data_w => 64,
+ g_bsn_w => 1,
+ g_empty_w => 1,
+ g_channel_w => 1,
+ g_error_w => 1,
+ g_use_bsn => FALSE,
+ g_use_empty => FALSE,
+ g_use_channel => FALSE,
+ g_use_error => FALSE,
+ g_use_sync => FALSE,
+ g_use_ctrl => TRUE,
+ g_use_complex => FALSE,
+ g_fifo_size => 4*g_blocks_per_sync,
+ g_fifo_af_margin => 4,
+ g_fifo_rl => 0
+ )
+ PORT MAP(
+ rst => KPN_RST,
+ clk => KPN_CLK,
+ -- Monitor FIFO filling
+ wr_ful => open,
+ usedw => open,
+ rd_emp => open,
+ -- ST Sink
+ snk_out => compaan_src_in_arr(i),
+ snk_in => compaan_src_out_arr(i),
+ -- ST Source
+ src_in => c_dp_siso_rdy,
+ src_out => src_out_arr_nop(i)
+ );
+ END GENERATE;
+
+ -- Generate SOP, EOP for ASTRON
+ gen_pkg_signals: FOR i IN 0 TO 14 GENERATE
+ u_gen_signals : ENTITY dp_lib.dp_block_gen
+ GENERIC MAP(
+ g_use_src_in => FALSE,
+ g_nof_data => g_blocks_per_sync
+ )
+ PORT MAP(
+ rst => KPN_RST,
+ clk => KPN_CLK,
+ -- Streaming sink
+ snk_in => src_out_arr_nop(i),
+ -- Streaming source
+ src_in => src_in_arr(i),
+ src_out => src_out_arr(i),
+ -- MM control
+ en => '1'
+ );
+ END GENERATE;
+
+END ARCHITECTURE STRUCTURE;
+
diff --git a/applications/compaan/designs/compaan_io_test_fn/src/vhdl/mmm_compaan_io_test_fn.vhd b/applications/compaan/designs/compaan_io_test_fn/src/vhdl/mmm_compaan_io_test_fn.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..99e2f11de878e4844bb9946d97a94e85d7dd803a
--- /dev/null
+++ b/applications/compaan/designs/compaan_io_test_fn/src/vhdl/mmm_compaan_io_test_fn.vhd
@@ -0,0 +1,621 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- u_inst_mmm_compaan_io_test_fn : ENTITY work.mmm_compaan_io_test_fn
+-- GENERIC MAP(
+-- g_sim => g_sim,
+-- g_sim_unb_nr => g_sim_unb_nr,
+-- g_sim_node_nr => g_sim_node_nr
+-- )
+-- PORT MAP(
+-- mm_clk => mm_clk,
+-- mm_rst => mm_rst,
+-- pout_wdi => pout_wdi,
+-- reg_wdi_mosi => reg_wdi_mosi,
+-- reg_wdi_miso => reg_wdi_miso,
+-- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+-- reg_unb_system_info_miso => reg_unb_system_info_miso,
+-- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+-- rom_unb_system_info_miso => rom_unb_system_info_miso,
+-- reg_unb_sens_mosi => reg_unb_sens_mosi,
+-- reg_unb_sens_miso => reg_unb_sens_miso,
+-- reg_ppsh_mosi => reg_ppsh_mosi,
+-- reg_ppsh_miso => reg_ppsh_miso,
+-- eth1g_mm_rst => eth1g_mm_rst,
+-- eth1g_reg_interrupt => eth1g_reg_interrupt,
+-- eth1g_ram_mosi => eth1g_ram_mosi,
+-- eth1g_ram_miso => eth1g_ram_miso,
+-- eth1g_reg_mosi => eth1g_reg_mosi,
+-- eth1g_reg_miso => eth1g_reg_miso,
+-- eth1g_tse_mosi => eth1g_tse_mosi,
+-- eth1g_tse_miso => eth1g_tse_miso,
+-- reg_epcs_mosi => reg_epcs_mosi,
+-- reg_epcs_miso => reg_epcs_miso,
+-- reg_remu_mosi => reg_remu_mosi,
+-- reg_remu_miso => reg_remu_miso,
+-- reg_dp_offload_tx_mosi => reg_dp_offload_tx_mosi,
+-- reg_dp_offload_tx_miso => reg_dp_offload_tx_miso,
+-- reg_dp_offload_tx_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
+-- reg_dp_offload_tx_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
+-- reg_dp_offload_tx_hdr_ovr_mosi => reg_dp_offload_tx_hdr_ovr_mosi,
+-- reg_dp_offload_tx_hdr_ovr_miso => reg_dp_offload_tx_hdr_ovr_miso,
+-- reg_dp_offload_rx_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+-- reg_dp_offload_rx_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+-- reg_mdio_0_mosi => reg_mdio_0_mosi,
+-- reg_mdio_0_miso => reg_mdio_0_miso,
+-- reg_mdio_1_mosi => reg_mdio_1_mosi,
+-- reg_mdio_1_miso => reg_mdio_1_miso,
+-- reg_mdio_2_mosi => reg_mdio_2_mosi,
+-- reg_mdio_2_miso => reg_mdio_2_miso,
+-- reg_tr_10gbe_mosi => reg_tr_10gbe_mosi,
+-- reg_tr_10gbe_miso => reg_tr_10gbe_miso,
+-- reg_tr_xaui_mosi => reg_tr_xaui_mosi,
+-- reg_tr_xaui_miso => reg_tr_xaui_miso,
+-- reg_diagnostics_mosi => reg_diagnostics_mosi,
+-- reg_diagnostics_miso => reg_diagnostics_miso,
+-- reg_tr_nonbonded_mosi => reg_tr_nonbonded_mosi,
+-- reg_tr_nonbonded_miso => reg_tr_nonbonded_miso,
+-- reg_compaan_mosi => reg_compaan_mosi,
+-- reg_compaan_miso => reg_compaan_miso
+-- );
+--
+-- SIGNAL reg_wdi_mosi : t_mem_mosi;
+-- SIGNAL reg_wdi_miso : t_mem_miso;
+-- SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
+-- SIGNAL reg_unb_system_info_miso : t_mem_miso;
+-- SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
+-- SIGNAL rom_unb_system_info_miso : t_mem_miso;
+-- SIGNAL reg_unb_sens_mosi : t_mem_mosi;
+-- SIGNAL reg_unb_sens_miso : t_mem_miso;
+-- SIGNAL reg_ppsh_mosi : t_mem_mosi;
+-- SIGNAL reg_ppsh_miso : t_mem_miso;
+-- SIGNAL eth1g_ram_mosi : t_mem_mosi;
+-- SIGNAL eth1g_ram_miso : t_mem_miso;
+-- SIGNAL eth1g_reg_mosi : t_mem_mosi;
+-- SIGNAL eth1g_reg_miso : t_mem_miso;
+-- SIGNAL eth1g_tse_mosi : t_mem_mosi;
+-- SIGNAL eth1g_tse_miso : t_mem_miso;
+-- SIGNAL reg_epcs_mosi : t_mem_mosi;
+-- SIGNAL reg_epcs_miso : t_mem_miso;
+-- SIGNAL reg_remu_mosi : t_mem_mosi;
+-- SIGNAL reg_remu_miso : t_mem_miso;
+-- SIGNAL reg_dp_offload_tx_mosi : t_mem_mosi;
+-- SIGNAL reg_dp_offload_tx_miso : t_mem_miso;
+-- SIGNAL reg_dp_offload_tx_hdr_dat_mosi : t_mem_mosi;
+-- SIGNAL reg_dp_offload_tx_hdr_dat_miso : t_mem_miso;
+-- SIGNAL reg_dp_offload_tx_hdr_ovr_mosi : t_mem_mosi;
+-- SIGNAL reg_dp_offload_tx_hdr_ovr_miso : t_mem_miso;
+-- SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
+-- SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
+-- SIGNAL reg_mdio_0_mosi : t_mem_mosi;
+-- SIGNAL reg_mdio_0_miso : t_mem_miso;
+-- SIGNAL reg_mdio_1_mosi : t_mem_mosi;
+-- SIGNAL reg_mdio_1_miso : t_mem_miso;
+-- SIGNAL reg_mdio_2_mosi : t_mem_mosi;
+-- SIGNAL reg_mdio_2_miso : t_mem_miso;
+-- SIGNAL reg_tr_10gbe_mosi : t_mem_mosi;
+-- SIGNAL reg_tr_10gbe_miso : t_mem_miso;
+-- SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
+-- SIGNAL reg_tr_xaui_miso : t_mem_miso;
+-- SIGNAL reg_diagnostics_mosi : t_mem_mosi;
+-- SIGNAL reg_diagnostics_miso : t_mem_miso;
+-- SIGNAL reg_tr_nonbonded_mosi : t_mem_mosi;
+-- SIGNAL reg_tr_nonbonded_miso : t_mem_miso;
+-- SIGNAL reg_compaan_mosi : t_mem_mosi;
+-- SIGNAL reg_compaan_miso : t_mem_miso;
+--
+LIBRARY IEEE, common_lib, unb1_board_lib, mm_lib, eth_lib, technology_lib, tech_tse_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE common_lib.common_network_total_header_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
+
+ENTITY mmm_compaan_io_test_fn IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0
+ );
+ PORT (
+ mm_clk : IN STD_LOGIC := '1';
+ mm_rst : IN STD_LOGIC := '1';
+ pout_wdi : OUT STD_LOGIC := '1';
+ reg_wdi_mosi : OUT t_mem_mosi;
+ reg_wdi_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_unb_system_info_mosi : OUT t_mem_mosi;
+ reg_unb_system_info_miso : IN t_mem_miso := c_mem_miso_rst;
+ rom_unb_system_info_mosi : OUT t_mem_mosi;
+ rom_unb_system_info_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_unb_sens_mosi : OUT t_mem_mosi;
+ reg_unb_sens_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_ppsh_mosi : OUT t_mem_mosi;
+ reg_ppsh_miso : IN t_mem_miso := c_mem_miso_rst;
+ eth1g_mm_rst : OUT STD_LOGIC;
+ eth1g_reg_interrupt : IN STD_LOGIC;
+ eth1g_ram_mosi : OUT t_mem_mosi;
+ eth1g_ram_miso : IN t_mem_miso := c_mem_miso_rst;
+ eth1g_reg_mosi : OUT t_mem_mosi;
+ eth1g_reg_miso : IN t_mem_miso := c_mem_miso_rst;
+ eth1g_tse_mosi : OUT t_mem_mosi;
+ eth1g_tse_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_epcs_mosi : OUT t_mem_mosi;
+ reg_epcs_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_remu_mosi : OUT t_mem_mosi;
+ reg_remu_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_dp_offload_tx_mosi : OUT t_mem_mosi;
+ reg_dp_offload_tx_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_dp_offload_tx_hdr_dat_mosi : OUT t_mem_mosi;
+ reg_dp_offload_tx_hdr_dat_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_dp_offload_tx_hdr_ovr_mosi : OUT t_mem_mosi;
+ reg_dp_offload_tx_hdr_ovr_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_dp_offload_rx_hdr_dat_mosi : OUT t_mem_mosi;
+ reg_dp_offload_rx_hdr_dat_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_mdio_0_mosi : OUT t_mem_mosi;
+ reg_mdio_0_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_mdio_1_mosi : OUT t_mem_mosi;
+ reg_mdio_1_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_mdio_2_mosi : OUT t_mem_mosi;
+ reg_mdio_2_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_tr_10gbe_mosi : OUT t_mem_mosi;
+ reg_tr_10gbe_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_tr_xaui_mosi : OUT t_mem_mosi;
+ reg_tr_xaui_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_diagnostics_mosi : OUT t_mem_mosi;
+ reg_diagnostics_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_tr_nonbonded_mosi : OUT t_mem_mosi;
+ reg_tr_nonbonded_miso : IN t_mem_miso := c_mem_miso_rst;
+ reg_compaan_mosi : OUT t_mem_mosi;
+ reg_compaan_miso : IN t_mem_miso := c_mem_miso_rst
+ );
+END ENTITY mmm_compaan_io_test_fn;
+
+ARCHITECTURE str OF mmm_compaan_io_test_fn IS
+
+ CONSTANT c_sim_node_type : STRING(1 TO 2) := sel_a_b(g_sim_node_nr<4, "FN", "BN");
+ CONSTANT c_sim_node_nr : NATURAL := sel_a_b(c_sim_node_type="BN", g_sim_node_nr-4, g_sim_node_nr);
+ CONSTANT c_sim_eth_src_mac : STD_LOGIC_VECTOR(c_network_eth_mac_slv'RANGE) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
+ CONSTANT c_sim_eth_control_rx_en : NATURAL := 2**c_eth_mm_reg_control_bi.rx_en;
+
+ SIGNAL sim_eth_mm_bus_switch : STD_LOGIC ;
+ SIGNAL sim_eth_psc_access : STD_LOGIC ;
+ SIGNAL i_eth1g_reg_mosi : t_mem_mosi;
+ SIGNAL i_eth1g_reg_miso : t_mem_miso;
+ SIGNAL mm_rst_n : STD_LOGIC ;
+ SIGNAL sim_eth1g_reg_mosi : t_mem_mosi;
+
+ COMPONENT mm_file IS
+ GENERIC (
+ g_file_prefix : STRING ;
+ g_mm_clk_period : TIME := 8 ns;
+ g_update_on_change : BOOLEAN := FALSE;
+ g_mm_rd_latency : NATURAL := 1
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ mm_master_out : OUT t_mem_mosi := c_mem_mosi_rst;
+ mm_master_in : IN t_mem_miso := c_mem_miso_rst
+ );
+ END COMPONENT mm_file;
+
+ COMPONENT qsys_compaan_io_test_fn IS
+ PORT (
+ reg_dp_offload_tx_hdr_dat_write_export : out std_logic;
+ reg_dp_offload_tx_hdr_ovr_reset_export : out std_logic;
+ eth1g_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_dp_offload_tx_reset_export : out std_logic;
+ reset_in_reset_n : in std_logic := '0';
+ reg_diagnostics_write_export : out std_logic;
+ pio_pps_address_export : out std_logic;
+ pio_system_info_address_export : out std_logic_vector(4 downto 0);
+ pio_pps_reset_export : out std_logic;
+ eth1g_tse_writedata_export : out std_logic_vector(31 downto 0);
+ reg_mdio_1_clk_export : out std_logic;
+ reg_tr_10gbe_write_export : out std_logic;
+ eth1g_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ eth1g_ram_address_export : out std_logic_vector(9 downto 0);
+ reg_mdio_0_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ pio_pps_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_dp_offload_rx_hdr_dat_clk_export : out std_logic;
+ eth1g_reg_writedata_export : out std_logic_vector(31 downto 0);
+ pio_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ reg_unb_sens_reset_export : out std_logic;
+ reg_tr_xaui_write_export : out std_logic;
+ eth1g_tse_address_export : out std_logic_vector(9 downto 0);
+ clk_in_clk : in std_logic := '0';
+ reg_tr_xaui_writedata_export : out std_logic_vector(31 downto 0);
+ reg_wdi_reset_export : out std_logic;
+ reg_dp_offload_tx_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_dp_offload_tx_read_export : out std_logic;
+ rom_system_info_clk_export : out std_logic;
+ reg_unb_sens_read_export : out std_logic;
+ reg_compaan_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_unb_sens_write_export : out std_logic;
+ reg_dp_offload_rx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_mdio_0_clk_export : out std_logic;
+ eth1g_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ eth1g_ram_write_export : out std_logic;
+ reg_dp_offload_tx_write_export : out std_logic;
+ reg_diagnostics_writedata_export : out std_logic_vector(31 downto 0);
+ reg_dp_offload_tx_hdr_ovr_read_export : out std_logic;
+ reg_tr_xaui_address_export : out std_logic_vector(10 downto 0);
+ reg_unb_sens_clk_export : out std_logic;
+ reg_tr_nonbonded_clk_export : out std_logic;
+ reg_compaan_writedata_export : out std_logic_vector(31 downto 0);
+ reg_dp_offload_tx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0);
+ reg_mdio_0_write_export : out std_logic;
+ reg_wdi_read_export : out std_logic;
+ reg_dp_offload_rx_hdr_dat_write_export : out std_logic;
+ eth1g_ram_read_export : out std_logic;
+ reg_dp_offload_rx_hdr_dat_read_export : out std_logic;
+ eth1g_reg_read_export : out std_logic;
+ reg_tr_10gbe_read_export : out std_logic;
+ reg_dp_offload_rx_hdr_dat_reset_export : out std_logic;
+ eth1g_tse_write_export : out std_logic;
+ reg_unb_sens_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_dp_offload_tx_writedata_export : out std_logic_vector(31 downto 0);
+ reg_mdio_2_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_tr_xaui_waitrequest_export : in std_logic := '0';
+ pio_pps_clk_export : out std_logic;
+ eth1g_reg_address_export : out std_logic_vector(3 downto 0);
+ pio_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_dp_offload_tx_hdr_ovr_address_export : out std_logic_vector(4 downto 0);
+ rom_system_info_writedata_export : out std_logic_vector(31 downto 0);
+ reg_tr_xaui_reset_export : out std_logic;
+ reg_compaan_clk_export : out std_logic;
+ reg_dp_offload_tx_hdr_dat_reset_export : out std_logic;
+ reg_dp_offload_tx_hdr_dat_address_export : out std_logic_vector(5 downto 0);
+ reg_tr_nonbonded_reset_export : out std_logic;
+ reg_mdio_2_read_export : out std_logic;
+ reg_mdio_1_writedata_export : out std_logic_vector(31 downto 0);
+ reg_dp_offload_tx_hdr_ovr_writedata_export : out std_logic_vector(31 downto 0);
+ reg_dp_offload_tx_hdr_ovr_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_mdio_2_reset_export : out std_logic;
+ reg_tr_nonbonded_address_export : out std_logic_vector(3 downto 0);
+ reg_tr_10gbe_writedata_export : out std_logic_vector(31 downto 0);
+ reg_wdi_address_export : out std_logic;
+ pio_system_info_write_export : out std_logic;
+ reg_tr_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_tr_nonbonded_writedata_export : out std_logic_vector(31 downto 0);
+ reg_tr_nonbonded_write_export : out std_logic;
+ pio_pps_write_export : out std_logic;
+ rom_system_info_write_export : out std_logic;
+ rom_system_info_read_export : out std_logic;
+ reg_dp_offload_tx_hdr_dat_clk_export : out std_logic;
+ reg_diagnostics_address_export : out std_logic_vector(5 downto 0);
+ reg_dp_offload_rx_hdr_dat_address_export : out std_logic_vector(6 downto 0);
+ reg_dp_offload_rx_hdr_dat_writedata_export : out std_logic_vector(31 downto 0);
+ reg_mdio_2_clk_export : out std_logic;
+ reg_tr_nonbonded_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_mdio_1_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_mdio_2_address_export : out std_logic_vector(2 downto 0);
+ eth1g_tse_read_export : out std_logic;
+ reg_tr_xaui_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_mdio_1_read_export : out std_logic;
+ reg_unb_sens_writedata_export : out std_logic_vector(31 downto 0);
+ eth1g_ram_writedata_export : out std_logic_vector(31 downto 0);
+ reg_compaan_address_export : out std_logic_vector(18 downto 0);
+ reg_dp_offload_tx_address_export : out std_logic;
+ reg_mdio_2_writedata_export : out std_logic_vector(31 downto 0);
+ reg_tr_nonbonded_read_export : out std_logic;
+ out_port_from_the_pio_debug_wave : out std_logic_vector(31 downto 0);
+ reg_mdio_1_address_export : out std_logic_vector(2 downto 0);
+ reg_tr_xaui_read_export : out std_logic;
+ reg_wdi_writedata_export : out std_logic_vector(31 downto 0);
+ pio_system_info_reset_export : out std_logic;
+ pio_system_info_read_export : out std_logic;
+ reg_mdio_1_reset_export : out std_logic;
+ reg_wdi_clk_export : out std_logic;
+ reg_dp_offload_tx_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ eth1g_mm_rst_export : out std_logic;
+ reg_diagnostics_read_export : out std_logic;
+ reg_tr_10gbe_reset_export : out std_logic;
+ reg_compaan_read_export : out std_logic;
+ reg_diagnostics_reset_export : out std_logic;
+ reg_tr_10gbe_clk_export : out std_logic;
+ reg_dp_offload_tx_hdr_ovr_clk_export : out std_logic;
+ out_port_from_the_pio_wdi : out std_logic;
+ eth1g_reg_write_export : out std_logic;
+ reg_mdio_1_write_export : out std_logic;
+ reg_compaan_reset_export : out std_logic;
+ reg_dp_offload_tx_hdr_dat_read_export : out std_logic;
+ rom_system_info_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_tr_xaui_clk_export : out std_logic;
+ reg_wdi_write_export : out std_logic;
+ reg_wdi_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_compaan_write_export : out std_logic;
+ pio_pps_read_export : out std_logic;
+ reg_mdio_2_write_export : out std_logic;
+ reg_dp_offload_tx_clk_export : out std_logic;
+ pio_system_info_clk_export : out std_logic;
+ reg_tr_10gbe_address_export : out std_logic_vector(14 downto 0);
+ pio_pps_writedata_export : out std_logic_vector(31 downto 0);
+ reg_mdio_0_writedata_export : out std_logic_vector(31 downto 0);
+ eth1g_tse_waitrequest_export : in std_logic := '0';
+ reg_tr_10gbe_waitrequest_export : in std_logic := '0';
+ eth1g_mm_clk_export : out std_logic;
+ rom_system_info_reset_export : out std_logic;
+ reg_unb_sens_address_export : out std_logic_vector(2 downto 0);
+ reg_mdio_0_reset_export : out std_logic;
+ rom_system_info_address_export : out std_logic_vector(9 downto 0);
+ eth1g_irq_export : in std_logic := '0';
+ reg_mdio_0_address_export : out std_logic_vector(2 downto 0);
+ reg_diagnostics_readdata_export : in std_logic_vector(31 downto 0) := (others => '0');
+ reg_dp_offload_tx_hdr_ovr_write_export : out std_logic;
+ reg_diagnostics_clk_export : out std_logic;
+ reg_mdio_0_read_export : out std_logic
+ );
+ END COMPONENT qsys_compaan_io_test_fn;
+
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- MM <-> file I/O for simulation. The files are created in $UPE/sim.
+ ----------------------------------------------------------------------------
+ gen_mm_file_io : IF g_sim = TRUE GENERATE
+ u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
+ PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
+ PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
+ PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
+ PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
+ PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_eth1g_ram : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_RAM")
+ PORT MAP(mm_rst, mm_clk, eth1g_ram_mosi, eth1g_ram_miso );
+ u_mm_file_eth1g_reg : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
+ PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ u_mm_file_eth1g_tse : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ETH1G_TSE")
+ PORT MAP(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
+ u_mm_file_reg_epcs : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_EPCS")
+ PORT MAP(mm_rst, mm_clk, reg_epcs_mosi, reg_epcs_miso );
+ u_mm_file_reg_remu : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_REMU")
+ PORT MAP(mm_rst, mm_clk, reg_remu_mosi, reg_remu_miso );
+ u_mm_file_reg_dp_offload_tx : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_mosi, reg_dp_offload_tx_miso );
+ u_mm_file_reg_dp_offload_tx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_DAT")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_dat_mosi, reg_dp_offload_tx_hdr_dat_miso );
+ u_mm_file_reg_dp_offload_tx_hdr_ovr : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_TX_HDR_OVR")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_tx_hdr_ovr_mosi, reg_dp_offload_tx_hdr_ovr_miso );
+ u_mm_file_reg_dp_offload_rx_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_HDR_DAT")
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_hdr_dat_mosi, reg_dp_offload_rx_hdr_dat_miso );
+ u_mm_file_reg_mdio_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_MDIO_0")
+ PORT MAP(mm_rst, mm_clk, reg_mdio_0_mosi, reg_mdio_0_miso );
+ u_mm_file_reg_mdio_1 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_MDIO_1")
+ PORT MAP(mm_rst, mm_clk, reg_mdio_1_mosi, reg_mdio_1_miso );
+ u_mm_file_reg_mdio_2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_MDIO_2")
+ PORT MAP(mm_rst, mm_clk, reg_mdio_2_mosi, reg_mdio_2_miso );
+ u_mm_file_reg_tr_10gbe : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE")
+ PORT MAP(mm_rst, mm_clk, reg_tr_10gbe_mosi, reg_tr_10gbe_miso );
+ u_mm_file_reg_tr_xaui : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI")
+ PORT MAP(mm_rst, mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso );
+ u_mm_file_reg_diagnostics : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAGNOSTICS")
+ PORT MAP(mm_rst, mm_clk, reg_diagnostics_mosi, reg_diagnostics_miso );
+ u_mm_file_reg_tr_nonbonded : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_NONBONDED")
+ PORT MAP(mm_rst, mm_clk, reg_tr_nonbonded_mosi, reg_tr_nonbonded_miso );
+ u_mm_file_reg_compaan : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_COMPAAN")
+ PORT MAP(mm_rst, mm_clk, reg_compaan_mosi, reg_compaan_miso );
+ ----------------------------------------------------------------------------
+ -- 1GbE setup sequence normally performed by unb_os@NIOS
+ ----------------------------------------------------------------------------
+ eth1g_mm_rst <= '1', '0' AFTER 40 ns;
+ p_eth_setup : PROCESS
+ BEGIN
+ sim_eth_mm_bus_switch <= '1';
+ eth1g_tse_mosi.wr <= '0';
+ eth1g_tse_mosi.rd <= '0';
+ WAIT FOR 400 ns;
+ WAIT UNTIL rising_edge(mm_clk);
+ proc_tech_tse_setup(c_tech_stratixiv, FALSE, c_tech_tse_tx_fifo_depth, c_tech_tse_rx_fifo_depth, c_tech_tse_tx_ready_latency, c_sim_eth_src_mac, sim_eth_psc_access, mm_clk, eth1g_tse_miso, eth1g_tse_mosi);
+ -- Enable RX
+ proc_mem_mm_bus_wr(c_eth_reg_control_wi+0, c_sim_eth_control_rx_en, mm_clk, eth1g_reg_miso, sim_eth1g_reg_mosi); -- control rx en
+ sim_eth_mm_bus_switch <= '0';
+ WAIT;
+ END PROCESS;
+
+ p_switch : PROCESS(sim_eth_mm_bus_switch, sim_eth1g_reg_mosi, i_eth1g_reg_mosi)
+ BEGIN
+ IF sim_eth_mm_bus_switch = '1' THEN
+ eth1g_reg_mosi <= sim_eth1g_reg_mosi;
+ ELSE
+ eth1g_reg_mosi <= i_eth1g_reg_mosi;
+ END IF;
+ END PROCESS;
+ ----------------------------------------------------------------------------
+ -- Procedure that polls a sim control file that can be used to e.g. get
+ -- the simulation time in ns
+ ----------------------------------------------------------------------------
+ mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
+
+ END GENERATE;
+ ----------------------------------------------------------------------------
+ -- SOPC or QSYS for synthesis
+ ----------------------------------------------------------------------------
+ gen_qsys_compaan_io_test_fn : IF g_sim = FALSE GENERATE
+
+ mm_rst_n <= NOT(mm_rst);
+
+ u_qsys_compaan_io_test_fn : qsys_compaan_io_test_fn
+ PORT MAP(
+ clk_in_clk => mm_clk,
+ eth1g_irq_export => eth1g_reg_interrupt,
+ eth1g_mm_clk_export => OPEN,
+ eth1g_mm_rst_export => eth1g_mm_rst,
+ eth1g_ram_address_export => eth1g_ram_mosi.address(9 DOWNTO 0),
+ eth1g_ram_read_export => eth1g_ram_mosi.rd,
+ eth1g_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
+ eth1g_ram_write_export => eth1g_ram_mosi.wr,
+ eth1g_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ eth1g_reg_address_export => eth1g_reg_mosi.address(3 DOWNTO 0),
+ eth1g_reg_read_export => eth1g_reg_mosi.rd,
+ eth1g_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
+ eth1g_reg_write_export => eth1g_reg_mosi.wr,
+ eth1g_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ eth1g_tse_address_export => eth1g_tse_mosi.address(9 DOWNTO 0),
+ eth1g_tse_read_export => eth1g_tse_mosi.rd,
+ eth1g_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
+ eth1g_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
+ eth1g_tse_write_export => eth1g_tse_mosi.wr,
+ eth1g_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ out_port_from_the_pio_debug_wave => OPEN,
+ out_port_from_the_pio_wdi => pout_wdi,
+ pio_pps_address_export => reg_ppsh_mosi.address(0),
+ pio_pps_clk_export => OPEN,
+ pio_pps_read_export => reg_ppsh_mosi.rd,
+ pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
+ pio_pps_reset_export => OPEN,
+ pio_pps_write_export => reg_ppsh_mosi.wr,
+ pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ pio_system_info_address_export => reg_unb_system_info_mosi.address(4 DOWNTO 0),
+ pio_system_info_clk_export => OPEN,
+ pio_system_info_read_export => reg_unb_system_info_mosi.rd,
+ pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ pio_system_info_reset_export => OPEN,
+ pio_system_info_write_export => reg_unb_system_info_mosi.wr,
+ pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_compaan_address_export => reg_compaan_mosi.address(18 DOWNTO 0),
+ reg_compaan_clk_export => OPEN,
+ reg_compaan_read_export => reg_compaan_mosi.rd,
+ reg_compaan_readdata_export => reg_compaan_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_compaan_reset_export => OPEN,
+ reg_compaan_write_export => reg_compaan_mosi.wr,
+ reg_compaan_writedata_export => reg_compaan_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_diagnostics_address_export => reg_diagnostics_mosi.address(5 DOWNTO 0),
+ reg_diagnostics_clk_export => OPEN,
+ reg_diagnostics_read_export => reg_diagnostics_mosi.rd,
+ reg_diagnostics_readdata_export => reg_diagnostics_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_diagnostics_reset_export => OPEN,
+ reg_diagnostics_write_export => reg_diagnostics_mosi.wr,
+ reg_diagnostics_writedata_export => reg_diagnostics_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_rx_hdr_dat_address_export => reg_dp_offload_rx_hdr_dat_mosi.address(6 DOWNTO 0),
+ reg_dp_offload_rx_hdr_dat_clk_export => OPEN,
+ reg_dp_offload_rx_hdr_dat_read_export => reg_dp_offload_rx_hdr_dat_mosi.rd,
+ reg_dp_offload_rx_hdr_dat_readdata_export => reg_dp_offload_rx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_rx_hdr_dat_reset_export => OPEN,
+ reg_dp_offload_rx_hdr_dat_write_export => reg_dp_offload_rx_hdr_dat_mosi.wr,
+ reg_dp_offload_rx_hdr_dat_writedata_export => reg_dp_offload_rx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_address_export => reg_dp_offload_tx_mosi.address(0),
+ reg_dp_offload_tx_clk_export => OPEN,
+ reg_dp_offload_tx_hdr_dat_address_export => reg_dp_offload_tx_hdr_dat_mosi.address(5 DOWNTO 0),
+ reg_dp_offload_tx_hdr_dat_clk_export => OPEN,
+ reg_dp_offload_tx_hdr_dat_read_export => reg_dp_offload_tx_hdr_dat_mosi.rd,
+ reg_dp_offload_tx_hdr_dat_readdata_export => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_hdr_dat_reset_export => OPEN,
+ reg_dp_offload_tx_hdr_dat_write_export => reg_dp_offload_tx_hdr_dat_mosi.wr,
+ reg_dp_offload_tx_hdr_dat_writedata_export => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_hdr_ovr_address_export => reg_dp_offload_tx_hdr_ovr_mosi.address(4 DOWNTO 0),
+ reg_dp_offload_tx_hdr_ovr_clk_export => OPEN,
+ reg_dp_offload_tx_hdr_ovr_read_export => reg_dp_offload_tx_hdr_ovr_mosi.rd,
+ reg_dp_offload_tx_hdr_ovr_readdata_export => reg_dp_offload_tx_hdr_ovr_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_hdr_ovr_reset_export => OPEN,
+ reg_dp_offload_tx_hdr_ovr_write_export => reg_dp_offload_tx_hdr_ovr_mosi.wr,
+ reg_dp_offload_tx_hdr_ovr_writedata_export => reg_dp_offload_tx_hdr_ovr_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_read_export => reg_dp_offload_tx_mosi.rd,
+ reg_dp_offload_tx_readdata_export => reg_dp_offload_tx_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_dp_offload_tx_reset_export => OPEN,
+ reg_dp_offload_tx_write_export => reg_dp_offload_tx_mosi.wr,
+ reg_dp_offload_tx_writedata_export => reg_dp_offload_tx_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_mdio_0_address_export => reg_mdio_0_mosi.address(2 DOWNTO 0),
+ reg_mdio_0_clk_export => OPEN,
+ reg_mdio_0_read_export => reg_mdio_0_mosi.rd,
+ reg_mdio_0_readdata_export => reg_mdio_0_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_mdio_0_reset_export => OPEN,
+ reg_mdio_0_write_export => reg_mdio_0_mosi.wr,
+ reg_mdio_0_writedata_export => reg_mdio_0_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_mdio_1_address_export => reg_mdio_1_mosi.address(2 DOWNTO 0),
+ reg_mdio_1_clk_export => OPEN,
+ reg_mdio_1_read_export => reg_mdio_1_mosi.rd,
+ reg_mdio_1_readdata_export => reg_mdio_1_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_mdio_1_reset_export => OPEN,
+ reg_mdio_1_write_export => reg_mdio_1_mosi.wr,
+ reg_mdio_1_writedata_export => reg_mdio_1_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_mdio_2_address_export => reg_mdio_2_mosi.address(2 DOWNTO 0),
+ reg_mdio_2_clk_export => OPEN,
+ reg_mdio_2_read_export => reg_mdio_2_mosi.rd,
+ reg_mdio_2_readdata_export => reg_mdio_2_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_mdio_2_reset_export => OPEN,
+ reg_mdio_2_write_export => reg_mdio_2_mosi.wr,
+ reg_mdio_2_writedata_export => reg_mdio_2_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_tr_10gbe_address_export => reg_tr_10gbe_mosi.address(14 DOWNTO 0),
+ reg_tr_10gbe_clk_export => OPEN,
+ reg_tr_10gbe_read_export => reg_tr_10gbe_mosi.rd,
+ reg_tr_10gbe_readdata_export => reg_tr_10gbe_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_tr_10gbe_reset_export => OPEN,
+ reg_tr_10gbe_waitrequest_export => reg_tr_10gbe_miso.waitrequest,
+ reg_tr_10gbe_write_export => reg_tr_10gbe_mosi.wr,
+ reg_tr_10gbe_writedata_export => reg_tr_10gbe_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_tr_nonbonded_address_export => reg_tr_nonbonded_mosi.address(3 DOWNTO 0),
+ reg_tr_nonbonded_clk_export => OPEN,
+ reg_tr_nonbonded_read_export => reg_tr_nonbonded_mosi.rd,
+ reg_tr_nonbonded_readdata_export => reg_tr_nonbonded_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_tr_nonbonded_reset_export => OPEN,
+ reg_tr_nonbonded_write_export => reg_tr_nonbonded_mosi.wr,
+ reg_tr_nonbonded_writedata_export => reg_tr_nonbonded_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_tr_xaui_address_export => reg_tr_xaui_mosi.address(10 DOWNTO 0),
+ reg_tr_xaui_clk_export => OPEN,
+ reg_tr_xaui_read_export => reg_tr_xaui_mosi.rd,
+ reg_tr_xaui_readdata_export => reg_tr_xaui_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_tr_xaui_reset_export => OPEN,
+ reg_tr_xaui_waitrequest_export => reg_tr_xaui_miso.waitrequest,
+ reg_tr_xaui_write_export => reg_tr_xaui_mosi.wr,
+ reg_tr_xaui_writedata_export => reg_tr_xaui_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_unb_sens_address_export => reg_unb_sens_mosi.address(2 DOWNTO 0),
+ reg_unb_sens_clk_export => OPEN,
+ reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
+ reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_unb_sens_reset_export => OPEN,
+ reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
+ reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reg_wdi_address_export => reg_wdi_mosi.address(0),
+ reg_wdi_clk_export => OPEN,
+ reg_wdi_read_export => reg_wdi_mosi.rd,
+ reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
+ reg_wdi_reset_export => OPEN,
+ reg_wdi_write_export => reg_wdi_mosi.wr,
+ reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ reset_in_reset_n => mm_rst_n,
+ rom_system_info_address_export => rom_unb_system_info_mosi.address(9 DOWNTO 0),
+ rom_system_info_clk_export => OPEN,
+ rom_system_info_read_export => rom_unb_system_info_mosi.rd,
+ rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
+ rom_system_info_reset_export => OPEN,
+ rom_system_info_write_export => rom_unb_system_info_mosi.wr,
+ rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0)
+ );
+ END GENERATE;
+
+END str;
diff --git a/applications/compaan/designs/compaan_io_test_fn/tb/python/tc_compaan_io_test.py b/applications/compaan/designs/compaan_io_test_fn/tb/python/tc_compaan_io_test.py
new file mode 100644
index 0000000000000000000000000000000000000000..e98e15df780d9385115a23b919ab47618f6963d4
--- /dev/null
+++ b/applications/compaan/designs/compaan_io_test_fn/tb/python/tc_compaan_io_test.py
@@ -0,0 +1,174 @@
+#! /usr/bin/env python
+###############################################################################
+#
+# Copyright (dC) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+# Purpose:
+# . Test Compaan's capability to send data to a terminal
+
+
+from common import *
+import sys
+import test_case
+import node_io
+import pi_diag_block_gen
+import pi_diag_data_buffer
+import pi_dp_offload_tx_hdr_dat_compaan_unb1_10g_terminal
+import pi_eth
+import pi_compaan
+from eth import *
+
+################################################################################
+## Constants and variables
+################################################################################
+# System definitions
+c_10g_data_w = 32 # <= 32 for terminal
+c_blocksize = 8 # = frame_len
+c_nof_blocks_per_sync = 8
+c_test_loopback = True
+c_only_set_dpotx = False
+
+# Block gen definitions
+c_bg_ram_size = 32
+c_bg_nof_streams = 1
+c_bg_gap_size = 3000
+c_write_block_gen = True
+
+# UDP header definitions
+eth_src_mac = 0x2286080008 # 10G MAC base address for UniBoard
+eth_dst_mac = 0x074306C700 #0x00074306C700 # 10G MAC address DOP36
+ip_src_addr_fn0 = 0xc0a80164 # 0xc0a80164 = 192.168.1.100
+ip_src_addr_fn1 = 0xc0a80165 # 0xc0a80165 = 192.168.1.101
+ip_src_addr_fn2 = 0xc0a80166 # 0xc0a80164 = 192.168.1.102
+ip_src_addr_fn3 = 0xc0a80167 # 0xc0a80165 = 192.168.1.103
+ip_dst_addr = 0xc0a80102 # 0xc0a80102 = 192.168.1.2 = IP-address 10G in DOP36
+
+# Instantiate testcase and IO
+tc = test_case.Testcase('TB -', '')
+io = node_io.NodeIO(tc.nodeImages, tc.base_ip)
+
+# Instantiate compaan
+ca = pi_compaan.PiCompaan(tc, io, nof_inst=1)
+
+# Create block generator/data buffer instance
+bg = pi_diag_block_gen.PiDiagBlockGen(tc, io, c_bg_nof_streams, c_bg_ram_size, tc.nodeFn1Nrs )
+db = pi_diag_data_buffer.PiDiagDataBuffer(tc, io, instanceName = '', nofStreams=c_bg_nof_streams, ramSizePerStream=c_bg_ram_size, nodeNr = tc.nodeFn1Nrs )
+
+# Create dp_offload_tx instance
+dpotx_hdr_dat = pi_dp_offload_tx_hdr_dat_compaan_unb1_10g_terminal.PiDpOffloadTxHdrDatCompaanUnb110GTerminal(tc, io, nof_inst=1, node_nrs=tc.nodeFn0Nrs)
+
+###############################################################################
+# Calculate and print the IP header checksum for FN0
+###############################################################################
+# Fixed header constants
+IP_HEADER_LENGTH = 20
+UDP_HEADER_LENGTH = 8
+USR_HEADER_LENGTH = 20
+USR_HDR_WORD_ALIGN = 2
+NOF_PAYLOAD_BYTES = c_blocksize * 8
+
+ip_version = 4
+ip_header_length = 5 # 5 32b words
+ip_services = 0
+ip_total_length = IP_HEADER_LENGTH+UDP_HEADER_LENGTH+USR_HEADER_LENGTH+USR_HDR_WORD_ALIGN+NOF_PAYLOAD_BYTES - 7 # 6196B
+ip_identification = 0
+ip_flags = 2
+ip_fragment_offset = 0
+ip_time_to_live = 127
+ip_protocol = 17
+ip_header_checksum = 0 # to be calculated
+hdr_bits_common = CommonBits(ip_version ,4) & \
+ CommonBits(ip_header_length ,4) & \
+ CommonBits(ip_services ,8) & \
+ CommonBits(ip_total_length ,16) & \
+ CommonBits(ip_identification ,16) & \
+ CommonBits(ip_flags ,3) & \
+ CommonBits(ip_fragment_offset ,13) & \
+ CommonBits(ip_time_to_live ,8) & \
+ CommonBits(ip_protocol ,8) & \
+ CommonBits(ip_header_checksum ,16)
+
+hdr_bits_fn0 = hdr_bits_common & \
+ CommonBits(ip_src_addr_fn0 ,32) & \
+ CommonBits(ip_dst_addr ,32)
+
+hdr_bits_fn1 = hdr_bits_common & \
+ CommonBits(ip_src_addr_fn1 ,32) & \
+ CommonBits(ip_dst_addr ,32)
+
+hdr_bits_fn2 = hdr_bits_common & \
+ CommonBits(ip_src_addr_fn2 ,32) & \
+ CommonBits(ip_dst_addr ,32)
+
+hdr_bits_fn3 = hdr_bits_common & \
+ CommonBits(ip_src_addr_fn3 ,32) & \
+ CommonBits(ip_dst_addr ,32)
+
+hdr_bytes_fn0 = CommonBytes(hdr_bits_fn0.data, IP_HEADER_LENGTH)
+hdr_bytes_fn1 = CommonBytes(hdr_bits_fn1.data, IP_HEADER_LENGTH)
+hdr_bytes_fn2 = CommonBytes(hdr_bits_fn2.data, IP_HEADER_LENGTH)
+hdr_bytes_fn3 = CommonBytes(hdr_bits_fn3.data, IP_HEADER_LENGTH)
+
+tc.append_log(3, 'IP header checksum FN0: %d' % ip_hdr_checksum(hdr_bytes_fn0))
+tc.append_log(3, 'IP header checksum FN1: %d' % ip_hdr_checksum(hdr_bytes_fn1))
+tc.append_log(3, 'IP header checksum FN2: %d' % ip_hdr_checksum(hdr_bytes_fn2))
+tc.append_log(3, 'IP header checksum FN3: %d' % ip_hdr_checksum(hdr_bytes_fn3))
+
+################################################################################
+## Write settings
+################################################################################
+tc.append_log(3, 'Setting DPOTX for node FN0')
+
+dpotx_hdr_dat.write(node_nrs=tc.nodeFn0Nrs, inst_nrs=tc.gpNumbers, registers=[('eth_src_mac', eth_src_mac + 0)], regmap=dpotx_hdr_dat.regmap)
+dpotx_hdr_dat.write(node_nrs=tc.nodeFn0Nrs, inst_nrs=tc.gpNumbers, registers=[('eth_dst_mac', eth_dst_mac)], regmap=dpotx_hdr_dat.regmap)
+dpotx_hdr_dat.write(node_nrs=tc.nodeFn0Nrs, inst_nrs=tc.gpNumbers, registers=[('ip_src_addr', ip_src_addr_fn0)], regmap=dpotx_hdr_dat.regmap)
+dpotx_hdr_dat.write(node_nrs=tc.nodeFn0Nrs, inst_nrs=tc.gpNumbers, registers=[('ip_dst_addr', ip_dst_addr)], regmap=dpotx_hdr_dat.regmap)
+dpotx_hdr_dat.write(node_nrs=tc.nodeFn0Nrs, inst_nrs=tc.gpNumbers, registers=[('ip_header_checksum', ip_hdr_checksum(hdr_bytes_fn0))], regmap=dpotx_hdr_dat.regmap)
+
+dpotx_hdr_dat.read(node_nrs=tc.nodeFn0Nrs, inst_nrs=tc.gpNumbers, regmap=dpotx_hdr_dat.regmap)
+
+tc.append_log(3, 'Setting BG for node BN0')
+bg.write_block_gen_settings(samplesPerPacket=c_blocksize, blocksPerSync=c_nof_blocks_per_sync, gapSize=c_bg_gap_size, memLowAddr=0, memHighAddr=c_bg_ram_size-1, BSNInit=10)
+
+
+################################################################################
+## Write data to the block generator
+################################################################################
+bg_data=[]
+tc.append_log(3, 'Writing data to BG RAM')
+for i in range(c_bg_ram_size):
+ bg_data.append(i)
+
+if c_write_block_gen:
+ for i in range(c_bg_nof_streams):
+ bg.write_waveform_ram(data=bg_data, channelNr=i)
+
+bg.write_enable()
+
+################################################################################
+## Read data from the databuffer
+################################################################################
+db_out = []
+do_until_ge(db.read_nof_words, ms_retry=1000, val=c_blocksize, s_timeout=3600)
+bg.write_disable()
+for i in range(1):
+ db_out.append(flatten(db.read_data_buffer(streamNr=i, n=c_blocksize*3, radix='uns', width=c_10g_data_w, nofColumns=1)))
+
+print db_out
\ No newline at end of file
diff --git a/applications/compaan/designs/compaan_io_test_fn/tb/vhdl/tb_io_test_fn.vhd b/applications/compaan/designs/compaan_io_test_fn/tb/vhdl/tb_io_test_fn.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7a065d65cbf66a10d88c7360c9859fbacf178056
--- /dev/null
+++ b/applications/compaan/designs/compaan_io_test_fn/tb/vhdl/tb_io_test_fn.vhd
@@ -0,0 +1,278 @@
+
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb1_board_lib, i2c_lib, compaan_io_test_bn_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_io_test_fn IS
+END tb_io_test_fn;
+
+ARCHITECTURE tb OF tb_io_test_fn IS
+
+ -----------------------------------------------------------------------------
+ -- CONSTANTS
+ -----------------------------------------------------------------------------
+ -- System
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_unb1_board_nr : NATURAL := 0;
+ CONSTANT c_node_nr_dut_fn : NATURAL := 0;
+ CONSTANT c_node_nr_dut_bn : NATURAL := 4;
+ CONSTANT c_node_nr_10G_lcu : NATURAL := 1;
+ CONSTANT c_id_dut_fn : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb1_board_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr_dut_fn, c_unb1_board_nof_chip_w);
+ CONSTANT c_id_dut_bn : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb1_board_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr_dut_bn, c_unb1_board_nof_chip_w);
+ CONSTANT c_id_10g_lcu : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb1_board_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr_10g_lcu, c_unb1_board_nof_chip_w);
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+
+ -- Clock periods
+ CONSTANT c_eth_clk_period : TIME := 40 ns;
+ CONSTANT c_sa_clk_period : TIME := 6.4 ns;
+ CONSTANT c_clk_period : TIME := 5 ns;
+ CONSTANT c_cable_delay : TIME := 12 ns;
+ CONSTANT c_pps_period : NATURAL := 1000;
+
+ -- UNB1 Sensors
+ CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW
+ CONSTANT c_eth_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0101001"; -- MAX1618 address MID LOW
+ CONSTANT c_hot_swap_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1000100"; -- LTC4260 address L L L
+ CONSTANT c_fpga_temp : INTEGER := 60;
+ CONSTANT c_eth_temp : INTEGER := 40;
+ CONSTANT c_hot_swap_R_sense : REAL := 0.01;
+
+ CONSTANT c_uniboard_current : REAL := 5.0; -- = assume 5.0 A on UniBoard
+ CONSTANT c_uniboard_supply : REAL := 48.0; -- = assume 48.0 V on UniBoard
+ CONSTANT c_uniboard_adin : REAL := -1.0; -- = NC on UniBoard
+
+ ------------------------------------------------------------------------------
+ -- SIGNALS
+ ------------------------------------------------------------------------------
+ -- System
+ SIGNAL VERSION : STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0) := c_version;
+ SIGNAL ID_DUT_FN : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_id_dut_fn;
+ SIGNAL ID_DUT_BN : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_id_dut_bn;
+ SIGNAL ID_10G_LCU : STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0) := c_id_10g_lcu;
+ SIGNAL TESTIO : STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
+
+ -- Clocks
+ SIGNAL clk : STD_LOGIC := '0';
+ SIGNAL sa_clk : STD_LOGIC := '1';
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '0';
+ SIGNAL eth_rxp : STD_LOGIC;
+ SIGNAL eth_txp : STD_LOGIC;
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ -- Serial I/O: Terminal
+ SIGNAL FN_BN_0_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ SIGNAL FN_BN_0_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ SIGNAL FN_BN_1_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ SIGNAL FN_BN_1_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ SIGNAL FN_BN_2_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ SIGNAL FN_BN_2_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ SIGNAL FN_BN_3_TX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ SIGNAL FN_BN_3_RX : STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+
+ -- Serial I/O: 10GbE Interface
+ SIGNAL SI_FN_0_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL SI_FN_0_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL SI_FN_1_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL SI_FN_1_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL SI_FN_2_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL SI_FN_2_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL SI_FN_3_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL SI_FN_3_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+
+BEGIN
+ ----------------------------------------------------------------------------
+ -- Externally generated clocks
+ ----------------------------------------------------------------------------
+ clk <= NOT clk AFTER c_clk_period/2;
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;
+ sa_clk <= NOT sa_clk AFTER c_sa_clk_period/2;
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, clk, pps);
+
+ ------------------------------------------------------------------------------
+ -- 1GbE Loopback model
+ ------------------------------------------------------------------------------
+ eth_rxp <= TRANSPORT eth_txp AFTER c_cable_delay;
+
+ ------------------------------------------------------------------------------
+ -- DUT Fn
+ ------------------------------------------------------------------------------
+ u_dut_fn: ENTITY work.compaan_io_test_fn
+ GENERIC MAP(
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb1_board_nr,
+ g_sim_node_nr => c_node_nr_dut_fn
+ )
+ PORT MAP(
+ CLK => clk,
+ PPS => pps,
+ VERSION => VERSION,
+ ID => ID_DUT_FN,
+
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ SA_CLK => sa_clk,
+ SB_CLK => sa_clk,
+
+ FN_BN_0_TX => FN_BN_0_TX,
+ FN_BN_0_RX => FN_BN_0_RX,
+ FN_BN_1_TX => FN_BN_1_TX,
+ FN_BN_1_RX => FN_BN_1_RX,
+ FN_BN_2_TX => FN_BN_2_TX,
+ FN_BN_2_RX => FN_BN_2_RX,
+ FN_BN_3_TX => FN_BN_3_TX,
+ FN_BN_3_RX => FN_BN_3_RX,
+
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+ SI_FN_3_TX => SI_FN_3_TX,
+ SI_FN_3_RX => SI_FN_3_RX
+ );
+
+ -----------------------------------------------------------------------------
+ -- DUT Bn
+ -----------------------------------------------------------------------------
+ u_dut_bn: ENTITY compaan_io_test_bn_lib.compaan_io_test_bn
+ GENERIC MAP(
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb1_board_nr,
+ g_sim_node_nr => c_node_nr_dut_bn
+ )
+ PORT MAP(
+ CLK => clk,
+ PPS => pps,
+ VERSION => VERSION,
+ ID => ID_DUT_BN,
+
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ SB_CLK => sa_clk,
+
+ FN_BN_0_TX => FN_BN_0_RX,
+ FN_BN_0_RX => FN_BN_0_TX,
+ FN_BN_1_TX => FN_BN_1_RX,
+ FN_BN_1_RX => FN_BN_1_TX,
+ FN_BN_2_TX => FN_BN_2_RX,
+ FN_BN_2_RX => FN_BN_2_TX,
+ FN_BN_3_TX => FN_BN_3_RX,
+ FN_BN_3_RX => FN_BN_3_TX
+ );
+
+ -----------------------------------------------------------------------------
+ -- 10G LCU
+ -----------------------------------------------------------------------------
+ u_10g_lcu: ENTITY work.compaan_unb1_10g_bg_db
+ GENERIC MAP(
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb1_board_nr,
+ g_sim_node_nr => c_node_nr_10g_lcu
+ )
+ PORT MAP(
+ CLK => clk,
+ PPS => pps,
+ VERSION => VERSION,
+ ID => ID_10G_LCU,
+
+ ETH_clk => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ SA_CLK => sa_clk,
+
+ SI_FN_0_TX => SI_FN_0_RX,
+ SI_FN_0_RX => SI_FN_0_TX,
+ SI_FN_1_TX => SI_FN_1_RX,
+ SI_FN_1_RX => SI_FN_1_TX,
+ SI_FN_2_TX => SI_FN_2_RX,
+ SI_FN_2_RX => SI_FN_2_TX,
+ SI_FN_3_TX => SI_FN_3_RX,
+ SI_FN_3_RX => SI_FN_3_TX
+ );
+
+ ------------------------------------------------------------------------------
+ -- UniBoard sensors
+ ------------------------------------------------------------------------------
+ -- I2C slaves that are available for each FPGA
+ u_fpga_temp : ENTITY i2c_lib.dev_max1618
+ GENERIC MAP (
+ g_address => c_fpga_temp_address
+ )
+ PORT MAP (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_fpga_temp
+ );
+
+ -- I2C slaves that are available only via FPGA back node 3
+ u_eth_temp : ENTITY i2c_lib.dev_max1618
+ GENERIC MAP (
+ g_address => c_eth_temp_address
+ )
+ PORT MAP (
+ scl => sens_scl,
+ sda => sens_sda,
+ temp => c_eth_temp
+ );
+
+ u_power : ENTITY i2c_lib.dev_ltc4260
+ GENERIC MAP (
+ g_address => c_hot_swap_address,
+ g_R_sense => c_hot_swap_R_sense
+ )
+ PORT MAP (
+ scl => sens_scl,
+ sda => sens_sda,
+ ana_current_sense => c_uniboard_current,
+ ana_volt_source => c_uniboard_supply,
+ ana_volt_adin => c_uniboard_adin
+ );
+
+END tb;