Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
H
HDL
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Iterations
Wiki
Requirements
Jira
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Build
Pipelines
Jobs
Pipeline schedules
Test cases
Artifacts
Deploy
Releases
Container Registry
Model registry
Operate
Environments
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
RTSD
HDL
Commits
58c7882f
Commit
58c7882f
authored
8 years ago
by
Daniel van der Schuur
Browse files
Options
Downloads
Patches
Plain Diff
-Updated beamlet selection: now forwarding beamlets 0..23 instead of
0,1,256,257,512,513,768,769.
parent
7ef939a8
No related branches found
No related tags found
No related merge requests found
Changes
1
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
applications/arts/designs/arts_unb1_sc1_3dish_1pol/src/vhdl/arts_unb1_sc1_3dish_1pol.vhd
+14
-33
14 additions, 33 deletions
...unb1_sc1_3dish_1pol/src/vhdl/arts_unb1_sc1_3dish_1pol.vhd
with
14 additions
and
33 deletions
applications/arts/designs/arts_unb1_sc1_3dish_1pol/src/vhdl/arts_unb1_sc1_3dish_1pol.vhd
+
14
−
33
View file @
58c7882f
...
@@ -152,7 +152,7 @@ ARCHITECTURE str OF arts_unb1_sc1_3dish_1pol IS
...
@@ -152,7 +152,7 @@ ARCHITECTURE str OF arts_unb1_sc1_3dish_1pol IS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- DP split, Repack
-- DP split, Repack
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
CONSTANT
c_nof_sc1_symbols
:
NATURAL
:
=
6
;
-- 24 16b-subbands = 6 64b-words
CONSTANT
c_nof_sc1_symbols
:
NATURAL
:
=
24
;
SIGNAL
dp_split_src_in_2arr_2
:
t_dp_siso_2arr_2
(
c_nof_10GbE_streams
-1
DOWNTO
0
);
SIGNAL
dp_split_src_in_2arr_2
:
t_dp_siso_2arr_2
(
c_nof_10GbE_streams
-1
DOWNTO
0
);
SIGNAL
dp_split_src_out_2arr_2
:
t_dp_sosi_2arr_2
(
c_nof_10GbE_streams
-1
DOWNTO
0
);
SIGNAL
dp_split_src_out_2arr_2
:
t_dp_sosi_2arr_2
(
c_nof_10GbE_streams
-1
DOWNTO
0
);
...
@@ -449,7 +449,9 @@ BEGIN
...
@@ -449,7 +449,9 @@ BEGIN
);
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Forward only the first 6 64b words (=24 16b beamlets)
-- Forward only the first 24 64b words
-- . This will forward 4 sets (bf_units) of 24 beamlets. We'll discard
-- substreams 1..3 later and only use substream 0 (beamlets 0..23).
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
gen_dp_split
:
FOR
i
IN
0
TO
c_nof_10GbE_streams
-1
GENERATE
gen_dp_split
:
FOR
i
IN
0
TO
c_nof_10GbE_streams
-1
GENERATE
u_dp_split
:
ENTITY
dp_lib
.
dp_split
u_dp_split
:
ENTITY
dp_lib
.
dp_split
...
@@ -474,45 +476,24 @@ BEGIN
...
@@ -474,45 +476,24 @@ BEGIN
dp_split_src_out_arr
(
i
)
<=
dp_split_src_out_2arr_2
(
i
)(
1
);
dp_split_src_out_arr
(
i
)
<=
dp_split_src_out_2arr_2
(
i
)(
1
);
END
GENERATE
;
END
GENERATE
;
-------------------------------------------------------------------------------
-- Repack 6 64b words into 24 16b words (beamlets)
-------------------------------------------------------------------------------
gen_dp_repack_data
:
FOR
i
IN
0
TO
c_nof_10GbE_streams
-1
GENERATE
u_dp_repack_data
:
ENTITY
dp_lib
.
dp_repack_data
GENERIC
MAP
(
g_in_dat_w
=>
c_xgmii_data_w
,
g_in_nof_words
=>
1
,
g_in_symbol_w
=>
c_channel_dat_w
,
g_out_dat_w
=>
c_channel_dat_w
,
g_out_nof_words
=>
4
,
g_out_symbol_w
=>
c_channel_dat_w
)
PORT
MAP
(
rst
=>
dp_rst
,
clk
=>
dp_clk
,
snk_out
=>
dp_split_src_in_arr
(
i
),
snk_in
=>
dp_split_src_out_arr
(
i
),
src_in
=>
dp_repack_data_src_in_arr
(
i
),
src_out
=>
dp_repack_data_src_out_arr
(
i
)
);
END
GENERATE
;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- bf_unit
-- bf_unit
-- . We're using the unquantized raw output data(15..0). The default weights
-- . We're using the unquantized raw output data(15..0). The default weights
-- are complex(1) so overflow will not occur during multiplication.
-- are complex(1) so overflow will not occur during multiplication.
-- However, overflow might occur (in theory) during the adder stage. We're
-- However, overflow might occur (in theory) during the adder stage. We're
-- currently accepting this risk as it is low
--FIXME beware!
-- currently accepting this risk as it is low
.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Wire complex inputs
-- Wire complex inputs
p_complex
:
PROCESS
(
dp_
repack_data
_src_out_arr
)
IS
p_complex
:
PROCESS
(
dp_
split
_src_out_arr
)
IS
BEGIN
BEGIN
bf_unit_snk_in_arr
<=
dp_
repack_data
_src_out_arr
;
bf_unit_snk_in_arr
<=
dp_
split
_src_out_arr
;
FOR
i
IN
0
TO
c_nof_10GbE_streams
-1
LOOP
FOR
i
IN
0
TO
c_nof_10GbE_streams
-1
LOOP
bf_unit_snk_in_arr
(
i
)
.
im
(
c_channel_compl_dat_w
-1
DOWNTO
0
)
<=
dp_repack_data_src_out_arr
(
i
)
.
data
(
c_channel_dat_w
-1
DOWNTO
c_channel_compl_dat_w
);
bf_unit_snk_in_arr
(
i
)
.
data
<=
(
OTHERS
=>
'0'
);
bf_unit_snk_in_arr
(
i
)
.
re
(
c_channel_compl_dat_w
-1
DOWNTO
0
)
<=
dp_repack_data_src_out_arr
(
i
)
.
data
(
c_channel_compl_dat_w
-1
DOWNTO
0
);
bf_unit_snk_in_arr
(
i
)
.
im
<=
(
OTHERS
=>
'0'
);
bf_unit_snk_in_arr
(
i
)
.
re
<=
(
OTHERS
=>
'0'
);
-- Forward only bf_unit substream 0
bf_unit_snk_in_arr
(
i
)
.
im
(
c_channel_compl_dat_w
-1
DOWNTO
0
)
<=
dp_split_src_out_arr
(
i
)
.
data
(
c_channel_dat_w
-1
DOWNTO
c_channel_compl_dat_w
);
bf_unit_snk_in_arr
(
i
)
.
re
(
c_channel_compl_dat_w
-1
DOWNTO
0
)
<=
dp_split_src_out_arr
(
i
)
.
data
(
c_channel_compl_dat_w
-1
DOWNTO
0
);
END
LOOP
;
END
LOOP
;
END
PROCESS
;
END
PROCESS
;
...
@@ -538,7 +519,7 @@ BEGIN
...
@@ -538,7 +519,7 @@ BEGIN
reg_st_sst_miso
=>
reg_bf_unit_st_sst_miso
,
reg_st_sst_miso
=>
reg_bf_unit_st_sst_miso
,
in_sosi_arr
=>
bf_unit_snk_in_arr
,
in_sosi_arr
=>
bf_unit_snk_in_arr
,
in_siso_arr
=>
dp_
repack_data
_src_in_arr
,
in_siso_arr
=>
dp_
split
_src_in_arr
,
out_raw_sosi
=>
bf_unit_raw_src_out
,
out_raw_sosi
=>
bf_unit_raw_src_out
,
out_bst_sosi
=>
bf_unit_bst_src_out
,
out_bst_sosi
=>
bf_unit_bst_src_out
,
out_qua_sosi
=>
bf_unit_qua_src_out
out_qua_sosi
=>
bf_unit_qua_src_out
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment