Clarified description about that the DSP component has to pass on sop and eop.

libraries/base/dp/src/vhdl/dp_fifo_info.vhd

@@ -32,6 +32,13 @@
 --   the data. To save logic and RAM and to not burden the data function with
 --   the handling of the info this dp_fifo_info can realign the original
 --   snk_in info with the delayed snk_in data.
+--   The dp_fifo_info uses the info_snk_in.sop and info_snk_in.eop to write
+--   the info_snk_in info to the FIFO and it uses the data_snk_in.sop and
+--   data_snk_in.eop to read the info from the FIFO. Therefore the DSP
+--   component must pass on the snk_in.sop and snk_in.eop, to be able to
+--   attach the info_snk_in sop info and eop info again at the output. The
+--   g_fifo_size must be sufficient to fit the maximum latency in number of
+--   blocks (sop's) that the DSP component can introduce.
 --
 -- Usage:
 --                           data_snk_out
@@ -39,8 +46,8 @@
 --                               .
 --                   |-----|     .         |------|
 --   snk_out <------ |     | <------------ |      | <---- src_in
---   snk_in  ---*--> | DP  | ------------> | dp   | ----> src_out
---              |    |     |               | fifo |
+--   snk_in  ---*--> | DP/ | ------------> | dp   | ----> src_out
+--              |    | DSP |               | fifo |
 --              |    |-----|               | info |
 --              |            info_snk_in   |      |
 --              \------------------------> |------|
@@ -51,6 +58,11 @@
 -- . The data is passed on unchanged by dp_fifo_info.
 -- . The dp_fifo_info preserves the RL=1 but is does delay the data by one
 --   cycle.
+-- . If the DSP component does not pass on the sop and eop, then it can be
+--   possible to recreate these at the output based on the valid using e.g.
+--   dp_block_gen. This assumes that the DSP does pass on the valid, that the
+--   block size is known and that the first valid at the output corresponds
+--   to a sop.
 
 LIBRARY IEEE, common_lib, technology_lib;
 USE IEEE.STD_LOGIC_1164.ALL;