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Commit 57d7a495 authored by Reinier van der Walle's avatar Reinier van der Walle
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Merge branch 'L2SDP-80' into 'master' 

Resolve L2SDP-80

Closes L2SDP-80

See merge request desp/hdl!27
parents c147c5bb 66e0f2b6
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2 merge requests!28Master,!27Resolve L2SDP-80
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boards/uniboard2c/designs/altera_ref_designs/ddr4/ed_synth_19_2_0_57_DDR4.qar 0 → 100644
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− 0
View file @ 57d7a495
File added
libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qsys
+ 25
− 65
View file @ 57d7a495
......@@ -36,19 +36,6 @@
<parameter name="systemHash" value="0" />
<parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
<connPtSystemInfos>
<entry>
<key>cal_debug_out_clk</key>
<value>
<connectionPointName>cal_debug_out_clk</connectionPointName>
<suppliedSystemInfos/>
<consumedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
<value>0</value>
</entry>
</consumedSystemInfos>
</value>
</entry>
<entry>
<key>ctrl_amm_0</key>
<value>
......@@ -99,7 +86,7 @@
<consumedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
<value>175000000</value>
<value>200000000</value>
</entry>
</consumedSystemInfos>
</value>
......@@ -111,36 +98,9 @@
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="cal_debug_out"
internal="emif_0.cal_debug_out"
type="avalon"
dir="start">
<port name="cal_debug_out_addr" internal="cal_debug_out_addr" />
<port name="cal_debug_out_byteenable" internal="cal_debug_out_byteenable" />
<port name="cal_debug_out_read" internal="cal_debug_out_read" />
<port name="cal_debug_out_read_data" internal="cal_debug_out_read_data" />
<port
name="cal_debug_out_read_data_valid"
internal="cal_debug_out_read_data_valid" />
<port name="cal_debug_out_waitrequest" internal="cal_debug_out_waitrequest" />
<port name="cal_debug_out_write" internal="cal_debug_out_write" />
<port name="cal_debug_out_write_data" internal="cal_debug_out_write_data" />
</interface>
<interface
name="cal_debug_out_clk"
internal="emif_0.cal_debug_out_clk"
type="clock"
dir="start">
<port name="cal_debug_out_clk" internal="cal_debug_out_clk" />
</interface>
<interface
name="cal_debug_out_reset_n"
internal="emif_0.cal_debug_out_reset_n"
type="reset"
dir="start">
<port name="cal_debug_out_reset_n" internal="cal_debug_out_reset_n" />
</interface>
<interface name="cal_debug_out" internal="emif_0.cal_debug_out" />
<interface name="cal_debug_out_clk" internal="emif_0.cal_debug_out_clk" />
<interface name="cal_debug_out_reset_n" internal="emif_0.cal_debug_out_reset_n" />
<interface
name="ctrl_amm_0"
internal="emif_0.ctrl_amm_0"
......@@ -257,18 +217,18 @@
<parameter name="BOARD_DDR3_USER_WDATA_SLEW_RATE" value="2.0" />
<parameter name="BOARD_DDR3_USE_DEFAULT_ISI_VALUES" value="true" />
<parameter name="BOARD_DDR3_USE_DEFAULT_SLEW_RATES" value="true" />
<parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="-0.003125" />
<parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.103" />
<parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.006008328" />
<parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="0.0425" />
<parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="0.0" />
<parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
<parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
<parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="0.02" />
<parameter name="BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
<parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
<parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.215" />
<parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.323" />
<parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.6" />
<parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.6" />
<parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
<parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.072" />
<parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.0" />
<parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.176" />
<parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
<parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.02" />
<parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.0" />
<parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="2.0" />
<parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="4.0" />
......@@ -488,7 +448,7 @@
<parameter name="DIAG_DDR4_CAL_FULL_CAL_ON_RESET" value="true" />
<parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
<parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_HEAD_OF_CHAIN" value="true" />
<parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
<parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="false" />
<parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_JTAG</parameter>
<parameter name="DIAG_DDR4_EX_DESIGN_ISSP_EN" value="true" />
<parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
......@@ -826,7 +786,7 @@
<parameter name="MEM_DDR4_READ_PREAMBLE" value="2" />
<parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
<parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
<parameter name="MEM_DDR4_RTT_NOM_ENUM" value="DDR4_RTT_NOM_RZQ_5" />
<parameter name="MEM_DDR4_RTT_NOM_ENUM" value="DDR4_RTT_NOM_RZQ_4" />
<parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
<parameter name="MEM_DDR4_RTT_WR_ENUM">DDR4_RTT_WR_ODT_DISABLED</parameter>
<parameter name="MEM_DDR4_R_ODT0_1X1" value="on" />
......@@ -859,12 +819,12 @@
<parameter name="MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM" value="20" />
<parameter name="MEM_DDR4_SPD_152_DRAM_RTT_PARK" value="39" />
<parameter name="MEM_DDR4_SPEEDBIN_ENUM" value="DDR4_SPEEDBIN_2133" />
<parameter name="MEM_DDR4_TCCD_L_CYC" value="4" />
<parameter name="MEM_DDR4_TCCD_L_CYC" value="6" />
<parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
<parameter name="MEM_DDR4_TCL" value="12" />
<parameter name="MEM_DDR4_TCL" value="11" />
<parameter name="MEM_DDR4_TDIVW_DJ_CYC" value="0.1" />
<parameter name="MEM_DDR4_TDIVW_TOTAL_UI" value="0.2" />
<parameter name="MEM_DDR4_TDQSCK_PS" value="170" />
<parameter name="MEM_DDR4_TDQSCK_PS" value="180" />
<parameter name="MEM_DDR4_TDQSQ_PS" value="66" />
<parameter name="MEM_DDR4_TDQSQ_UI" value="0.16" />
<parameter name="MEM_DDR4_TDQSS_CYC" value="0.27" />
......@@ -875,7 +835,7 @@
<parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
<parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
<parameter name="MEM_DDR4_TFAW_DLR_CYC" value="16" />
<parameter name="MEM_DDR4_TFAW_NS" value="28.57" />
<parameter name="MEM_DDR4_TFAW_NS" value="25.0" />
<parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
<parameter name="MEM_DDR4_TIH_PS" value="105" />
<parameter name="MEM_DDR4_TINIT_US" value="500" />
......@@ -884,7 +844,7 @@
<parameter name="MEM_DDR4_TMRD_CK_CYC" value="8" />
<parameter name="MEM_DDR4_TQH_CYC" value="0.38" />
<parameter name="MEM_DDR4_TQH_UI" value="0.76" />
<parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
<parameter name="MEM_DDR4_TQSH_CYC" value="0.4" />
<parameter name="MEM_DDR4_TRAS_NS" value="33.0" />
<parameter name="MEM_DDR4_TRCD_NS" value="14.06" />
<parameter name="MEM_DDR4_TREFI_US" value="7.8" />
......@@ -892,18 +852,18 @@
<parameter name="MEM_DDR4_TRFC_NS" value="260.0" />
<parameter name="MEM_DDR4_TRP_NS" value="14.06" />
<parameter name="MEM_DDR4_TRRD_DLR_CYC" value="4" />
<parameter name="MEM_DDR4_TRRD_L_CYC" value="4" />
<parameter name="MEM_DDR4_TRRD_L_CYC" value="6" />
<parameter name="MEM_DDR4_TRRD_S_CYC" value="4" />
<parameter name="MEM_DDR4_TWLH_CYC" value="0.13" />
<parameter name="MEM_DDR4_TWLH_PS" value="0.0" />
<parameter name="MEM_DDR4_TWLS_CYC" value="0.13" />
<parameter name="MEM_DDR4_TWLS_PS" value="0.0" />
<parameter name="MEM_DDR4_TWR_NS" value="15.0" />
<parameter name="MEM_DDR4_TWTR_L_CYC" value="6" />
<parameter name="MEM_DDR4_TWTR_S_CYC" value="2" />
<parameter name="MEM_DDR4_TWTR_L_CYC" value="8" />
<parameter name="MEM_DDR4_TWTR_S_CYC" value="3" />
<parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_0</parameter>
<parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_VALUE" value="68.0" />
<parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="false" />
<parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="true" />
<parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
<parameter name="MEM_DDR4_WRITE_CRC" value="false" />
<parameter name="MEM_DDR4_WRITE_DBI" value="false" />
......@@ -1108,7 +1068,7 @@
<parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="false" />
<parameter name="PHY_DDR4_HPS_ENABLE_EARLY_RELEASE" value="false" />
<parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
<parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="700.0" />
<parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="800.0" />
<parameter name="PHY_DDR4_RATE_ENUM" value="RATE_QUARTER" />
<parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
<parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="IO_STD_SSTL_12" />
......@@ -1118,7 +1078,7 @@
<parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="IO_STD_SSTL_12" />
<parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="OUT_OCT_40_CAL" />
<parameter name="PHY_DDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
<parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="IN_OCT_48_CAL" />
<parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="IN_OCT_120_CAL" />
<parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="IO_STD_POD_12" />
<parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="OUT_OCT_34_CAL" />
<parameter name="PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
......
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