Added Intel reference design for unb2c as .qar and corrected IP

...ds/uniboard2c/designs/altera_ref_designs/ddr4/ed_sim.qsys

.../uniboard2c/designs/altera_ref_designs/ddr4/ed_synth.qsys

...signs/altera_ref_designs/ddr4/ed_synth_19_2_0_57_DDR4.qar

...esigns/altera_ref_designs/ddr4/ip/ed_sim/ed_sim_emif_0.ip

...ef_designs/ddr4/ip/ed_sim/ed_sim_global_reset_n_source.ip

..._designs/ddr4/ip/ed_sim/ed_sim_global_reset_n_splitter.ip

...c/designs/altera_ref_designs/ddr4/ip/ed_sim/ed_sim_mem.ip

...a_ref_designs/ddr4/ip/ed_sim/ed_sim_pll_ref_clk_source.ip

...s/altera_ref_designs/ddr4/ip/ed_sim/ed_sim_sim_checker.ip

...2c/designs/altera_ref_designs/ddr4/ip/ed_sim/ed_sim_tg.ip

...ns/altera_ref_designs/ddr4/ip/ed_synth/ed_synth_emif_0.ip

...igns/ddr4/ip/ed_synth/ed_synth_global_reset_n_splitter.ip

...esigns/altera_ref_designs/ddr4/ip/ed_synth/ed_synth_tg.ip

...ard2c/designs/altera_ref_designs/ddr4/make_qii_design.tcl

...ard2c/designs/altera_ref_designs/ddr4/make_sim_design.tcl

boards/uniboard2c/designs/altera_ref_designs/ddr4/params.tcl

.../designs/altera_ref_designs/ddr4/qii/ed_synth.archive.rpt

...rd2c/designs/altera_ref_designs/ddr4/qii/ed_synth.asm.rpt

...board2c/designs/altera_ref_designs/ddr4/qii/ed_synth.done

...gns/altera_ref_designs/ddr4/qii/ed_synth.fit.finalize.rpt