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RTSD
HDL
Commits
5787dd18
Commit
5787dd18
authored
8 years ago
by
Eric Kooistra
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Use tb_end signal.
parent
fe53bcae
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libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
+5
-1
5 additions, 1 deletion
libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
with
5 additions
and
1 deletion
libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
+
5
−
1
View file @
5787dd18
...
@@ -46,6 +46,7 @@ ARCHITECTURE tb OF tb_tb_io_ddr IS
...
@@ -46,6 +46,7 @@ ARCHITECTURE tb OF tb_tb_io_ddr IS
CONSTANT
c_tb_end_vec
:
STD_LOGIC_VECTOR
(
15
DOWNTO
0
)
:
=
(
OTHERS
=>
'1'
);
CONSTANT
c_tb_end_vec
:
STD_LOGIC_VECTOR
(
15
DOWNTO
0
)
:
=
(
OTHERS
=>
'1'
);
SIGNAL
tb_end_vec
:
STD_LOGIC_VECTOR
(
15
DOWNTO
0
)
:
=
c_tb_end_vec
;
-- sufficiently long to fit all tb instances
SIGNAL
tb_end_vec
:
STD_LOGIC_VECTOR
(
15
DOWNTO
0
)
:
=
c_tb_end_vec
;
-- sufficiently long to fit all tb instances
SIGNAL
tb_end
:
STD_LOGIC
:
=
'0'
;
BEGIN
BEGIN
...
@@ -93,9 +94,12 @@ BEGIN
...
@@ -93,9 +94,12 @@ BEGIN
u_default
:
ENTITY
work
.
tb_io_ddr
GENERIC
MAP
(
FALSE
,
c_technology
,
c_tech_ddr3
,
c_tech_ddr4
,
FALSE
,
FALSE
,
5
ns
,
4
,
2500
,
2
,
1
,
1
,
1
,
"VAL"
)
PORT
MAP
(
tb_end_vec
(
0
));
u_default
:
ENTITY
work
.
tb_io_ddr
GENERIC
MAP
(
FALSE
,
c_technology
,
c_tech_ddr3
,
c_tech_ddr4
,
FALSE
,
FALSE
,
5
ns
,
4
,
2500
,
2
,
1
,
1
,
1
,
"VAL"
)
PORT
MAP
(
tb_end_vec
(
0
));
END
GENERATE
;
END
GENERATE
;
tb_end
<=
'1'
WHEN
tb_end_vec
=
c_tb_end_vec
ELSE
'0'
;
p_tb_end
:
PROCESS
p_tb_end
:
PROCESS
BEGIN
BEGIN
WAIT
UNTIL
tb_end_vec
=
c_tb_end_vec
;
WAIT
UNTIL
tb_end
=
'1'
;
WAIT
FOR
1
ns
;
REPORT
"Multi tb simulation finished."
SEVERITY
FAILURE
;
REPORT
"Multi tb simulation finished."
SEVERITY
FAILURE
;
WAIT
;
WAIT
;
END
PROCESS
;
END
PROCESS
;
...
...
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