From 5787dd1862d678acf6609bb49c23c3ef5499cbee Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Wed, 11 May 2016 14:08:52 +0000
Subject: [PATCH] Use tb_end signal.
---
libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
index b21fa8258c..47019f4c98 100644
--- a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
@@ -46,6 +46,7 @@ ARCHITECTURE tb OF tb_tb_io_ddr IS
CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS=>'1');
SIGNAL tb_end_vec : STD_LOGIC_VECTOR(15 DOWNTO 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
+ SIGNAL tb_end : STD_LOGIC := '0';
BEGIN
@@ -93,9 +94,12 @@ BEGIN
u_default : ENTITY work.tb_io_ddr GENERIC MAP (FALSE, c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, 5 ns, 4, 2500, 2, 1, 1, 1, "VAL") PORT MAP (tb_end_vec(0));
END GENERATE;
+ tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0';
+
p_tb_end : PROCESS
BEGIN
- WAIT UNTIL tb_end_vec=c_tb_end_vec;
+ WAIT UNTIL tb_end='1';
+ WAIT FOR 1 ns;
REPORT "Multi tb simulation finished." SEVERITY FAILURE;
WAIT;
END PROCESS;
--
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