Renamed MM bus code from common to mm HDL library. Improved usage description of mm_bus.vhd

libraries/base/mm/src/vhdl/mm_bus.vhd

@@ -25,12 +25,12 @@
 --          interfaces
 -- Description:
 -- * MM bus
---   The common_mem_bus creates a memory mapped (MM) bus that connects read
+--   The mm_bus creates a memory mapped (MM) bus that connects read
 --   and write accesses from the master interface to the addressed slave
 --   interface. There is one master that controls the bus and there are
 --   g_nof_slaves on the bus. Per slave the start address and address span
 --   have to be specified via g_base_arr and g_width_arr.
--- 
+--
 -- * Slave allocation
 --   The slaves have to be located on the bus such that the MSbits of the 
 --   global address can be used to select the slave and the LSbits of the
@@ -90,6 +90,35 @@
 --   c_pipeline_mosi + g_rd_latency_arr of the selected slave + 
 --   c_pipeline_miso_rd. 
 --     
+-- Usage:
+--   The ascii drawing shows how this mm_bus can be used in combination
+--   with other MM bus components to create an memory mapped bus:
+--
+--   . mm_bus        : connects a master to multiple independent slaves
+--   . mm_slave_mux  : connects an array of slave to a single slave port
+--   . mm_master_mux : connects mulitple masters to a single slave
+--   
+--                mm_slave_mux
+--         mm_bus     |---S
+--            |-------|---S
+--            |---S   |---S
+--       M ---|
+--            |---S
+--            |---S
+--            |-------|
+--            |---S   |---S
+--                    |
+--       M -----------|
+--                mm_master_mux
+--
+--    The mm_slave_mux is useful to present an array of equal slave MM
+--    ports via a single port on the MM bus. Otherwise the mm_bus could
+--    instead directly present each slave MM array port.
+--    The mm_slave_mux introduces hierarchy in the MM bus structure. This
+--    can help to influcence the timing closure. Using only mm_bus or 
+--    the a combination of mm_bus and mm_slave_mux can help to steer 
+--    where pipelining is inserted in the MM bus.
+-- 
 -- Limitations:
 -- * A limitation is that if one slave has a read latency of 2 and another
 --   slave has a read latency of 1 then it is not possible to access them
@@ -105,10 +134,10 @@
 --   latency adapter for the mosi dependent on the miso.waitrequest.
 --
 -- Remarks:
--- . The common_mem_bus resembles common_mem_mux, but the difference is that
+-- . The mm_bus resembles common_mem_mux, but the difference is that
 --   with common_mem_mux all slaves have the same address range and are
 --   spaced without address gaps. It is possible to use common_mem_mux in
---   series with common_mem_bus to provide hierarchy by reprensenting an array
+--   series with mm_bus to provide hierarchy by reprensenting an array
 --   of slave ports via a single slave port on the MM bus.
 -- . In simulation selecting an unused element address will cause a simulation
 --   failure. Therefore the element index is only accepted when it is in the
@@ -122,7 +151,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 
-ENTITY common_mem_bus IS
+ENTITY mm_bus IS
   GENERIC (
     g_nof_slaves         : POSITIVE;           -- Number of MM slave interfaces on the bus
     g_base_arr           : t_nat_natural_arr;  -- Address base per slave
@@ -139,9 +168,9 @@ ENTITY common_mem_bus IS
     slave_mosi_arr : OUT t_mem_mosi_arr(0 TO g_nof_slaves-1); 
     slave_miso_arr : IN  t_mem_miso_arr(0 TO g_nof_slaves-1) := (OTHERS=>c_mem_miso_rst)
   );
-END common_mem_bus;
+END mm_bus;
 
-ARCHITECTURE rtl OF common_mem_bus IS
+ARCHITECTURE rtl OF mm_bus IS
   
   -- Determine the address range of all slaves on the MM bus.
   FUNCTION func_derive_mm_bus_addr_w(g_base_arr, g_width_arr : t_nat_natural_arr) RETURN NATURAL IS

libraries/base/mm/src/vhdl/mm_master_mux.vhd

@@ -24,8 +24,8 @@
 -- Purpose: Multiplex an array of MM master interfaces to a single MM master
 --          interface
 -- Description:
---   This common_mem_master_mux is a simple multiplexer that allows multiple
---   masters to access the same MM port. The common_mem_master_mux does not
+--   This mm_master_mux is a simple multiplexer that allows multiple
+--   masters to access the same MM port. The mm_master_mux does not
 --   provide arbitration between the masters in the array. Therefore the
 --   precondition is that the external application takes care that the MM
 --   accesses of the multiple masters in the array do not overlap in time.
@@ -35,16 +35,20 @@
 --   the application introducing a gap, before a read access by another master
 --   can be multiplexed.
 --
---   The common_mem_master_mux operates combinatorially, so it introduces no
+--   The mm_master_mux operates combinatorially, so it introduces no
 --   extra latency. The mm_clk is needed to hold the index of the master that
 --   is currently active, to ensure that the read data.is passed on to the
 --   master that did the rd access.
 --
 -- Remarks:
+-- . This resembles common_mem_demux.vhd, but is not identical. The difference
+--   is that common_mem_demux is the inverse of common_mem_demux and therefore 
+--   assumes that all the mux_mosi spans the entire array whereas for this
+--   mm_master_mux the mux_mosi spans one element.
 -- . There is no bus arbitrator. This is sufficient for use cases where e.g.
 --   one master only does some initialization accesses after reset and the
 --   other master is the main master that does all subsequent accesses.
---   Therefore this common_mem_master_mux is typically suited per MM slave
+--   Therefore this mm_master_mux is typically suited per MM slave
 --   that needs dual master access, rather then to select between two main
 --   central MM masters.
 -- . There is no pipelining. The advantage is that the mux_miso.waitrequest is
@@ -58,7 +62,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 
-ENTITY common_mem_master_mux IS
+ENTITY mm_master_mux IS
   GENERIC (
     g_nof_masters     : POSITIVE;  -- Number of MM masters
     g_rd_latency_min  : NATURAL    -- Minimum read latency
@@ -70,9 +74,9 @@ ENTITY common_mem_master_mux IS
     mux_mosi        : OUT t_mem_mosi; 
     mux_miso        : IN  t_mem_miso
   );
-END common_mem_master_mux;
+END mm_master_mux;
 
-ARCHITECTURE rtl OF common_mem_master_mux IS
+ARCHITECTURE rtl OF mm_master_mux IS
   
   SIGNAL index                : NATURAL := 0;
   SIGNAL index_hold           : NATURAL := 0;
@@ -90,7 +94,7 @@ BEGIN
     -- The pre condition is that the input masters will only start an access
     -- when the mux master is free. For a rd access this means that the
     -- read latency of the rdval has passed. Therefor it is not necessary
-    -- that this common_mem_master_mux maintains an index pipeline
+    -- that this mm_master_mux maintains an index pipeline
     -- from rd until expected rdval. Instead it is sufficient to hold the
     -- index of the active master, until the next master does an access. For
     -- rd access hold the last active index to ensure that rdval will be

libraries/base/mm/tb/vhdl/mm_waitrequest_model.vhd

@@ -52,7 +52,7 @@ USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE common_lib.common_lfsr_sequences_pkg.ALL;
 
-ENTITY common_mem_waitrequest_model IS
+ENTITY mm_waitrequest_model IS
   GENERIC (
     g_waitrequest : BOOLEAN;
     g_seed        : NATURAL := 0;
@@ -65,9 +65,9 @@ ENTITY common_mem_waitrequest_model IS
     slave_mosi  : OUT t_mem_mosi;
     slave_miso  : IN  t_mem_miso
   );
-END common_mem_waitrequest_model;
+END mm_waitrequest_model;
 
-ARCHITECTURE rtl OF common_mem_waitrequest_model IS
+ARCHITECTURE rtl OF mm_waitrequest_model IS
   
   CONSTANT c_prsg_init     : NATURAL := g_seed + 1;  -- PRSG init must be > 0
   

libraries/base/mm/tb/vhdl/tb_mm_bus.vhd

@@ -21,7 +21,7 @@
 -------------------------------------------------------------------------------
 -- 
 -- Author: E. Kooistra
--- Purpose: Test bench for common_mem_bus.vhd
+-- Purpose: Test bench for mm_bus.vhd
 -- Remark:
 -- . This test bench covers:
 --   . g_nof_slaves >= 1
@@ -29,30 +29,30 @@
 --   . g_pipeline_mosi
 --   . g_pipeline_miso_rd
 --   . g_pipeline_miso_wait = FALSE
---   . g_rd_latency >= 1 (using 0 is supported by common_mem_bus, but not by
+--   . g_rd_latency >= 1 (using 0 is supported by mm_bus, but not by
 --     the common_ram_r_w in u_slaves)
 --   . same g_rd_latency for all slaves
 --   . same g_width for all slaves
 --   . regular base address spacing of slaves in c_base_arr
--- . The common_mem_bus.vhd can support a list of arbitrary width slaves, but
---   this tb_common_mem_bus test bench uses an array of fixed width slaves.
+-- . The mm_bus.vhd can support a list of arbitrary width slaves, but
+--   this tb_mm_bus test bench uses an array of fixed width slaves.
 --   It is considered sufficient coverage for this tb and the corresponding
 --   multi tb_tb to also only support regular c_base_arr, same g_rd_latency,
---   and same g_width for all slaves. The tb_common_mem_master_mux also uses a
---   common_mem_bus.vhd and the tb_common_mem_master_mux does uses an array of
+--   and same g_width for all slaves. The tb_mm_master_mux also uses a
+--   mm_bus.vhd and the tb_mm_master_mux does uses an array of
 --   arbitrary width slaves.
 --   
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE;
+LIBRARY IEEE, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
-USE work.common_pkg.ALL;
-USE work.common_mem_pkg.ALL;
-USE work.tb_common_pkg.ALL;
-USE work.tb_common_mem_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
 
-ENTITY tb_common_mem_bus IS
+ENTITY tb_mm_bus IS
  GENERIC (
     g_nof_slaves         : POSITIVE := 1;       -- Number of slave memory interfaces on the MM bus array.
     g_base_offset        : NATURAL := 0;        -- Address of first slave on the MM bus
@@ -63,14 +63,14 @@ ENTITY tb_common_mem_bus IS
     g_pipeline_miso_rd   : BOOLEAN := TRUE;
     g_pipeline_miso_wait : BOOLEAN := FALSE
   );
-END tb_common_mem_bus;
+END tb_mm_bus;
 
 -- Usage:
 --   > as 10
 --   > run -all
 
 
-ARCHITECTURE tb OF tb_common_mem_bus IS
+ARCHITECTURE tb OF tb_mm_bus IS
 
   CONSTANT mm_clk_period   : TIME    := 10 ns;
 
@@ -158,7 +158,7 @@ BEGIN
   END PROCESS;
 
   u_slaves : FOR I IN 0 TO g_nof_slaves-1 GENERATE
-    u_waitrequest_model : ENTITY work.common_mem_waitrequest_model
+    u_waitrequest_model : ENTITY work.mm_waitrequest_model
     GENERIC MAP (
       g_waitrequest => g_waitrequest,
       g_seed        => I
@@ -171,7 +171,7 @@ BEGIN
       slave_miso => ram_miso_arr(I)
     );
   
-    u_ram : ENTITY work.common_ram_r_w
+    u_ram : ENTITY common_lib.common_ram_r_w
     GENERIC MAP (
       g_ram       => c_test_ram,
       g_init_file => "UNUSED"
@@ -190,7 +190,7 @@ BEGIN
     );
   END GENERATE;
 
-  d_dut: ENTITY work.common_mem_bus
+  d_dut: ENTITY work.mm_bus
   GENERIC MAP (
     g_nof_slaves         => g_nof_slaves,
     g_base_arr           => c_base_arr,

libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd

@@ -21,14 +21,14 @@
 -------------------------------------------------------------------------------
 -- 
 -- Author: E. Kooistra
--- Purpose: Test bench for common_mem_master_mux.vhd and also common_mem_bus
+-- Purpose: Test bench for mm_master_mux.vhd and also mm_bus
 -- Description:
---   The test bench uses common_mem_master_mux to access a RAM via an array of
+--   The test bench uses mm_master_mux to access a RAM via an array of
 --   masters. The array of masters is modelled using a stimuli from a single
 --   master that get demultiplexed to the array of masters using
---   common_mem_bus. The address space of the RAM is defined by the g_base_arr
---   and g_width_arr that define the common_mem_bus. Therefore this test bench
---   implicitely also verifies common_mem_bus.vhd.
+--   mm_bus. The address space of the RAM is defined by the g_base_arr
+--   and g_width_arr that define the mm_bus. Therefore this test bench
+--   implicitely also verifies mm_bus.vhd.
 --   
 --               stimuli            master              mux
 --               mosi               mosi_arr            mosi
@@ -38,36 +38,36 @@
 --                                    /         mux
 --                                g_nof_masters
 -- Remark:
---   In an application it is typical to use common_mem_master_mux to connect
---   mulitple masters to multiple slabes via a common_mem_bus MM bus.
+--   In an application it is typical to use mm_master_mux to connect
+--   mulitple masters to multiple slabes via a mm_bus MM bus.
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE;
+LIBRARY IEEE, common_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
-USE work.common_pkg.ALL;
-USE work.common_mem_pkg.ALL;
-USE work.tb_common_pkg.ALL;
-USE work.tb_common_mem_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
 
-ENTITY tb_common_mem_master_mux IS
+ENTITY tb_mm_master_mux IS
  GENERIC (
     g_nof_masters            : POSITIVE := 2;   -- Number of master memory interfaces on the MM bus array.
-    g_base_arr               : t_nat_natural_arr := (0, 256);  -- Address base per slave port of common_mem_bus
-    g_width_arr              : t_nat_natural_arr := (4,   8);  -- Address width per slave port of common_mem_bus
+    g_base_arr               : t_nat_natural_arr := (0, 256);  -- Address base per slave port of mm_bus
+    g_width_arr              : t_nat_natural_arr := (4,   8);  -- Address width per slave port of mm_bus
     g_waitrequest            : BOOLEAN := TRUE;    -- When TRUE model waitrequest by the MM RAM slave, else fixed '0'
     g_pipeline_bus_mosi      : BOOLEAN := FALSE;
     g_pipeline_bus_miso_rd   : BOOLEAN := FALSE;
     g_pipeline_bus_miso_wait : BOOLEAN := FALSE    
   );
-END tb_common_mem_master_mux;
+END tb_mm_master_mux;
 
 -- Usage:
 --   > as 10
 --   > run -all
 
 
-ARCHITECTURE tb OF tb_common_mem_master_mux IS
+ARCHITECTURE tb OF tb_mm_master_mux IS
 
   CONSTANT mm_clk_period   : TIME    := 10 ns;
   
@@ -155,7 +155,7 @@ BEGIN
   END PROCESS;
 
   -- Model multiple masters using stimuli from a single master
-  u_masters : ENTITY work.common_mem_bus
+  u_masters : ENTITY work.mm_bus
   GENERIC MAP (
     g_nof_slaves         => g_nof_masters,
     g_base_arr           => g_base_arr,
@@ -174,7 +174,7 @@ BEGIN
   );
   
   -- DUT = device under test
-  u_dut: ENTITY work.common_mem_master_mux
+  u_dut: ENTITY work.mm_master_mux
   GENERIC MAP (
     g_nof_masters     => g_nof_masters,
     g_rd_latency_min  => c_read_latency
@@ -188,7 +188,7 @@ BEGIN
   );
 
   -- Model master access to MM bus with multiple slaves using a single RAM
-  u_waitrequest_model : ENTITY work.common_mem_waitrequest_model
+  u_waitrequest_model : ENTITY work.mm_waitrequest_model
   GENERIC MAP (
     g_waitrequest => g_waitrequest
   )
@@ -200,7 +200,7 @@ BEGIN
     slave_miso => ram_miso
   );
   
-  u_ram : ENTITY work.common_ram_r_w
+  u_ram : ENTITY common_lib.common_ram_r_w
   GENERIC MAP (
     g_ram       => c_test_ram,
     g_init_file => "UNUSED"

libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd

@@ -21,18 +21,18 @@
 -------------------------------------------------------------------------------
 -- 
 -- Author: E. Kooistra
--- Purpose: Multi test bench for common_mem_bus.vhd
+-- Purpose: Multi test bench for mm_bus.vhd
 --
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE;
+LIBRARY IEEE, common_lib;
 USE IEEE.std_logic_1164.ALL;
-USE work.common_pkg.ALL;
+USE common_lib.common_pkg.ALL;
 
-ENTITY tb_tb_common_mem_bus IS
-END tb_tb_common_mem_bus;
+ENTITY tb_tb_mm_bus IS
+END tb_tb_mm_bus;
 
-ARCHITECTURE tb OF tb_tb_common_mem_bus IS
+ARCHITECTURE tb OF tb_tb_mm_bus IS
   SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
 BEGIN
   -- Usage:
@@ -48,14 +48,14 @@ BEGIN
   -- g_pipeline_miso_rd   : BOOLEAN := TRUE;
   -- g_pipeline_miso_wait : BOOLEAN := FALSE
     
-  u_no_pipe                        : ENTITY work.tb_common_mem_bus GENERIC MAP (16,      0, 3, 1, FALSE, FALSE, FALSE, FALSE);
-  u_no_pipe_base_offset            : ENTITY work.tb_common_mem_bus GENERIC MAP (16, 3*2**4, 4, 1, FALSE, FALSE, FALSE, FALSE);
-  u_pipe_mosi                      : ENTITY work.tb_common_mem_bus GENERIC MAP ( 3,      0, 4, 1, FALSE,  TRUE, FALSE, FALSE);
-  u_pipe_mosi_miso_rd              : ENTITY work.tb_common_mem_bus GENERIC MAP ( 3,      0, 4, 1, FALSE,  TRUE,  TRUE, FALSE);
-  u_waitrequest_no_pipe            : ENTITY work.tb_common_mem_bus GENERIC MAP ( 3,      0, 4, 1,  TRUE, FALSE, FALSE, FALSE);
-  u_waitrequest_pipe_miso_rd       : ENTITY work.tb_common_mem_bus GENERIC MAP ( 3,      0, 4, 1,  TRUE, FALSE,  TRUE, FALSE);
-  u_waitrequest_pipe_miso_rd_rlat2 : ENTITY work.tb_common_mem_bus GENERIC MAP ( 3,      0, 4, 2,  TRUE, FALSE,  TRUE, FALSE);
-  --u_waitrequest_pipe_mosi          : ENTITY work.tb_common_mem_bus GENERIC MAP ( 3,      0, 4, 1,  TRUE,  TRUE, FALSE, FALSE);
-  --u_waitrequest_pipe_mosi_miso_rd  : ENTITY work.tb_common_mem_bus GENERIC MAP ( 3,      0, 4, 1,  TRUE,  TRUE,  TRUE, FALSE);
+  u_no_pipe                        : ENTITY work.tb_mm_bus GENERIC MAP (16,      0, 3, 1, FALSE, FALSE, FALSE, FALSE);
+  u_no_pipe_base_offset            : ENTITY work.tb_mm_bus GENERIC MAP (16, 3*2**4, 4, 1, FALSE, FALSE, FALSE, FALSE);
+  u_pipe_mosi                      : ENTITY work.tb_mm_bus GENERIC MAP ( 3,      0, 4, 1, FALSE,  TRUE, FALSE, FALSE);
+  u_pipe_mosi_miso_rd              : ENTITY work.tb_mm_bus GENERIC MAP ( 3,      0, 4, 1, FALSE,  TRUE,  TRUE, FALSE);
+  u_waitrequest_no_pipe            : ENTITY work.tb_mm_bus GENERIC MAP ( 3,      0, 4, 1,  TRUE, FALSE, FALSE, FALSE);
+  u_waitrequest_pipe_miso_rd       : ENTITY work.tb_mm_bus GENERIC MAP ( 3,      0, 4, 1,  TRUE, FALSE,  TRUE, FALSE);
+  u_waitrequest_pipe_miso_rd_rlat2 : ENTITY work.tb_mm_bus GENERIC MAP ( 3,      0, 4, 2,  TRUE, FALSE,  TRUE, FALSE);
+  --u_waitrequest_pipe_mosi          : ENTITY work.tb_mm_bus GENERIC MAP ( 3,      0, 4, 1,  TRUE,  TRUE, FALSE, FALSE);
+  --u_waitrequest_pipe_mosi_miso_rd  : ENTITY work.tb_mm_bus GENERIC MAP ( 3,      0, 4, 1,  TRUE,  TRUE,  TRUE, FALSE);
   
 END tb;

libraries/base/mm/tb/vhdl/tb_tb_mm_master_mux.vhd

@@ -21,18 +21,18 @@
 -------------------------------------------------------------------------------
 -- 
 -- Author: E. Kooistra
--- Purpose: Multi test bench for common_mem_master_mux.vhd
+-- Purpose: Multi test bench for mm_master_mux.vhd
 --
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE;
+LIBRARY IEEE, common_lib;
 USE IEEE.std_logic_1164.ALL;
-USE work.common_pkg.ALL;
+USE common_lib.common_pkg.ALL;
 
-ENTITY tb_tb_common_mem_master_mux IS
-END tb_tb_common_mem_master_mux;
+ENTITY tb_tb_mm_master_mux IS
+END tb_tb_mm_master_mux;
 
-ARCHITECTURE tb OF tb_tb_common_mem_master_mux IS
+ARCHITECTURE tb OF tb_tb_mm_master_mux IS
   SIGNAL tb_end : STD_LOGIC := '0';  -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
 BEGIN
   -- Usage:
@@ -40,19 +40,19 @@ BEGIN
   -- > run -all
 
   -- g_nof_masters            : POSITIVE := 2;   -- Number of master memory interfaces on the MM bus array.
-  -- g_base_arr               : t_nat_natural_arr := (0, 256);  -- Address base per slave port of common_mem_bus
-  -- g_width_arr              : t_nat_natural_arr := (4,   8);  -- Address width per slave port of common_mem_bus
+  -- g_base_arr               : t_nat_natural_arr := (0, 256);  -- Address base per slave port of mm_bus
+  -- g_width_arr              : t_nat_natural_arr := (4,   8);  -- Address width per slave port of mm_bus
   -- g_waitrequest            : BOOLEAN := FALSE;    -- When TRUE model waitrequest by the MM RAM slave, else fixed '0'
   -- g_pipeline_bus_mosi      : BOOLEAN := FALSE;
   -- g_pipeline_bus_miso_rd   : BOOLEAN := FALSE;
   -- g_pipeline_bus_miso_wait : BOOLEAN := FALSE    
     
-  u_no_pipe                       : ENTITY work.tb_common_mem_master_mux GENERIC MAP (2, (0, 256), (4,   8), FALSE, FALSE, FALSE, FALSE);
-  u_pipe_mosi                     : ENTITY work.tb_common_mem_master_mux GENERIC MAP (2, (0, 256), (4,   8), FALSE,  TRUE, FALSE, FALSE);
-  u_pipe_miso_rd                  : ENTITY work.tb_common_mem_master_mux GENERIC MAP (2, (0, 256), (4,   8), FALSE, FALSE,  TRUE, FALSE);
-  u_waitrequest_no_pipe           : ENTITY work.tb_common_mem_master_mux GENERIC MAP (2, (0, 256), (4,   8),  TRUE, FALSE, FALSE, FALSE);
-  u_waitrequest_pipe_miso_rd      : ENTITY work.tb_common_mem_master_mux GENERIC MAP (2, (0, 256), (4,   8),  TRUE, FALSE,  TRUE, FALSE);
-  --u_waitrequest_pipe_mosi         : ENTITY work.tb_common_mem_master_mux GENERIC MAP (2, (0, 256), (4,   8),  TRUE,  TRUE, FALSE, FALSE);
-  --u_waitrequest_pipe_mosi_miso_rd : ENTITY work.tb_common_mem_master_mux GENERIC MAP (2, (0, 256), (4,   8),  TRUE,  TRUE,  TRUE, FALSE);
+  u_no_pipe                       : ENTITY work.tb_mm_master_mux GENERIC MAP (2, (0, 256), (4,   8), FALSE, FALSE, FALSE, FALSE);
+  u_pipe_mosi                     : ENTITY work.tb_mm_master_mux GENERIC MAP (2, (0, 256), (4,   8), FALSE,  TRUE, FALSE, FALSE);
+  u_pipe_miso_rd                  : ENTITY work.tb_mm_master_mux GENERIC MAP (2, (0, 256), (4,   8), FALSE, FALSE,  TRUE, FALSE);
+  u_waitrequest_no_pipe           : ENTITY work.tb_mm_master_mux GENERIC MAP (2, (0, 256), (4,   8),  TRUE, FALSE, FALSE, FALSE);
+  u_waitrequest_pipe_miso_rd      : ENTITY work.tb_mm_master_mux GENERIC MAP (2, (0, 256), (4,   8),  TRUE, FALSE,  TRUE, FALSE);
+  --u_waitrequest_pipe_mosi         : ENTITY work.tb_mm_master_mux GENERIC MAP (2, (0, 256), (4,   8),  TRUE,  TRUE, FALSE, FALSE);
+  --u_waitrequest_pipe_mosi_miso_rd : ENTITY work.tb_mm_master_mux GENERIC MAP (2, (0, 256), (4,   8),  TRUE,  TRUE,  TRUE, FALSE);
   
 END tb;