Added mm_slave_mux.vhd that wraps common_mem_mux.vhd to provide an single port...

Added mm_slave_mux.vhd that wraps common_mem_mux.vhd to provide an single port MM bus interface to an array of MM slaves.

libraries/base/mm/src/vhdl/mm_slave_mux.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+-- 
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+-- 
+--     http://www.apache.org/licenses/LICENSE-2.0
+-- 
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- 
+-- Author: E. Kooistra
+-- Purpose: Combines an array of MM interfaces into a single MM interface.
+-- Description:
+--   Wraps common_mem_mux.vhd.
+-- Remark:
+--   No need for g_rd_latency pipelining, so pure combinatorial and no need
+--   for clk. If necessary apply pipelining via mm_bus.vhd.
+-------------------------------------------------------------------------------
+
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+
+ENTITY mm_slave_mux IS
+  GENERIC (
+    g_broadcast   : BOOLEAN := FALSE;   -- TRUE use port[0] to access all, else use separate ports
+    g_nof_mosi    : POSITIVE := 256;    -- Number of slave memory interfaces in the array.
+    g_mosi_addr_w : POSITIVE := 8       -- Address width per slave
+  );
+  PORT (
+    mosi     : IN  t_mem_mosi;
+    miso     : OUT t_mem_miso;
+    mosi_arr : OUT t_mem_mosi_arr(g_nof_mosi - 1 DOWNTO 0); 
+    miso_arr : IN  t_mem_miso_arr(g_nof_mosi - 1 DOWNTO 0) := (OTHERS=>c_mem_miso_rst)
+  );
+END mm_slave_mux;
+
+ARCHITECTURE str OF mm_slave_mux IS
+BEGIN
+
+  u_common_mem_mux : ENTITY common_lib.common_mem_mux
+  GENERIC MAP (
+    g_broadcast   => g_broadcast,
+    g_nof_mosi    => g_nof_mosi,
+    g_mult_addr_w => g_mosi_addr_w,
+    g_rd_latency  => 0
+  )
+  PORT MAP (
+    clk      => '0',   -- only used when g_rd_latency > 0
+    mosi     => mosi,
+    miso     => miso,
+    mosi_arr => mosi_arr,
+    miso_arr => miso_arr
+  );
+  
+END str;