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Commit 5364b786 authored by Eric Kooistra's avatar Eric Kooistra
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No need to use ip/ and no need to use *_top.vhd.

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libraries/technology/ip_arria10/mac_10g/README.txt
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View file @ 5364b786
...@@ -39,18 +39,17 @@ No synthesis trials were done, because this will implicitely be done when the IP ...@@ -39,18 +39,17 @@ No synthesis trials were done, because this will implicitely be done when the IP
generated/ip_arria10_mac_10g.qip generated/ip_arria10_mac_10g.qip
is included in the ip/hdllib.cfg and contains what is needed to synthesize the IP. is included in the hdllib.cfg and contains what is needed to synthesize the IP.
5) Remarks 5) Remarks
a) Generated ip_arria10_mac_10g.vhd uses IP specific library ip_arria10_mac_10g_alt_em10g32_140 a) Use generated IP specific library clause name
The ip/hdllib.cfg defines the IP specific library to make it known: The generated ip_arria10_<lib_name>.vhd uses an IP specific library name. Therefore the hdllib.cfg uses the IP
specific library as library claus name to make it known:
hdl_lib_name = ip_arria10_mac_10g_alt_em10g32_140 hdl_lib_name = ip_arria10_<lib_name>
hdl_library_clause_name = ip_arria10_mac_10g_alt_em10g32_140 hdl_library_clause_name = ip_arria10_<lib_name>_<ip_specific>
The ip_arria10_mac_10g_top.vhd wrapper makes the IP accessible via ip_arria10_mac_10g_lib, to
avoid that the IP specific library needs to be used at the technology independent level.
\ No newline at end of file
libraries/technology/ip_arria10/mac_10g/hdllib.cfg
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− 6
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hdl_lib_name = ip_arria10_mac_10g hdl_lib_name = ip_arria10_mac_10g
hdl_library_clause_name = ip_arria10_mac_10g_lib hdl_library_clause_name = ip_arria10_mac_10g_alt_em10g32_140
hdl_lib_uses = ip_arria10_mac_10g_alt_em10g32_140 hdl_lib_uses =
hdl_lib_technology = ip_arria10 hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
synth_files = synth_files =
ip_arria10_mac_10g_top.vhd
test_bench_files = test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
#$RADIOHDL/libraries/technology/ip_arria10/mac_10g/generated_tb/generated/sim/ip_arria10_mac_10g_tb.vhd
modelsim_search_libraries = quartus_qip_files =
altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver generated/ip_arria10_mac_10g.qip
altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
libraries/technology/ip_arria10/mac_10g/ip/hdllib.cfg deleted 100644 → 0
+ 0
− 20
View file @ e062a646
hdl_lib_name = ip_arria10_mac_10g_alt_em10g32_140
hdl_library_clause_name = ip_arria10_mac_10g_alt_em10g32_140
hdl_lib_uses =
hdl_lib_technology = ip_arria10
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/mac_10g/ip/compile_ip.tcl
synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
#$RADIOHDL/libraries/technology/ip_arria10/mac_10g/generated_tb/generated/sim/ip_arria10_mac_10g_tb.vhd
quartus_qip_files =
generated/ip_arria10_mac_10g.qip
libraries/technology/ip_arria10/mac_10g/ip_arria10_mac_10g_top.vhd deleted 100644 → 0
+ 0
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-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Purpose: Wrapper for generated ip_arria10_mac_10g.vhd
-- Description:
-- This wrapper avoids the need to vmap the ip_arria10_mac_10g_alt_em10g32_140 library
-- in the technology independent library that instantiate this IP.
-- Remarks:
-- . Manually created from generated ip_arria10_mac_10g.vhd.
library IEEE;
use IEEE.std_logic_1164.all;
library ip_arria10_mac_10g_alt_em10g32_140;
entity ip_arria10_mac_10g_top is
port (
csr_read : in std_logic := '0'; -- csr.read
csr_write : in std_logic := '0'; -- .write
csr_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
csr_readdata : out std_logic_vector(31 downto 0); -- .readdata
csr_waitrequest : out std_logic; -- .waitrequest
csr_address : in std_logic_vector(12 downto 0) := (others => '0'); -- .address
tx_312_5_clk : in std_logic := '0'; -- tx_312_5_clk.clk
tx_156_25_clk : in std_logic := '0'; -- tx_156_25_clk.clk
rx_312_5_clk : in std_logic := '0'; -- rx_312_5_clk.clk
rx_156_25_clk : in std_logic := '0'; -- rx_156_25_clk.clk
csr_clk : in std_logic := '0'; -- csr_clk.clk
csr_rst_n : in std_logic := '0'; -- csr_rst_n.reset_n
tx_rst_n : in std_logic := '0'; -- tx_rst_n.reset_n
rx_rst_n : in std_logic := '0'; -- rx_rst_n.reset_n
avalon_st_tx_startofpacket : in std_logic := '0'; -- avalon_st_tx.startofpacket
avalon_st_tx_endofpacket : in std_logic := '0'; -- .endofpacket
avalon_st_tx_valid : in std_logic := '0'; -- .valid
avalon_st_tx_data : in std_logic_vector(63 downto 0) := (others => '0'); -- .data
avalon_st_tx_empty : in std_logic_vector(2 downto 0) := (others => '0'); -- .empty
avalon_st_tx_error : in std_logic := '0'; -- .error
avalon_st_tx_ready : out std_logic; -- .ready
avalon_st_pause_data : in std_logic_vector(1 downto 0) := (others => '0'); -- avalon_st_pause.data
xgmii_tx : out std_logic_vector(71 downto 0); -- xgmii_tx.data
avalon_st_txstatus_valid : out std_logic; -- avalon_st_txstatus.valid
avalon_st_txstatus_data : out std_logic_vector(39 downto 0); -- .data
avalon_st_txstatus_error : out std_logic_vector(6 downto 0); -- .error
xgmii_rx : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_rx.data
link_fault_status_xgmii_rx_data : out std_logic_vector(1 downto 0); -- link_fault_status_xgmii_rx.data
avalon_st_rx_data : out std_logic_vector(63 downto 0); -- avalon_st_rx.data
avalon_st_rx_startofpacket : out std_logic; -- .startofpacket
avalon_st_rx_valid : out std_logic; -- .valid
avalon_st_rx_empty : out std_logic_vector(2 downto 0); -- .empty
avalon_st_rx_error : out std_logic_vector(5 downto 0); -- .error
avalon_st_rx_ready : in std_logic := '0'; -- .ready
avalon_st_rx_endofpacket : out std_logic; -- .endofpacket
avalon_st_rxstatus_valid : out std_logic; -- avalon_st_rxstatus.valid
avalon_st_rxstatus_data : out std_logic_vector(39 downto 0); -- .data
avalon_st_rxstatus_error : out std_logic_vector(6 downto 0); -- .error
unidirectional_en : out std_logic; -- unidirectional.en
unidirectional_remote_fault_dis : out std_logic -- .remote_fault_dis
);
end ip_arria10_mac_10g_top;
architecture str of ip_arria10_mac_10g_top is
begin
u_ip_arria10_mac_10g : entity ip_arria10_mac_10g_alt_em10g32_140.ip_arria10_mac_10g
port map (
csr_read => csr_read , -- csr.read
csr_write => csr_write , -- .write
csr_writedata => csr_writedata , -- .writedata
csr_readdata => csr_readdata , -- .readdata
csr_waitrequest => csr_waitrequest , -- .waitrequest
csr_address => csr_address , -- .address
tx_312_5_clk => tx_312_5_clk , -- tx_312_5_clk.clk
tx_156_25_clk => tx_156_25_clk , -- tx_156_25_clk.clk
rx_312_5_clk => rx_312_5_clk , -- rx_312_5_clk.clk
rx_156_25_clk => rx_156_25_clk , -- rx_156_25_clk.clk
csr_clk => csr_clk , -- csr_clk.clk
csr_rst_n => csr_rst_n , -- csr_rst_n.reset_n
tx_rst_n => tx_rst_n , -- tx_rst_n.reset_n
rx_rst_n => rx_rst_n , -- rx_rst_n.reset_n
avalon_st_tx_startofpacket => avalon_st_tx_startofpacket , -- avalon_st_tx.startofpacket
avalon_st_tx_endofpacket => avalon_st_tx_endofpacket , -- .endofpacket
avalon_st_tx_valid => avalon_st_tx_valid , -- .valid
avalon_st_tx_data => avalon_st_tx_data , -- .data
avalon_st_tx_empty => avalon_st_tx_empty , -- .empty
avalon_st_tx_error => avalon_st_tx_error , -- .error
avalon_st_tx_ready => avalon_st_tx_ready , -- .ready
avalon_st_pause_data => avalon_st_pause_data , -- avalon_st_pause.data
xgmii_tx => xgmii_tx , -- xgmii_tx.data
avalon_st_txstatus_valid => avalon_st_txstatus_valid , -- avalon_st_txstatus.valid
avalon_st_txstatus_data => avalon_st_txstatus_data , -- .data
avalon_st_txstatus_error => avalon_st_txstatus_error , -- .error
xgmii_rx => xgmii_rx , -- xgmii_rx.data
link_fault_status_xgmii_rx_data => link_fault_status_xgmii_rx_data, -- link_fault_status_xgmii_rx.data
avalon_st_rx_data => avalon_st_rx_data , -- avalon_st_rx.data
avalon_st_rx_startofpacket => avalon_st_rx_startofpacket , -- .startofpacket
avalon_st_rx_valid => avalon_st_rx_valid , -- .valid
avalon_st_rx_empty => avalon_st_rx_empty , -- .empty
avalon_st_rx_error => avalon_st_rx_error , -- .error
avalon_st_rx_ready => avalon_st_rx_ready , -- .ready
avalon_st_rx_endofpacket => avalon_st_rx_endofpacket , -- .endofpacket
avalon_st_rxstatus_valid => avalon_st_rxstatus_valid , -- avalon_st_rxstatus.valid
avalon_st_rxstatus_data => avalon_st_rxstatus_data , -- .data
avalon_st_rxstatus_error => avalon_st_rxstatus_error , -- .error
unidirectional_en => unidirectional_en , -- unidirectional.en
unidirectional_remote_fault_dis => unidirectional_remote_fault_dis -- .remote_fault_dis
);
end str;
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