UPdated the default register value from all '1's to a single '1'

libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd

@@ -89,7 +89,7 @@ BEGIN
     g_in_new_latency     => 1,   
     g_readback           => TRUE,
     g_reg                => c_mm_reg,
-    g_init_reg           => (OTHERS => '1')
+    g_init_reg           => TO_UVEC(1, c_word_w)
   )
   PORT MAP (
     -- Clocks and reset