From 515e127af0028263d33a219637147e4ce58e4f67 Mon Sep 17 00:00:00 2001
From: Pepping <pepping>
Date: Tue, 3 May 2016 11:03:20 +0000
Subject: [PATCH] UPdated the default register value from all '1's to a single
'1'
---
libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
index cc62e58d40..715fea29d7 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
@@ -89,7 +89,7 @@ BEGIN
g_in_new_latency => 1,
g_readback => TRUE,
g_reg => c_mm_reg,
- g_init_reg => (OTHERS => '1')
+ g_init_reg => TO_UVEC(1, c_word_w)
)
PORT MAP (
-- Clocks and reset
--
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