Declared mm_file component in mm_file_pkg.vhd to avoid having to do it in each tb or mmm file.

applications/stagiair/designs/stagiair_unb1_pwm_gen/src/vhdl/mmm_stagiair_unb1_pwm_gen.vhd

@@ -256,25 +256,6 @@ ARCHITECTURE str OF mmm_stagiair_unb1_pwm_gen IS
   ); 
   END COMPONENT qsys_stagiair_unb1_pwm_gen;
 
-  ----------------------------------------------------------------------------
-  -- mm_file component
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_mm_clk_period     : TIME := c_mm_clk_period;
-    g_update_on_change  : BOOLEAN := FALSE;
-    g_mm_rd_latency     : NATURAL := 1
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso 
-  );
-  END COMPONENT;
-
-
 BEGIN
 
   mm_clk   <= i_mm_clk;

applications/stagiair/designs/stagiair_unb1_terminal/src/vhdl/mmm_stagiair_unb1_terminal.vhd

@@ -178,21 +178,6 @@ ARCHITECTURE str OF mmm_stagiair_unb1_terminal IS
   SIGNAL mm_rst_n              : STD_LOGIC ;
   SIGNAL sim_eth1g_reg_mosi    : t_mem_mosi;
 
-  COMPONENT mm_file IS
-    GENERIC (
-      g_file_prefix      : STRING ;
-      g_mm_clk_period    : TIME    := 8 ns;
-      g_update_on_change : BOOLEAN := FALSE;
-      g_mm_rd_latency    : NATURAL := 1
-    );
-    PORT (
-      mm_rst        : IN  STD_LOGIC;
-      mm_clk        : IN  STD_LOGIC;
-      mm_master_out : OUT t_mem_mosi := c_mem_mosi_rst;
-      mm_master_in  : IN  t_mem_miso := c_mem_miso_rst
-    );
-  END COMPONENT mm_file;
-  
   COMPONENT qsys_stagiair_unb1_terminal IS
     PORT (
       reg_diag_bg_reset_export              : out std_logic;

applications/stagiair/designs/stagiair_unb1_wave_gen/src/vhdl/mmm_stagiair_unb1_wave_gen.vhd

@@ -123,25 +123,6 @@ ARCHITECTURE str OF mmm_stagiair_unb1_wave_gen IS
   SIGNAL i_mm_clk   : STD_LOGIC := '1';
   SIGNAL i_epcs_clk : STD_LOGIC := '1';
 
-  ----------------------------------------------------------------------------
-  -- mm_file component
-  ----------------------------------------------------------------------------
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;
-    g_mm_clk_period     : TIME := c_mm_clk_period;
-    g_update_on_change  : BOOLEAN := FALSE;
-    g_mm_rd_latency     : NATURAL := 1
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso 
-  );
-  END COMPONENT;
-
-
 BEGIN
 
   mm_clk   <= i_mm_clk;

applications/stagiair/libraries/terminal/tb/vhdl/tb_terminal_node.vhd

@@ -96,19 +96,6 @@ ARCHITECTURE t_bench OF tb_terminal_node IS
   SIGNAL fn_in_mesh_serial_3arr  : t_unb1_board_mesh_sl_3arr;
   SIGNAL fn_out_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
 
-  COMPONENT mm_file
-    GENERIC(
-      g_file_prefix       : STRING;
-      g_update_on_change  : BOOLEAN := FALSE
-    );
-    PORT(
-      mm_rst              : IN STD_LOGIC;
-      mm_clk              : IN STD_LOGIC;
-      mm_master_out       : OUT t_mem_mosi;
-      mm_master_in        : IN t_mem_miso
-    );
-  END COMPONENT;
-
 BEGIN
   mm_clk      <= NOT mm_clk AFTER c_mm_clk_period/2;
   mm_rst      <= '1', '0'   AFTER c_mm_clk_period*5;

applications/stagiair/libraries/wave_gen/tb/vhdl/tb_pwm_gen.vhd

@@ -71,19 +71,6 @@ ARCHITECTURE bench OF tb_pwm_gen IS
   SIGNAL reg_diag_data_buffer_mosi  : t_mem_mosi;
   SIGNAL reg_diag_data_buffer_miso  : t_mem_miso;
 
-  COMPONENT mm_file
-    GENERIC(
-      g_file_prefix       : STRING;
-      g_update_on_change  : BOOLEAN := FALSE
-    );
-    PORT(
-      mm_rst        : IN STD_LOGIC;
-      mm_clk        : IN STD_LOGIC;
-      mm_master_out : OUT t_mem_mosi;
-      mm_master_in  : IN t_mem_miso
-    );
-  END COMPONENT;
-
 BEGIN
   dp_clk  <= (NOT dp_clk) OR stop_clock AFTER clk_half_period;
   mm_clk  <= (NOT mm_clk) AFTER clk_half_period*7;

applications/stagiair/libraries/wave_gen/tb/vhdl/tb_wave_gen.vhd

@@ -37,19 +37,6 @@ ARCHITECTURE bench OF tb_wave_gen IS
   -------
   SIGNAL sync_sig			 : STD_LOGIC := '0';
   
-  COMPONENT mm_file
-  GENERIC(
-    g_file_prefix       : STRING;    
-    g_update_on_change  : BOOLEAN := FALSE
-  );
-  PORT (
-    mm_rst        : IN  STD_LOGIC;
-    mm_clk        : IN  STD_LOGIC;
-    mm_master_out : OUT t_mem_mosi;
-    mm_master_in  : IN  t_mem_miso 
-  );
-  END COMPONENT; 
-
 BEGIN
 
   dp_clk <= (NOT dp_clk) OR stop_clock AFTER clk_period/2;