diff --git a/applications/stagiair/designs/stagiair_unb1_pwm_gen/src/vhdl/mmm_stagiair_unb1_pwm_gen.vhd b/applications/stagiair/designs/stagiair_unb1_pwm_gen/src/vhdl/mmm_stagiair_unb1_pwm_gen.vhd
index 6b35937828880ae4467f713fdee7d240c240c0db..88d61b8270ae40dc4d632f79affe73c76f7cbaf5 100644
--- a/applications/stagiair/designs/stagiair_unb1_pwm_gen/src/vhdl/mmm_stagiair_unb1_pwm_gen.vhd
+++ b/applications/stagiair/designs/stagiair_unb1_pwm_gen/src/vhdl/mmm_stagiair_unb1_pwm_gen.vhd
@@ -256,25 +256,6 @@ ARCHITECTURE str OF mmm_stagiair_unb1_pwm_gen IS
);
END COMPONENT qsys_stagiair_unb1_pwm_gen;
- ----------------------------------------------------------------------------
- -- mm_file component
- ----------------------------------------------------------------------------
- COMPONENT mm_file
- GENERIC(
- g_file_prefix : STRING;
- g_mm_clk_period : TIME := c_mm_clk_period;
- g_update_on_change : BOOLEAN := FALSE;
- g_mm_rd_latency : NATURAL := 1
- );
- PORT (
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
- mm_master_out : OUT t_mem_mosi;
- mm_master_in : IN t_mem_miso
- );
- END COMPONENT;
-
-
BEGIN
mm_clk <= i_mm_clk;
diff --git a/applications/stagiair/designs/stagiair_unb1_terminal/src/vhdl/mmm_stagiair_unb1_terminal.vhd b/applications/stagiair/designs/stagiair_unb1_terminal/src/vhdl/mmm_stagiair_unb1_terminal.vhd
index 6215cf25f5a3e89365a1f9ef70cd8e6725f0eab8..a1dd2cff60a64ad4010d96ef1dc2ef743a67b2dc 100644
--- a/applications/stagiair/designs/stagiair_unb1_terminal/src/vhdl/mmm_stagiair_unb1_terminal.vhd
+++ b/applications/stagiair/designs/stagiair_unb1_terminal/src/vhdl/mmm_stagiair_unb1_terminal.vhd
@@ -178,21 +178,6 @@ ARCHITECTURE str OF mmm_stagiair_unb1_terminal IS
SIGNAL mm_rst_n : STD_LOGIC ;
SIGNAL sim_eth1g_reg_mosi : t_mem_mosi;
- COMPONENT mm_file IS
- GENERIC (
- g_file_prefix : STRING ;
- g_mm_clk_period : TIME := 8 ns;
- g_update_on_change : BOOLEAN := FALSE;
- g_mm_rd_latency : NATURAL := 1
- );
- PORT (
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
- mm_master_out : OUT t_mem_mosi := c_mem_mosi_rst;
- mm_master_in : IN t_mem_miso := c_mem_miso_rst
- );
- END COMPONENT mm_file;
-
COMPONENT qsys_stagiair_unb1_terminal IS
PORT (
reg_diag_bg_reset_export : out std_logic;
diff --git a/applications/stagiair/designs/stagiair_unb1_wave_gen/src/vhdl/mmm_stagiair_unb1_wave_gen.vhd b/applications/stagiair/designs/stagiair_unb1_wave_gen/src/vhdl/mmm_stagiair_unb1_wave_gen.vhd
index 89855d9c6a2ad9970fb574b807583d7b8942f9a3..5c5d9ba76f83972a760c69a9ce3b0641a9883933 100644
--- a/applications/stagiair/designs/stagiair_unb1_wave_gen/src/vhdl/mmm_stagiair_unb1_wave_gen.vhd
+++ b/applications/stagiair/designs/stagiair_unb1_wave_gen/src/vhdl/mmm_stagiair_unb1_wave_gen.vhd
@@ -123,25 +123,6 @@ ARCHITECTURE str OF mmm_stagiair_unb1_wave_gen IS
SIGNAL i_mm_clk : STD_LOGIC := '1';
SIGNAL i_epcs_clk : STD_LOGIC := '1';
- ----------------------------------------------------------------------------
- -- mm_file component
- ----------------------------------------------------------------------------
- COMPONENT mm_file
- GENERIC(
- g_file_prefix : STRING;
- g_mm_clk_period : TIME := c_mm_clk_period;
- g_update_on_change : BOOLEAN := FALSE;
- g_mm_rd_latency : NATURAL := 1
- );
- PORT (
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
- mm_master_out : OUT t_mem_mosi;
- mm_master_in : IN t_mem_miso
- );
- END COMPONENT;
-
-
BEGIN
mm_clk <= i_mm_clk;
diff --git a/applications/stagiair/libraries/terminal/tb/vhdl/tb_terminal_node.vhd b/applications/stagiair/libraries/terminal/tb/vhdl/tb_terminal_node.vhd
index db516aa26b60c0257fe82a9b42054e70beae6786..95ddcb18841de8d424aef06b8bd5eb074df18508 100644
--- a/applications/stagiair/libraries/terminal/tb/vhdl/tb_terminal_node.vhd
+++ b/applications/stagiair/libraries/terminal/tb/vhdl/tb_terminal_node.vhd
@@ -96,19 +96,6 @@ ARCHITECTURE t_bench OF tb_terminal_node IS
SIGNAL fn_in_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
SIGNAL fn_out_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
- COMPONENT mm_file
- GENERIC(
- g_file_prefix : STRING;
- g_update_on_change : BOOLEAN := FALSE
- );
- PORT(
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
- mm_master_out : OUT t_mem_mosi;
- mm_master_in : IN t_mem_miso
- );
- END COMPONENT;
-
BEGIN
mm_clk <= NOT mm_clk AFTER c_mm_clk_period/2;
mm_rst <= '1', '0' AFTER c_mm_clk_period*5;
diff --git a/applications/stagiair/libraries/wave_gen/tb/vhdl/tb_pwm_gen.vhd b/applications/stagiair/libraries/wave_gen/tb/vhdl/tb_pwm_gen.vhd
index da48889b1e57b7f99e334d18e64a42f3fca4233b..04af7b54327871cbfc9226fa19a6ac566b040127 100644
--- a/applications/stagiair/libraries/wave_gen/tb/vhdl/tb_pwm_gen.vhd
+++ b/applications/stagiair/libraries/wave_gen/tb/vhdl/tb_pwm_gen.vhd
@@ -71,19 +71,6 @@ ARCHITECTURE bench OF tb_pwm_gen IS
SIGNAL reg_diag_data_buffer_mosi : t_mem_mosi;
SIGNAL reg_diag_data_buffer_miso : t_mem_miso;
- COMPONENT mm_file
- GENERIC(
- g_file_prefix : STRING;
- g_update_on_change : BOOLEAN := FALSE
- );
- PORT(
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
- mm_master_out : OUT t_mem_mosi;
- mm_master_in : IN t_mem_miso
- );
- END COMPONENT;
-
BEGIN
dp_clk <= (NOT dp_clk) OR stop_clock AFTER clk_half_period;
mm_clk <= (NOT mm_clk) AFTER clk_half_period*7;
diff --git a/applications/stagiair/libraries/wave_gen/tb/vhdl/tb_wave_gen.vhd b/applications/stagiair/libraries/wave_gen/tb/vhdl/tb_wave_gen.vhd
index 1a74bc95facb514085688a8aa448461d00972387..1bc70b160559a70f192704bac7b50f505fda171b 100644
--- a/applications/stagiair/libraries/wave_gen/tb/vhdl/tb_wave_gen.vhd
+++ b/applications/stagiair/libraries/wave_gen/tb/vhdl/tb_wave_gen.vhd
@@ -37,19 +37,6 @@ ARCHITECTURE bench OF tb_wave_gen IS
-------
SIGNAL sync_sig : STD_LOGIC := '0';
- COMPONENT mm_file
- GENERIC(
- g_file_prefix : STRING;
- g_update_on_change : BOOLEAN := FALSE
- );
- PORT (
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
- mm_master_out : OUT t_mem_mosi;
- mm_master_in : IN t_mem_miso
- );
- END COMPONENT;
-
BEGIN
dp_clk <= (NOT dp_clk) OR stop_clock AFTER clk_period/2;