Skip to content
Snippets Groups Projects
Commit 4e0cd1ea authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
Browse files

setup all entities for different revisions

parent 207f047c
No related branches found
No related tags found
No related merge requests found
Hide whitespace changes
Inline Side-by-side
Showing
with 45 additions and 190 deletions
boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
+ 1
− 1
View file @ 4e0cd1ea
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
......
boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
+ 4
− 20
View file @ 4e0cd1ea
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
......@@ -36,10 +36,7 @@ ENTITY unb1_test_10GbE IS
g_sim_node_nr : NATURAL := 0; -- FN0
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
g_nof_MB : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
g_use_MB_I : NATURAL := 0; -- 1: use MB_I 0: do not use
g_use_MB_II : NATURAL := 0
g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
);
PORT (
-- GENERAL
......@@ -89,12 +86,7 @@ ENTITY unb1_test_10GbE IS
BN_BI_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-- SO-DIMM Memory Bank I
MB_I_IN : IN t_tech_ddr3_phy_in;
MB_I_IO : INOUT t_tech_ddr3_phy_io;
MB_I_OU : OUT t_tech_ddr3_phy_ou
BN_BI_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0)
);
END unb1_test_10GbE;
......@@ -162,15 +154,7 @@ BEGIN
BN_BI_2_TX => BN_BI_2_TX,
BN_BI_2_RX => BN_BI_2_RX,
BN_BI_3_TX => BN_BI_3_TX,
BN_BI_3_RX => BN_BI_3_RX,
MB_I_IN => MB_I_IN,
MB_I_IO => MB_I_IO,
MB_I_OU => MB_I_OU
-- MB_II_IN => MB_II_IN,
-- MB_II_IO => MB_II_IO,
-- MB_II_OU => MB_II_OU
BN_BI_3_RX => BN_BI_3_RX
);
END str;
......
boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
+ 6
− 6
View file @ 4e0cd1ea
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
......@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
-- Purpose: Test bench for unb1_test_10GbE.
-- Purpose: Test bench for unb1_test_1GbE.
-- Description: see tb_unb1_test
......@@ -28,15 +28,15 @@ LIBRARY IEEE, unb1_test_lib;
USE IEEE.std_logic_1164.ALL;
ENTITY tb_unb1_test_10GbE IS
END tb_unb1_test_10GbE;
ENTITY tb_unb1_test_1GbE IS
END tb_unb1_test_1GbE;
ARCHITECTURE tb OF tb_unb1_test_10GbE IS
ARCHITECTURE tb OF tb_unb1_test_1GbE IS
BEGIN
u_tb_unb1_test : ENTITY unb1_test_lib.tb_unb1_test
GENERIC MAP (
g_design_name => "unb1_test_10GbE",
g_design_name => "unb1_test_1GbE",
--g_sim_node_nr => 7 -- BN3
g_sim_node_nr => 0 --FN0
);
......
boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
+ 10
− 83
View file @ 4e0cd1ea
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
......@@ -20,26 +20,22 @@
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
LIBRARY IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY unb1_test_10GbE IS
ENTITY unb1_test_1GbE IS
GENERIC (
g_design_name : STRING := "unb1_test_10GbE"; -- use revision name = entity name = design name
g_design_note : STRING := "Test Design with 10GbE";
g_design_name : STRING := "unb1_test_1GbE"; -- use revision name = entity name = design name
g_design_note : STRING := "Test Design with 1GbE";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0; -- FN0
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
g_nof_MB : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
g_use_MB_I : NATURAL := 0; -- 1: use MB_I 0: do not use
g_use_MB_II : NATURAL := 0
g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
);
PORT (
-- GENERAL
......@@ -61,45 +57,12 @@ ENTITY unb1_test_10GbE IS
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC;
ETH_SGOUT : OUT STD_LOGIC;
-- Transceiver clocks
SA_CLK : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
-- Serial I/O
SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO)
SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_RSTN : OUT STD_LOGIC := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
BN_BI_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-- SO-DIMM Memory Bank I
MB_I_IN : IN t_tech_ddr3_phy_in;
MB_I_IO : INOUT t_tech_ddr3_phy_io;
MB_I_OU : OUT t_tech_ddr3_phy_ou
ETH_SGOUT : OUT STD_LOGIC
);
END unb1_test_10GbE;
END unb1_test_1GbE;
ARCHITECTURE str OF unb1_test_10GbE IS
ARCHITECTURE str OF unb1_test_1GbE IS
BEGIN
......@@ -134,43 +97,7 @@ BEGIN
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT,
-- Transceiver clocks
SA_CLK => SA_CLK,
-- Serial I/O
SI_FN_0_TX => SI_FN_0_TX,
SI_FN_0_RX => SI_FN_0_RX,
SI_FN_1_TX => SI_FN_1_TX,
SI_FN_1_RX => SI_FN_1_RX,
SI_FN_2_TX => SI_FN_2_TX,
SI_FN_2_RX => SI_FN_2_RX,
SI_FN_3_TX => SI_FN_3_TX,
SI_FN_3_RX => SI_FN_3_RX,
SI_FN_0_CNTRL => SI_FN_0_CNTRL,
SI_FN_1_CNTRL => SI_FN_1_CNTRL,
SI_FN_2_CNTRL => SI_FN_2_CNTRL,
SI_FN_3_CNTRL => SI_FN_3_CNTRL,
SI_FN_RSTN => SI_FN_RSTN,
BN_BI_0_TX => BN_BI_0_TX,
BN_BI_0_RX => BN_BI_0_RX,
BN_BI_1_TX => BN_BI_1_TX,
BN_BI_1_RX => BN_BI_1_RX,
BN_BI_2_TX => BN_BI_2_TX,
BN_BI_2_RX => BN_BI_2_RX,
BN_BI_3_TX => BN_BI_3_TX,
BN_BI_3_RX => BN_BI_3_RX,
MB_I_IN => MB_I_IN,
MB_I_IO => MB_I_IO,
MB_I_OU => MB_I_OU
-- MB_II_IN => MB_II_IN,
-- MB_II_IO => MB_II_IO,
-- MB_II_OU => MB_II_OU
ETH_SGOUT => ETH_SGOUT
);
END str;
......
boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
+ 6
− 6
View file @ 4e0cd1ea
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
......@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
-- Purpose: Test bench for unb1_test_10GbE.
-- Purpose: Test bench for unb1_test_all.
-- Description: see tb_unb1_test
......@@ -28,15 +28,15 @@ LIBRARY IEEE, unb1_test_lib;
USE IEEE.std_logic_1164.ALL;
ENTITY tb_unb1_test_10GbE IS
END tb_unb1_test_10GbE;
ENTITY tb_unb1_test_all IS
END tb_unb1_test_all;
ARCHITECTURE tb OF tb_unb1_test_10GbE IS
ARCHITECTURE tb OF tb_unb1_test_all IS
BEGIN
u_tb_unb1_test : ENTITY unb1_test_lib.tb_unb1_test
GENERIC MAP (
g_design_name => "unb1_test_10GbE",
g_design_name => "unb1_test_all",
--g_sim_node_nr => 7 -- BN3
g_sim_node_nr => 0 --FN0
);
......
boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
+ 6
− 6
View file @ 4e0cd1ea
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
......@@ -27,10 +27,10 @@ USE unb1_board_lib.unb1_board_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY unb1_test_10GbE IS
ENTITY unb1_test_all IS
GENERIC (
g_design_name : STRING := "unb1_test_10GbE"; -- use revision name = entity name = design name
g_design_note : STRING := "Test Design with 10GbE";
g_design_name : STRING := "unb1_test_all"; -- use revision name = entity name = design name
g_design_note : STRING := "Test Design with all";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0; -- FN0
......@@ -96,10 +96,10 @@ ENTITY unb1_test_10GbE IS
MB_I_IO : INOUT t_tech_ddr3_phy_io;
MB_I_OU : OUT t_tech_ddr3_phy_ou
);
END unb1_test_10GbE;
END unb1_test_all;
ARCHITECTURE str OF unb1_test_10GbE IS
ARCHITECTURE str OF unb1_test_all IS
BEGIN
......
boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
+ 6
− 6
View file @ 4e0cd1ea
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
......@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
-- Purpose: Test bench for unb1_test_10GbE.
-- Purpose: Test bench for unb1_test_ddr.
-- Description: see tb_unb1_test
......@@ -28,15 +28,15 @@ LIBRARY IEEE, unb1_test_lib;
USE IEEE.std_logic_1164.ALL;
ENTITY tb_unb1_test_10GbE IS
END tb_unb1_test_10GbE;
ENTITY tb_unb1_test_ddr IS
END tb_unb1_test_ddr;
ARCHITECTURE tb OF tb_unb1_test_10GbE IS
ARCHITECTURE tb OF tb_unb1_test_ddr IS
BEGIN
u_tb_unb1_test : ENTITY unb1_test_lib.tb_unb1_test
GENERIC MAP (
g_design_name => "unb1_test_10GbE",
g_design_name => "unb1_test_ddr",
--g_sim_node_nr => 7 -- BN3
g_sim_node_nr => 0 --FN0
);
......
boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
+ 6
− 62
View file @ 4e0cd1ea
-------------------------------------------------------------------------------
--
-- Copyright (C) 2014
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
......@@ -27,10 +27,10 @@ USE unb1_board_lib.unb1_board_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY unb1_test_10GbE IS
ENTITY unb1_test_ddr IS
GENERIC (
g_design_name : STRING := "unb1_test_10GbE"; -- use revision name = entity name = design name
g_design_note : STRING := "Test Design with 10GbE";
g_design_name : STRING := "unb1_test_ddr"; -- use revision name = entity name = design name
g_design_note : STRING := "Test Design with ddr";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0; -- FN0
......@@ -63,43 +63,15 @@ ENTITY unb1_test_10GbE IS
ETH_SGIN : IN STD_LOGIC;
ETH_SGOUT : OUT STD_LOGIC;
-- Transceiver clocks
SA_CLK : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
-- Serial I/O
SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO)
SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_RSTN : OUT STD_LOGIC := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
BN_BI_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-- SO-DIMM Memory Bank I
MB_I_IN : IN t_tech_ddr3_phy_in;
MB_I_IO : INOUT t_tech_ddr3_phy_io;
MB_I_OU : OUT t_tech_ddr3_phy_ou
);
END unb1_test_10GbE;
END unb1_test_ddr;
ARCHITECTURE str OF unb1_test_10GbE IS
ARCHITECTURE str OF unb1_test_ddr IS
BEGIN
......@@ -136,34 +108,6 @@ BEGIN
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT,
-- Transceiver clocks
SA_CLK => SA_CLK,
-- Serial I/O
SI_FN_0_TX => SI_FN_0_TX,
SI_FN_0_RX => SI_FN_0_RX,
SI_FN_1_TX => SI_FN_1_TX,
SI_FN_1_RX => SI_FN_1_RX,
SI_FN_2_TX => SI_FN_2_TX,
SI_FN_2_RX => SI_FN_2_RX,
SI_FN_3_TX => SI_FN_3_TX,
SI_FN_3_RX => SI_FN_3_RX,
SI_FN_0_CNTRL => SI_FN_0_CNTRL,
SI_FN_1_CNTRL => SI_FN_1_CNTRL,
SI_FN_2_CNTRL => SI_FN_2_CNTRL,
SI_FN_3_CNTRL => SI_FN_3_CNTRL,
SI_FN_RSTN => SI_FN_RSTN,
BN_BI_0_TX => BN_BI_0_TX,
BN_BI_0_RX => BN_BI_0_RX,
BN_BI_1_TX => BN_BI_1_TX,
BN_BI_1_RX => BN_BI_1_RX,
BN_BI_2_TX => BN_BI_2_TX,
BN_BI_2_RX => BN_BI_2_RX,
BN_BI_3_TX => BN_BI_3_TX,
BN_BI_3_RX => BN_BI_3_RX,
MB_I_IN => MB_I_IN,
MB_I_IO => MB_I_IO,
MB_I_OU => MB_I_OU
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment