diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
index 2df05adc26b6bd89131d69d836305fc3ea93a778..6cd7b0966c0ac9dc39b9669295960faf6d90894f 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2012
+-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
index b63296d9cd6f30a8831544b9d423240a408fb670..2da9d631c6e4942d4ade5b6d98afa3dfedbb3d67 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
@@ -36,10 +36,7 @@ ENTITY unb1_test_10GbE IS
g_sim_node_nr : NATURAL := 0; -- FN0
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
- g_nof_MB : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
- g_use_MB_I : NATURAL := 0; -- 1: use MB_I 0: do not use
- g_use_MB_II : NATURAL := 0
+ g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
);
PORT (
-- GENERAL
@@ -89,12 +86,7 @@ ENTITY unb1_test_10GbE IS
BN_BI_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
BN_BI_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- BN_BI_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-
- -- SO-DIMM Memory Bank I
- MB_I_IN : IN t_tech_ddr3_phy_in;
- MB_I_IO : INOUT t_tech_ddr3_phy_io;
- MB_I_OU : OUT t_tech_ddr3_phy_ou
+ BN_BI_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0)
);
END unb1_test_10GbE;
@@ -162,15 +154,7 @@ BEGIN
BN_BI_2_TX => BN_BI_2_TX,
BN_BI_2_RX => BN_BI_2_RX,
BN_BI_3_TX => BN_BI_3_TX,
- BN_BI_3_RX => BN_BI_3_RX,
-
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU
-
--- MB_II_IN => MB_II_IN,
--- MB_II_IO => MB_II_IO,
--- MB_II_OU => MB_II_OU
+ BN_BI_3_RX => BN_BI_3_RX
);
END str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
index 2df05adc26b6bd89131d69d836305fc3ea93a778..14e0877e5d76dacaf90c15422f7abeafd7747c6a 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2012
+-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
--- Purpose: Test bench for unb1_test_10GbE.
+-- Purpose: Test bench for unb1_test_1GbE.
-- Description: see tb_unb1_test
@@ -28,15 +28,15 @@ LIBRARY IEEE, unb1_test_lib;
USE IEEE.std_logic_1164.ALL;
-ENTITY tb_unb1_test_10GbE IS
-END tb_unb1_test_10GbE;
+ENTITY tb_unb1_test_1GbE IS
+END tb_unb1_test_1GbE;
-ARCHITECTURE tb OF tb_unb1_test_10GbE IS
+ARCHITECTURE tb OF tb_unb1_test_1GbE IS
BEGIN
u_tb_unb1_test : ENTITY unb1_test_lib.tb_unb1_test
GENERIC MAP (
- g_design_name => "unb1_test_10GbE",
+ g_design_name => "unb1_test_1GbE",
--g_sim_node_nr => 7 -- BN3
g_sim_node_nr => 0 --FN0
);
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
index b63296d9cd6f30a8831544b9d423240a408fb670..64b772e1d3f1d3931015d407074cae8a5a6ae586 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
@@ -20,26 +20,22 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib, tech_ddr_lib;
+LIBRARY IEEE, common_lib, unb1_board_lib, unb1_test_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
-USE tech_ddr_lib.tech_ddr_pkg.ALL;
-ENTITY unb1_test_10GbE IS
+ENTITY unb1_test_1GbE IS
GENERIC (
- g_design_name : STRING := "unb1_test_10GbE"; -- use revision name = entity name = design name
- g_design_note : STRING := "Test Design with 10GbE";
+ g_design_name : STRING := "unb1_test_1GbE"; -- use revision name = entity name = design name
+ g_design_note : STRING := "Test Design with 1GbE";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0; -- FN0
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
- g_nof_MB : NATURAL := c_unb1_board_nof_ddr3; -- Fixed control infrastructure for 2 modules per FPGA
- g_use_MB_I : NATURAL := 0; -- 1: use MB_I 0: do not use
- g_use_MB_II : NATURAL := 0
+ g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
);
PORT (
-- GENERAL
@@ -61,45 +57,12 @@ ENTITY unb1_test_10GbE IS
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC;
- ETH_SGOUT : OUT STD_LOGIC;
-
- -- Transceiver clocks
- SA_CLK : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
-
- -- Serial I/O
- SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-
- SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO)
- SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
- SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
- SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
- SI_FN_RSTN : OUT STD_LOGIC := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
-
- BN_BI_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- BN_BI_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- BN_BI_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- BN_BI_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- BN_BI_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- BN_BI_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- BN_BI_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- BN_BI_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-
- -- SO-DIMM Memory Bank I
- MB_I_IN : IN t_tech_ddr3_phy_in;
- MB_I_IO : INOUT t_tech_ddr3_phy_io;
- MB_I_OU : OUT t_tech_ddr3_phy_ou
+ ETH_SGOUT : OUT STD_LOGIC
);
-END unb1_test_10GbE;
+END unb1_test_1GbE;
-ARCHITECTURE str OF unb1_test_10GbE IS
+ARCHITECTURE str OF unb1_test_1GbE IS
BEGIN
@@ -134,43 +97,7 @@ BEGIN
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT,
-
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- Serial I/O
- SI_FN_0_TX => SI_FN_0_TX,
- SI_FN_0_RX => SI_FN_0_RX,
- SI_FN_1_TX => SI_FN_1_TX,
- SI_FN_1_RX => SI_FN_1_RX,
- SI_FN_2_TX => SI_FN_2_TX,
- SI_FN_2_RX => SI_FN_2_RX,
- SI_FN_3_TX => SI_FN_3_TX,
- SI_FN_3_RX => SI_FN_3_RX,
-
- SI_FN_0_CNTRL => SI_FN_0_CNTRL,
- SI_FN_1_CNTRL => SI_FN_1_CNTRL,
- SI_FN_2_CNTRL => SI_FN_2_CNTRL,
- SI_FN_3_CNTRL => SI_FN_3_CNTRL,
- SI_FN_RSTN => SI_FN_RSTN,
-
- BN_BI_0_TX => BN_BI_0_TX,
- BN_BI_0_RX => BN_BI_0_RX,
- BN_BI_1_TX => BN_BI_1_TX,
- BN_BI_1_RX => BN_BI_1_RX,
- BN_BI_2_TX => BN_BI_2_TX,
- BN_BI_2_RX => BN_BI_2_RX,
- BN_BI_3_TX => BN_BI_3_TX,
- BN_BI_3_RX => BN_BI_3_RX,
-
- MB_I_IN => MB_I_IN,
- MB_I_IO => MB_I_IO,
- MB_I_OU => MB_I_OU
-
--- MB_II_IN => MB_II_IN,
--- MB_II_IO => MB_II_IO,
--- MB_II_OU => MB_II_OU
+ ETH_SGOUT => ETH_SGOUT
);
END str;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
index 2df05adc26b6bd89131d69d836305fc3ea93a778..2db5522ba40b133d2c077600a3a05ee0c32f6996 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2012
+-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
--- Purpose: Test bench for unb1_test_10GbE.
+-- Purpose: Test bench for unb1_test_all.
-- Description: see tb_unb1_test
@@ -28,15 +28,15 @@ LIBRARY IEEE, unb1_test_lib;
USE IEEE.std_logic_1164.ALL;
-ENTITY tb_unb1_test_10GbE IS
-END tb_unb1_test_10GbE;
+ENTITY tb_unb1_test_all IS
+END tb_unb1_test_all;
-ARCHITECTURE tb OF tb_unb1_test_10GbE IS
+ARCHITECTURE tb OF tb_unb1_test_all IS
BEGIN
u_tb_unb1_test : ENTITY unb1_test_lib.tb_unb1_test
GENERIC MAP (
- g_design_name => "unb1_test_10GbE",
+ g_design_name => "unb1_test_all",
--g_sim_node_nr => 7 -- BN3
g_sim_node_nr => 0 --FN0
);
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
index b63296d9cd6f30a8831544b9d423240a408fb670..4ca4e1ab6c759c667437a523addfc3caa4d6fe08 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
@@ -27,10 +27,10 @@ USE unb1_board_lib.unb1_board_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
-ENTITY unb1_test_10GbE IS
+ENTITY unb1_test_all IS
GENERIC (
- g_design_name : STRING := "unb1_test_10GbE"; -- use revision name = entity name = design name
- g_design_note : STRING := "Test Design with 10GbE";
+ g_design_name : STRING := "unb1_test_all"; -- use revision name = entity name = design name
+ g_design_note : STRING := "Test Design with all";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0; -- FN0
@@ -96,10 +96,10 @@ ENTITY unb1_test_10GbE IS
MB_I_IO : INOUT t_tech_ddr3_phy_io;
MB_I_OU : OUT t_tech_ddr3_phy_ou
);
-END unb1_test_10GbE;
+END unb1_test_all;
-ARCHITECTURE str OF unb1_test_10GbE IS
+ARCHITECTURE str OF unb1_test_all IS
BEGIN
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
index 2df05adc26b6bd89131d69d836305fc3ea93a778..6dfe2c6a163d1c8db504a63279c60df4cf3341cf 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2012
+-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
--- Purpose: Test bench for unb1_test_10GbE.
+-- Purpose: Test bench for unb1_test_ddr.
-- Description: see tb_unb1_test
@@ -28,15 +28,15 @@ LIBRARY IEEE, unb1_test_lib;
USE IEEE.std_logic_1164.ALL;
-ENTITY tb_unb1_test_10GbE IS
-END tb_unb1_test_10GbE;
+ENTITY tb_unb1_test_ddr IS
+END tb_unb1_test_ddr;
-ARCHITECTURE tb OF tb_unb1_test_10GbE IS
+ARCHITECTURE tb OF tb_unb1_test_ddr IS
BEGIN
u_tb_unb1_test : ENTITY unb1_test_lib.tb_unb1_test
GENERIC MAP (
- g_design_name => "unb1_test_10GbE",
+ g_design_name => "unb1_test_ddr",
--g_sim_node_nr => 7 -- BN3
g_sim_node_nr => 0 --FN0
);
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
index b63296d9cd6f30a8831544b9d423240a408fb670..3388ac2b8c606b8585e901ab3757f755ade771d7 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2014
+-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
@@ -27,10 +27,10 @@ USE unb1_board_lib.unb1_board_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE tech_ddr_lib.tech_ddr_pkg.ALL;
-ENTITY unb1_test_10GbE IS
+ENTITY unb1_test_ddr IS
GENERIC (
- g_design_name : STRING := "unb1_test_10GbE"; -- use revision name = entity name = design name
- g_design_note : STRING := "Test Design with 10GbE";
+ g_design_name : STRING := "unb1_test_ddr"; -- use revision name = entity name = design name
+ g_design_note : STRING := "Test Design with ddr";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0; -- FN0
@@ -63,43 +63,15 @@ ENTITY unb1_test_10GbE IS
ETH_SGIN : IN STD_LOGIC;
ETH_SGOUT : OUT STD_LOGIC;
- -- Transceiver clocks
- SA_CLK : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
-
- -- Serial I/O
- SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-
- SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO)
- SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
- SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
- SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
- SI_FN_RSTN : OUT STD_LOGIC := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
-
- BN_BI_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- BN_BI_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- BN_BI_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- BN_BI_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- BN_BI_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- BN_BI_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- BN_BI_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- BN_BI_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-
-- SO-DIMM Memory Bank I
MB_I_IN : IN t_tech_ddr3_phy_in;
MB_I_IO : INOUT t_tech_ddr3_phy_io;
MB_I_OU : OUT t_tech_ddr3_phy_ou
);
-END unb1_test_10GbE;
+END unb1_test_ddr;
-ARCHITECTURE str OF unb1_test_10GbE IS
+ARCHITECTURE str OF unb1_test_ddr IS
BEGIN
@@ -136,34 +108,6 @@ BEGIN
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT,
- -- Transceiver clocks
- SA_CLK => SA_CLK,
-
- -- Serial I/O
- SI_FN_0_TX => SI_FN_0_TX,
- SI_FN_0_RX => SI_FN_0_RX,
- SI_FN_1_TX => SI_FN_1_TX,
- SI_FN_1_RX => SI_FN_1_RX,
- SI_FN_2_TX => SI_FN_2_TX,
- SI_FN_2_RX => SI_FN_2_RX,
- SI_FN_3_TX => SI_FN_3_TX,
- SI_FN_3_RX => SI_FN_3_RX,
-
- SI_FN_0_CNTRL => SI_FN_0_CNTRL,
- SI_FN_1_CNTRL => SI_FN_1_CNTRL,
- SI_FN_2_CNTRL => SI_FN_2_CNTRL,
- SI_FN_3_CNTRL => SI_FN_3_CNTRL,
- SI_FN_RSTN => SI_FN_RSTN,
-
- BN_BI_0_TX => BN_BI_0_TX,
- BN_BI_0_RX => BN_BI_0_RX,
- BN_BI_1_TX => BN_BI_1_TX,
- BN_BI_1_RX => BN_BI_1_RX,
- BN_BI_2_TX => BN_BI_2_TX,
- BN_BI_2_RX => BN_BI_2_RX,
- BN_BI_3_TX => BN_BI_3_TX,
- BN_BI_3_RX => BN_BI_3_RX,
-
MB_I_IN => MB_I_IN,
MB_I_IO => MB_I_IO,
MB_I_OU => MB_I_OU