From 4cb207f61c75de337d8d965022bcd9ec72a43cb6 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Mon, 2 Jul 2018 15:45:13 +0000
Subject: [PATCH] testbench should be skipped when the seleted technology is
not stratixiv
---
libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd b/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd
index 01e642e948..55052febaf 100644
--- a/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd
@@ -48,12 +48,13 @@ BEGIN
u_tech : ENTITY work.tb_tr_nonbonded GENERIC MAP (FALSE, 32, 0) PORT MAP (tb_end_vec(0));
u_sim : ENTITY work.tb_tr_nonbonded GENERIC MAP (FALSE, 32, 1) PORT MAP (tb_end_vec(1));
- tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0';
+ tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec OR c_tech_select_default /= c_tech_stratixiv ELSE '0';
p_tb_end : PROCESS
BEGIN
WAIT UNTIL tb_end='1';
- WAIT FOR 1 ns;
+ ASSERT (c_tech_select_default = c_tech_stratixiv) REPORT "Technology is not stratixiv, skipping testbench..." SEVERITY WARNING;
+ WAIT FOR 1 ms;
REPORT "Multi tb simulation finished." SEVERITY FAILURE;
WAIT;
END PROCESS;
--
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