Skip to content
Snippets Groups Projects
Commit 4bb16a0f authored by Jonathan Hargreaves's avatar Jonathan Hargreaves
Browse files

IP for unb2b FPGA Arria 10 version e1sg

parent b69b23c2
No related branches found
No related tags found
No related merge requests found
Showing
with 5656 additions and 0 deletions
#------------------------------------------------------------------------------
#
# Copyright (C) 2015
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_151_mhuabmq_seq_cal_sim.hex ./
file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_151_mhuabmq_seq_cal_synth.hex ./
file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_151_mhuabmq_seq_params_sim.hex ./
file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_151_mhuabmq_seq_params_synth.hex ./
}
#!/bin/bash
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2014
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# -------------------------------------------------------------------------- #
#
# Purpose: Generate IP with Qsys
# Description:
# Generate the IP in a separate generated/ subdirectory.
#
# Usage:
#
# ./generate_ip.sh
#
# Tool settings for selected target "unb2" with arria10
. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
# Only generate the source IP
# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
qsys-generate ip_arria10_e1sg_ddr4_4g_2000.qsys \
--synthesis=VHDL \
--simulation=VHDL \
--output-directory=generated \
--allow-mixed-language-simulation
# Also generate the testbench IP, this is not useful because it only generates bus functional models, so not a DDR4 memory model
#qsys-generate ip_arria10_e1sg_ddr4_4g_2000.qsys \
# --synthesis=VHDL \
# --simulation=VHDL \
# --testbench=STANDARD \
# --testbench-simulation=VHDL \
# --output-directory=generated \
# --allow-mixed-language-simulation \
# --allow-mixed-language-testbench-simulation
hdl_lib_name = ip_arria10_e1sg_ddr4_4g_2000
hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_2000_altera_emif_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_ddr4_4g_2000.qip
#------------------------------------------------------------------------------
#
# Copyright (C) 2015
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_151_4thorvi_seq_cal_sim.hex ./
file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_151_4thorvi_seq_cal_synth.hex ./
file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_151_4thorvi_seq_params_sim.hex ./
file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_151_4thorvi_seq_params_synth.hex ./
}
#!/bin/bash
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2014
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# -------------------------------------------------------------------------- #
#
# Purpose: Generate IP with Qsys
# Description:
# Generate the IP in a separate generated/ subdirectory.
#
# Usage:
#
# ./generate_ip.sh
#
# Tool settings for selected target "unb2" with arria10
. ${RADIOHDL}/tools/quartus/set_quartus unb2b
#qsys-generate --help
# Only generate the source IP
# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
qsys-generate ip_arria10_e1sg_ddr4_8g_1600.qsys \
--synthesis=VHDL \
--simulation=VHDL \
--output-directory=generated \
--allow-mixed-language-simulation
# Also generate the testbench IP, this is not useful because it only generates bus functional models, so not a DDR4 memory model
#qsys-generate ip_arria10_e1sg_ddr4_8g_1600.qsys \
# --synthesis=VHDL \
# --simulation=VHDL \
# --testbench=STANDARD \
# --testbench-simulation=VHDL \
# --output-directory=generated \
# --allow-mixed-language-simulation \
# --allow-mixed-language-testbench-simulation
hdl_lib_name = ip_arria10_e1sg_ddr4_8g_1600
hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_1600_altera_emif_151
hdl_lib_uses_synth =
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
generated/ip_arria10_e1sg_ddr4_8g_1600.qip
#------------------------------------------------------------------------------
#
# Copyright (C) 2015
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
#------------------------------------------------------------------------------
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_151_izxxuoi_seq_cal_sim.hex ./
file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_151_izxxuoi_seq_cal_synth.hex ./
file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_151_izxxuoi_seq_params_sim.hex ./
file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_151_izxxuoi_seq_params_synth.hex ./
}
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment