diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/clkbuf_global/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..39a7312b5aea86d6d9d13ec5e36eb700ec66c700
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_clkbuf_global.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..14f3f61a13058046e33eb6c53108ea9c2e7aec8e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_clkbuf_global
+hdl_library_clause_name = ip_arria10_e1sg_clkbuf_global_altclkctrl_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_clkbuf_global.qip
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/ip_arria10_e1sg_clkbuf_global.qsys b/libraries/technology/ip_arria10_e1sg/clkbuf_global/ip_arria10_e1sg_clkbuf_global.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..5a82a2c34c5fce90d05435d140ce193ed2233d94
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/ip_arria10_e1sg_clkbuf_global.qsys
@@ -0,0 +1,76 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_clkbuf_global">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element altclkctrl_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="altclkctrl_input"
+ internal="altclkctrl_0.altclkctrl_input"
+ type="conduit"
+ dir="end">
+ <port name="inclk" internal="inclk" />
+ </interface>
+ <interface
+ name="altclkctrl_output"
+ internal="altclkctrl_0.altclkctrl_output"
+ type="conduit"
+ dir="end">
+ <port name="outclk" internal="outclk" />
+ </interface>
+ <module
+ name="altclkctrl_0"
+ kind="altclkctrl"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CLOCK_TYPE" value="1" />
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="ENA_REGISTER_MODE" value="1" />
+ <parameter name="GUI_USE_ENA" value="false" />
+ <parameter name="NUMBER_OF_CLOCKS" value="1" />
+ <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt b/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..6884ec9c599bf7d01ffed812c8a3a2a9bbb09398
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
@@ -0,0 +1,55 @@
+README.txt for $RADIOHDL/libraries/technology/ip_arria10/complex_mult
+
+1) Porting
+2) IP component
+3) Compilation, simulation and verification
+4) Synthesis
+5) Remarks
+
+
+1) Porting
+
+The complex_mult IP was ported manually from Quartus v11.1 for Stratix IV to Quartus 15.0 for Arria10 by creating it in Qsys using
+the same parameter settings.
+
+
+2) IP component
+
+The generated IP is not kept in SVN, only the Qsys source file:
+
+ ip_arria10_complex_mult.qsys
+
+Therefore first the IP needs to be generated using:
+
+ ./generate_ip.sh
+
+
+3) Compilation, simulation and verification
+
+The generated IP also contains a msim_setup.tcl file that was used to manually create:
+
+ compile_ip.tcl
+
+This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code.
+
+
+4) Synthesis
+
+No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
+
+ generated/ip_arria10_complex_mult.qip
+
+is included in the hdllib.cfg and contains what is needed to synthesize the IP.
+
+
+5) Remarks
+
+a) Use generated IP specific library clause name
+
+ The generated ip_arria10_<lib_name>.vhd uses an IP specific library name. Therefore the hdllib.cfg uses the IP
+ specific library as library clause name to make it known:
+
+ hdl_lib_name = ip_arria10_<lib_name>
+ hdl_library_clause_name = ip_arria10_<lib_name>_<ip_specific>
+
+
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..6b0c071a9632de4f561a52e42d492934044c5732
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_complex_mult.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..baa00061ca3863f46ff5df86ca27206063477c26
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_complex_mult
+hdl_library_clause_name = ip_arria10_e1sg_complex_mult_altmult_complex_150
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_complex_mult.qip
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/ip_arria10_e1sg_complex_mult.qsys b/libraries/technology/ip_arria10_e1sg/complex_mult/ip_arria10_e1sg_complex_mult.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..b7de4d1abcbfcde62d6443bc231e69336f062fe7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/ip_arria10_e1sg_complex_mult.qsys
@@ -0,0 +1,89 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_complex_mult">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element altmult_complex_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="complex_input"
+ internal="altmult_complex_0.complex_input"
+ type="conduit"
+ dir="end">
+ <port name="aclr" internal="aclr" />
+ <port name="clock" internal="clock" />
+ <port name="dataa_imag" internal="dataa_imag" />
+ <port name="dataa_real" internal="dataa_real" />
+ <port name="datab_imag" internal="datab_imag" />
+ <port name="datab_real" internal="datab_real" />
+ <port name="ena" internal="ena" />
+ </interface>
+ <interface
+ name="complex_output"
+ internal="altmult_complex_0.complex_output"
+ type="conduit"
+ dir="end">
+ <port name="result_imag" internal="result_imag" />
+ <port name="result_real" internal="result_real" />
+ </interface>
+ <module
+ name="altmult_complex_0"
+ kind="altmult_complex"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_CLEAR_TYPE" value="ACLR" />
+ <parameter name="GUI_DYNAMIC_COMPLEX" value="false" />
+ <parameter name="GUI_USE_CLKEN" value="true" />
+ <parameter name="IMPLEMENTATION_STYLE" value="AUTO" />
+ <parameter name="PIPELINE" value="3" />
+ <parameter name="REPRESENTATION_A" value="1" />
+ <parameter name="REPRESENTATION_B" value="1" />
+ <parameter name="WIDTH_A" value="18" />
+ <parameter name="WIDTH_B" value="18" />
+ <parameter name="WIDTH_RESULT" value="36" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/README.txt b/libraries/technology/ip_arria10_e1sg/ddio/README.txt
new file mode 100755
index 0000000000000000000000000000000000000000..6ba19729bb9e0c499398db1ef5661a55845e419f
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddio/README.txt
@@ -0,0 +1,73 @@
+README.txt for $RADIOHDL/libraries/technology/ip_arria10/ddio
+
+Contents:
+
+1) DDIO components
+2) Arria10 IP
+3) Synthesis trials
+4) Issues
+
+
+1) DDIO components:
+ ip_arria10_ddio_in.vhd = Double Date Rate input
+ ip_arria10_ddio_out.vhd = Double Date Rate output
+
+
+2) Arria10 IP
+
+ The StratixIV IP uses altddio_in and altddio_out. First a Megawizard file for this StratixIV IP was made using the settings that
+ were used in common_ddio_in.vhd and common_ddio_out.vhd. This Megawizard IP file was then opened in Quartus to be able to let
+ Quartus 14 convert them using the altera_gpio component for Arria10.
+
+ The altera_gpio component is not part of the default Quartus 14.0a10 tool libraries, but instead it is created by Qsys together
+ with the IP. This makes that the altera_gpio can not easily be used in simulation and synthesis like was possible with altera_mf
+ in for Stratix IV (Quartus 11.1).
+
+ The ddio_in component is used by the PPSH and the ddio_out component is used by the ADUH. In both cases the g_width=1.
+ The Arria10 IP can be generated using a fixed width of 1. Therefore the width was set to 1 in the conversion from MegaWizard
+ to Qsys and the qsys files are stored as:
+
+ ip_arria10_ddio_in_1.qsys
+ ip_arria10_ddio_out_1.qsys
+
+ If the application would need a wider port then it can achieve this by instantiating the IP multiple times. This approach
+ avoids having to generate DDIO IP for every possible width. An alternative would be:
+ - to generate IP for e.g. width=16 and assuming that that is sufficient for all applications. Any application that uses less
+ width then leaves these IO unconnected so that the unused IO will get optimized away by synthesis.
+ - create the IP when it is needed, this scheme is more difficult to manage but is something to consider for the future.
+
+ The IP needs to be generated with:
+
+ ./generate_ip.sh
+
+ to create the simulation and synthesis files, because these are initially not kept in SVN.
+
+
+3) Synthesis trials
+
+ The Quartus project:
+
+ quartus/ddio.qpf
+
+ was used to verify that the DDIO IP actually synthesise to the appropriate FPGA resources.
+ Use the Quartus GUI to manually select a top level component for synthesis e.g. by right clicking the entity vhd file
+ in the file tab of the Quartus project navigator window.
+ Then check the resource usage in the synthesis and fitter reports.
+
+
+4) Issues
+
+a) Simulation model does not work (for Quartus 14.1, not tried for Quartus 15.0)
+
+ The simulation model for the DDIO does not compile ok because a din port is missing in the ddio_out en a dout port is
+ missing in the ddio_in. Adding this ports manualy does work for compile, but when the component is loaded as a simulation
+ then Modelsim reports some internal error on the IP. The compile also does not work when using 'do msim_setup.tcl', so
+ there is something wrong with the DDIO simulation model. The synthesis of the DDIO IP using ddio.qpf does work.
+
+ The work around is not not use the simulation model, but instead use a behavioral simulation model for the IP:
+ sim/ip_arria10_ddio_in_1.vhd
+ sim/ip_arria10_ddio_out_1.vhd
+ sim/tb_ip_arria10_ddio_1.vhd = self checking tb for ip_arria10_ddio_in_1 -> ip_arria10_ddio_out_1
+
+ The selection between the IP model or the behavioral model is made in the compile_ip.tcl script.
+
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..38843a33037ea6f47ed7430e5ab1ce4d9a996502
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddio/generate_ip.sh
@@ -0,0 +1,43 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Remark:
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+qsys-generate ip_arria10_e1sg_ddio_in_1.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
+qsys-generate ip_arria10_e1sg_ddio_out_1.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..4e22b8d9620d1fe0ecf1b54bb05435d87e53a7b5
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
@@ -0,0 +1,22 @@
+hdl_lib_name = ip_arria10_e1sg_ddio
+hdl_library_clause_name = ip_arria10_e1sg_ddio_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+ ip_arria10_e1sg_ddio_in.vhd
+ ip_arria10_e1sg_ddio_out.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_ddio_in_1.qip
+ generated/ip_arria10_e1sg_ddio_out_1.qip
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in.vhd b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..01883fe6fd18606c5bae30f8d04bdbe0a8591675
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in.vhd
@@ -0,0 +1,69 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Wrapper for ip_arria10_e1sg_ddio_in_1 to support g_width >= 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY ip_arria10_e1sg_ddio_in IS
+ GENERIC (
+ g_width : NATURAL := 1
+ );
+ PORT (
+ in_dat : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ in_clk : IN STD_LOGIC;
+ in_clk_en : IN STD_LOGIC := '1'; -- Not Connected
+ rst : IN STD_LOGIC := '0';
+ out_dat_hi : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ out_dat_lo : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+ );
+END ip_arria10_e1sg_ddio_in;
+
+
+ARCHITECTURE str OF ip_arria10_e1sg_ddio_in IS
+
+ component ip_arria10_e1sg_ddio_in_1 is
+ port (
+ datain : in std_logic_vector(0 downto 0) := (others => '0'); -- pad_in.export
+ inclock : in std_logic := '0'; -- ck.export
+ aclr : in std_logic := '0'; -- aclr.export
+ dataout_h : out std_logic_vector(0 downto 0); -- dataout_h.fragment
+ dataout_l : out std_logic_vector(0 downto 0) -- dataout_l.fragment
+ );
+ end component;
+
+BEGIN
+
+ gen_w : FOR I IN g_width-1 DOWNTO 0 GENERATE
+
+ u_ip_arria10_e1sg_ddio_in_1 : ip_arria10_e1sg_ddio_in_1
+ PORT MAP (
+ datain => in_dat(I DOWNTO I),
+ inclock => in_clk,
+ aclr => rst,
+ dataout_h => out_dat_hi(I DOWNTO I),
+ dataout_l => out_dat_lo(I DOWNTO I)
+ );
+
+ END GENERATE;
+
+END str;
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in_1.qsys b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in_1.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..650a26ccf8d254fc397445b09f1cebe4498c888f
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in_1.qsys
@@ -0,0 +1,110 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_ddio_in_1">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element ip_arria10_ddio_in_1
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="aclr"
+ internal="ip_arria10_ddio_in_1.aclr"
+ type="conduit"
+ dir="end">
+ <port name="aclr" internal="aclr" />
+ </interface>
+ <interface name="ck" internal="ip_arria10_ddio_in_1.ck" type="conduit" dir="end">
+ <port name="inclock" internal="inclock" />
+ </interface>
+ <interface
+ name="dataout_h"
+ internal="ip_arria10_ddio_in_1.dataout_h"
+ type="conduit"
+ dir="end">
+ <port name="dataout_h" internal="dataout_h" />
+ </interface>
+ <interface
+ name="dataout_l"
+ internal="ip_arria10_ddio_in_1.dataout_l"
+ type="conduit"
+ dir="end">
+ <port name="dataout_l" internal="dataout_l" />
+ </interface>
+ <interface name="din" internal="ip_arria10_ddio_in_1.din" />
+ <interface name="dout" internal="ip_arria10_ddio_in_1.dout" />
+ <interface
+ name="pad_in"
+ internal="ip_arria10_ddio_in_1.pad_in"
+ type="conduit"
+ dir="end">
+ <port name="datain" internal="datain" />
+ </interface>
+ <interface name="pad_out" internal="ip_arria10_ddio_in_1.pad_out" />
+ <module
+ name="ip_arria10_ddio_in_1"
+ kind="altera_gpio"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="AUTO_DEVICE" value="10AX115S2F45E1SG" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
+ <parameter name="EXT_DRIVER_PARAM" value="false" />
+ <parameter name="GENERATE_SDC_FILE" value="false" />
+ <parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_in_port_map.csv</parameter>
+ <parameter name="PIN_TYPE_GUI" value="Input" />
+ <parameter name="SIZE" value="1" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_areset_mode" value="Clear" />
+ <parameter name="gui_bus_hold" value="false" />
+ <parameter name="gui_diff_buff" value="false" />
+ <parameter name="gui_enable_cke" value="false" />
+ <parameter name="gui_enable_migratable_port_names" value="true" />
+ <parameter name="gui_enable_termination_ports" value="false" />
+ <parameter name="gui_hr_logic" value="false" />
+ <parameter name="gui_io_reg_mode" value="DDIO" />
+ <parameter name="gui_open_drain" value="false" />
+ <parameter name="gui_pseudo_diff" value="false" />
+ <parameter name="gui_separate_io_clks" value="false" />
+ <parameter name="gui_sreset_mode" value="None" />
+ <parameter name="gui_use_oe" value="false" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out.vhd b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a650300cd6e1d4e1abfdd212e1238dfca3b63c94
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out.vhd
@@ -0,0 +1,67 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Wrapper for ip_arria10_e1sg_ddio_out_1 to support g_width >= 1
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY ip_arria10_e1sg_ddio_out IS
+ GENERIC(
+ g_width : NATURAL := 1
+ );
+ PORT (
+ rst : IN STD_LOGIC := '0';
+ in_clk : IN STD_LOGIC;
+ in_clk_en : IN STD_LOGIC := '1'; -- Not Connected
+ in_dat_hi : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ in_dat_lo : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
+ out_dat : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
+ );
+END ip_arria10_e1sg_ddio_out;
+
+
+ARCHITECTURE str OF ip_arria10_e1sg_ddio_out IS
+
+ component ip_arria10_e1sg_ddio_out_1 is
+ port (
+ dataout : out std_logic_vector(0 downto 0); -- pad_out.export
+ outclock : in std_logic := '0'; -- ck.export
+ aclr : in std_logic := '0'; -- aclr.export
+ datain_h : in std_logic_vector(0 downto 0) := (others => '0'); -- datain_h.fragment
+ datain_l : in std_logic_vector(0 downto 0) := (others => '0') -- datain_l.fragment
+ );
+ end component;
+
+BEGIN
+
+ gen_w : FOR I IN g_width-1 DOWNTO 0 GENERATE
+ u_ip_arria10_e1sg_ddio_out_1 : ip_arria10_e1sg_ddio_out_1
+ PORT MAP (
+ dataout => out_dat(I DOWNTO I),
+ outclock => in_clk,
+ aclr => rst,
+ datain_h => in_dat_hi(I DOWNTO I),
+ datain_l => in_dat_lo(I DOWNTO I)
+ );
+ END GENERATE;
+
+END str;
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out_1.qsys b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out_1.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..f6a9713e2b4372c162640086bfb7dd9cad836f4e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out_1.qsys
@@ -0,0 +1,112 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_ddio_out_1">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element ip_arria10_ddio_out_1
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="aclr"
+ internal="ip_arria10_ddio_out_1.aclr"
+ type="conduit"
+ dir="end">
+ <port name="aclr" internal="aclr" />
+ </interface>
+ <interface
+ name="ck"
+ internal="ip_arria10_ddio_out_1.ck"
+ type="conduit"
+ dir="end">
+ <port name="inclock" internal="inclock" />
+ </interface>
+ <interface
+ name="datain_h"
+ internal="ip_arria10_ddio_out_1.datain_h"
+ type="conduit"
+ dir="end">
+ <port name="datain_h" internal="datain_h" />
+ </interface>
+ <interface
+ name="datain_l"
+ internal="ip_arria10_ddio_out_1.datain_l"
+ type="conduit"
+ dir="end">
+ <port name="datain_l" internal="datain_l" />
+ </interface>
+ <interface name="din" internal="ip_arria10_ddio_out_1.din" />
+ <interface
+ name="pad_out"
+ internal="ip_arria10_ddio_out_1.pad_out"
+ type="conduit"
+ dir="end">
+ <port name="dataout" internal="dataout" />
+ </interface>
+ <module
+ name="ip_arria10_ddio_out_1"
+ kind="altera_gpio"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="AUTO_DEVICE" value="10AX115S2F45E1SG" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
+ <parameter name="EXT_DRIVER_PARAM" value="false" />
+ <parameter name="GENERATE_SDC_FILE" value="false" />
+ <parameter name="IP_MIGRATE_PORT_MAP_FILE">altddio_out_port_map.csv</parameter>
+ <parameter name="PIN_TYPE_GUI" value="Output" />
+ <parameter name="SIZE" value="1" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_areset_mode" value="Clear" />
+ <parameter name="gui_bus_hold" value="false" />
+ <parameter name="gui_diff_buff" value="false" />
+ <parameter name="gui_enable_cke" value="false" />
+ <parameter name="gui_enable_migratable_port_names" value="true" />
+ <parameter name="gui_enable_termination_ports" value="false" />
+ <parameter name="gui_hr_logic" value="false" />
+ <parameter name="gui_io_reg_mode" value="DDIO" />
+ <parameter name="gui_open_drain" value="false" />
+ <parameter name="gui_pseudo_diff" value="false" />
+ <parameter name="gui_separate_io_clks" value="false" />
+ <parameter name="gui_sreset_mode" value="None" />
+ <parameter name="gui_use_oe" value="false" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_in_1.vhd b/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_in_1.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..db5475eea9189e1a1751d9d7036042244b6aeec5
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_in_1.vhd
@@ -0,0 +1,65 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Simulation model for DDIO in
+-- Description:
+-- The double data rate datain samples that arrive at time series t0, t1, t2,
+-- ... get output with samples t0, t2, ... in dataout_l and samples t1, t3,
+-- ... in dataout_h. Hence dataout = dataout_h & dataout_l contains the
+-- time series samples in little endian format with the first sample in the
+-- LSpart as shown in the timing diagram:
+-- _ _ _ _
+-- inclock | |_| |_| |_| |_
+-- datain 0 1 2 3 4 5 6 7
+-- in_dat_r 1 3 5
+-- in_dat_f 0 2 4
+-- dataout_h 1 3 5
+-- dataout_l 0 2 4
+--
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY ip_arria10_e1sg_ddio_in_1 IS
+ PORT (
+ datain : IN STD_LOGIC_VECTOR(0 downto 0) := (others => '0');
+ inclock : IN STD_LOGIC := '0';
+ aclr : IN STD_LOGIC := '0';
+ dataout_h : OUT STD_LOGIC_VECTOR(0 downto 0);
+ dataout_l : OUT STD_LOGIC_VECTOR(0 downto 0)
+ );
+END ip_arria10_e1sg_ddio_in_1;
+
+
+ARCHITECTURE beh OF ip_arria10_e1sg_ddio_in_1 IS
+
+ SIGNAL in_dat_r : STD_LOGIC;
+ SIGNAL in_dat_f : STD_LOGIC;
+
+BEGIN
+
+ in_dat_r <= datain(0) WHEN rising_edge(inclock);
+ in_dat_f <= datain(0) WHEN falling_edge(inclock);
+
+ dataout_h <= (OTHERS=>in_dat_r);
+ dataout_l <= (OTHERS=>in_dat_f) WHEN rising_edge(inclock);
+
+END beh;
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_out_1.vhd b/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_out_1.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e0e7c97ad1192b26828f89c52c29f1a9ed91669e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_out_1.vhd
@@ -0,0 +1,59 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Simulation model for DDIO out
+-- Description:
+-- This function is the inverse of DDIO in as described in ip_arria10_e1sg_ddio_in_1.
+-- The timing diagram:
+-- _ _ _ _ _
+-- outclock | |_| |_| |_| |_| |_
+-- datain_h 1 3 5
+-- datain_l 0 2 4
+-- dataout @ r 1 3 5
+-- dataout @ f 0 2 4
+-- dataout 0 1 2 3 4 5 6 7
+--
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY ip_arria10_e1sg_ddio_out_1 IS
+ PORT (
+ dataout : OUT STD_LOGIC_VECTOR(0 downto 0);
+ outclock : IN STD_LOGIC := '0';
+ aclr : IN STD_LOGIC := '0';
+ datain_h : IN STD_LOGIC_VECTOR(0 downto 0) := (others=>'0');
+ datain_l : IN STD_LOGIC_VECTOR(0 downto 0) := (others=>'0')
+ );
+END ip_arria10_e1sg_ddio_out_1;
+
+
+ARCHITECTURE beh OF ip_arria10_e1sg_ddio_out_1 IS
+
+ SIGNAL out_dat_r : STD_LOGIC;
+ SIGNAL out_dat_f : STD_LOGIC;
+
+BEGIN
+
+ dataout <= datain_l WHEN falling_edge(outclock) ELSE
+ datain_h WHEN rising_edge(outclock);
+
+END beh;
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd b/libraries/technology/ip_arria10_e1sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7e05f92baf2a96aabad5f5cd0e9f279b72b01352
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd
@@ -0,0 +1,126 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Test bench for the DDIO in and out simulation models
+-- Description:
+-- _ _ _ _
+-- inclock | |_| |_| |_| |_
+-- datain 0 1 2 3 4 5 6 7
+-- data_h 1 3 5
+-- data_l 0 2 4
+-- dataout 0 1 2 3 4 5 6 7
+--
+-- Usage:
+-- The tb is self checking (p_verify) and self stopping (tb_end)
+--
+-- . Load the simulation by right mouse selecting the entity in library work
+-- > as 3
+-- > run -a
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY tb_ip_arria10_e1sg_ddio_1 IS
+END tb_ip_arria10_e1sg_ddio_1;
+
+
+ARCHITECTURE tb OF tb_ip_arria10_e1sg_ddio_1 IS
+
+ CONSTANT c_clk_period : TIME := 10 ns;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL clk : STD_LOGIC := '1';
+ SIGNAL in_dat : STD_LOGIC;
+ SIGNAL in_data : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL data_h : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL data_l : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL out_data : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL out_dat : STD_LOGIC;
+ SIGNAL out_dat_exp : STD_LOGIC;
+
+BEGIN
+
+ tb_end <= '0', '1' AFTER 100*c_clk_period;
+
+ clk <= NOT clk OR tb_end AFTER c_clk_period/2;
+
+ p_in : PROCESS
+ BEGIN
+ -- 0
+ in_dat <= '0';
+ WAIT UNTIL falling_edge(clk);
+ in_dat <= '0';
+ WAIT UNTIL rising_edge(clk);
+ -- 1
+ in_dat <= '0';
+ WAIT UNTIL falling_edge(clk);
+ in_dat <= '1';
+ WAIT UNTIL rising_edge(clk);
+ -- 2
+ in_dat <= '1';
+ WAIT UNTIL falling_edge(clk);
+ in_dat <= '0';
+ WAIT UNTIL rising_edge(clk);
+ -- 3
+ in_dat <= '1';
+ WAIT UNTIL falling_edge(clk);
+ in_dat <= '1';
+ WAIT UNTIL rising_edge(clk);
+ -- 2
+ in_dat <= '1';
+ WAIT UNTIL falling_edge(clk);
+ in_dat <= '0';
+ WAIT UNTIL rising_edge(clk);
+ END PROCESS;
+
+ in_data(0) <= in_dat;
+
+ u_ddio_in : ENTITY work.ip_arria10_e1sg_ddio_in_1
+ PORT MAP (
+ datain => in_data,
+ inclock => clk,
+ dataout_h => data_h,
+ dataout_l => data_l
+ );
+
+ u_ddio_out : ENTITY work.ip_arria10_e1sg_ddio_out_1
+ PORT MAP (
+ dataout => out_data,
+ outclock => clk,
+ datain_h => data_h,
+ datain_l => data_l
+ );
+
+ out_dat <= out_data(0);
+
+ out_dat_exp <= TRANSPORT in_dat AFTER c_clk_period*1.5 + 1 ps;
+
+ p_verify : PROCESS(clk)
+ BEGIN
+ IF falling_edge(clk) THEN
+ ASSERT out_dat=out_dat_exp REPORT "tb_ip_arria10_e1sg_ddio_1: Error, unexpeced data at falling edge";
+ END IF;
+ IF rising_edge(clk) THEN
+ ASSERT out_dat=out_dat_exp REPORT "tb_ip_arria10_e1sg_ddio_1: Error, unexpeced data at rising edge";
+ END IF;
+ END PROCESS;
+
+END tb;
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..aa562b8f4eb5306a4dafc81370d772c3081acf06
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
@@ -0,0 +1,33 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generated/sim"
+
+# Copy ROM/RAM files to simulation directory
+if {[file isdirectory $IP_DIR]} {
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_151_4thorvi_seq_cal_sim.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_151_4thorvi_seq_cal_synth.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_151_4thorvi_seq_params_sim.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_151_4thorvi_seq_params_synth.hex ./
+}
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..9d98e72bcecf2225560e012317310689f02c6eee
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/generate_ip.sh
@@ -0,0 +1,54 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_ddr4_4g_1600.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
+
+# Also generate the testbench IP, this is not useful because it only generates bus functional models, so not a DDR4 memory model
+#qsys-generate ip_arria10_e1sg_ddr4_4g_1600.qsys \
+# --synthesis=VHDL \
+# --simulation=VHDL \
+# --testbench=STANDARD \
+# --testbench-simulation=VHDL \
+# --output-directory=generated \
+# --allow-mixed-language-simulation \
+# --allow-mixed-language-testbench-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..38704a1a7ae68ed96aaadf769d6a154242a3b1e7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_ddr4_4g_1600
+hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_1600_altera_emif_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_ddr4_4g_1600.qip
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qsys b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..30bb270aa5ad679d4c0a43556260980c1abbabc6
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qsys
@@ -0,0 +1,1170 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_ddr4_4g_1600">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element emif_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>ctrl_amm_0</key>
+ <value>
+ <connectionPointName>ctrl_amm_0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='ctrl_amm_0' start='0x0' end='0x120000000' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>33</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>576</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>emif_usr_clk</key>
+ <value>
+ <connectionPointName>emif_usr_clk</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>200000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="ctrl_amm_0"
+ internal="emif_0.ctrl_amm_0"
+ type="avalon"
+ dir="end">
+ <port name="amm_address_0" internal="amm_address_0" />
+ <port name="amm_burstcount_0" internal="amm_burstcount_0" />
+ <port name="amm_byteenable_0" internal="amm_byteenable_0" />
+ <port name="amm_read_0" internal="amm_read_0" />
+ <port name="amm_readdata_0" internal="amm_readdata_0" />
+ <port name="amm_readdatavalid_0" internal="amm_readdatavalid_0" />
+ <port name="amm_ready_0" internal="amm_ready_0" />
+ <port name="amm_write_0" internal="amm_write_0" />
+ <port name="amm_writedata_0" internal="amm_writedata_0" />
+ </interface>
+ <interface name="ctrl_mmr_slave_0" internal="emif_0.ctrl_mmr_slave_0" />
+ <interface
+ name="emif_usr_clk"
+ internal="emif_0.emif_usr_clk"
+ type="clock"
+ dir="start">
+ <port name="emif_usr_clk" internal="emif_usr_clk" />
+ </interface>
+ <interface
+ name="emif_usr_reset_n"
+ internal="emif_0.emif_usr_reset_n"
+ type="reset"
+ dir="start">
+ <port name="emif_usr_reset_n" internal="emif_usr_reset_n" />
+ </interface>
+ <interface
+ name="global_reset_n"
+ internal="emif_0.global_reset_n"
+ type="reset"
+ dir="end">
+ <port name="global_reset_n" internal="global_reset_n" />
+ </interface>
+ <interface name="mem" internal="emif_0.mem" type="conduit" dir="end">
+ <port name="mem_a" internal="mem_a" />
+ <port name="mem_act_n" internal="mem_act_n" />
+ <port name="mem_alert_n" internal="mem_alert_n" />
+ <port name="mem_ba" internal="mem_ba" />
+ <port name="mem_bg" internal="mem_bg" />
+ <port name="mem_ck" internal="mem_ck" />
+ <port name="mem_ck_n" internal="mem_ck_n" />
+ <port name="mem_cke" internal="mem_cke" />
+ <port name="mem_cs_n" internal="mem_cs_n" />
+ <port name="mem_dbi_n" internal="mem_dbi_n" />
+ <port name="mem_dq" internal="mem_dq" />
+ <port name="mem_dqs" internal="mem_dqs" />
+ <port name="mem_dqs_n" internal="mem_dqs_n" />
+ <port name="mem_odt" internal="mem_odt" />
+ <port name="mem_par" internal="mem_par" />
+ <port name="mem_reset_n" internal="mem_reset_n" />
+ </interface>
+ <interface name="oct" internal="emif_0.oct" type="conduit" dir="end">
+ <port name="oct_rzqin" internal="oct_rzqin" />
+ </interface>
+ <interface
+ name="pll_ref_clk"
+ internal="emif_0.pll_ref_clk"
+ type="clock"
+ dir="end">
+ <port name="pll_ref_clk" internal="pll_ref_clk" />
+ </interface>
+ <interface name="status" internal="emif_0.status" type="conduit" dir="end">
+ <port name="local_cal_fail" internal="local_cal_fail" />
+ <port name="local_cal_success" internal="local_cal_success" />
+ </interface>
+ <module
+ name="emif_0"
+ kind="altera_emif"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR3_MAX_DQS_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_DDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR3_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR3_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_RCLK_SLEW_RATE" value="5.0" />
+ <parameter name="BOARD_DDR3_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_RDATA_SLEW_RATE" value="2.5" />
+ <parameter name="BOARD_DDR3_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR3_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_DDR3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="0.013" />
+ <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.146" />
+ <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.03" />
+ <parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="-0.21" />
+ <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.252" />
+ <parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.323" />
+ <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.072" />
+ <parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.133" />
+ <parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="1.16" />
+ <parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="2.43" />
+ <parameter name="BOARD_DDR4_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="3.7" />
+ <parameter name="BOARD_DDR4_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="2.2" />
+ <parameter name="BOARD_DDR4_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_WCLK_SLEW_RATE" value="3.7" />
+ <parameter name="BOARD_DDR4_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.16" />
+ <parameter name="BOARD_DDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_DDR4_USE_DEFAULT_SLEW_RATES" value="false" />
+ <parameter name="BOARD_LPDDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+ <parameter name="BOARD_LPDDR3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_LPDDR3_MAX_DQS_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_LPDDR3_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_LPDDR3_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_LPDDR3_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_RDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_LPDDR3_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_LPDDR3_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_QDR2_AC_TO_K_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR2_MAX_K_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_K_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR2_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR2_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_RDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_QDR2_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_QDR4_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_DK_TO_CK_SKEW_NS" value="-0.02" />
+ <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR4_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR4_MAX_DK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_QDR4_SKEW_BETWEEN_DK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR4_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_RCLK_SLEW_RATE" value="5.0" />
+ <parameter name="BOARD_QDR4_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_RDATA_SLEW_RATE" value="2.5" />
+ <parameter name="BOARD_QDR4_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_QDR4_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_RLD3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_DK_TO_CK_SKEW_NS" value="-0.02" />
+ <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+ <parameter name="BOARD_RLD3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_RLD3_MAX_DK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_RLD3_SKEW_BETWEEN_DK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_RLD3_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_RCLK_SLEW_RATE" value="7.0" />
+ <parameter name="BOARD_RLD3_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_RDATA_SLEW_RATE" value="3.5" />
+ <parameter name="BOARD_RLD3_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="CAL_DEBUG_CLOCK_FREQUENCY" value="50000000" />
+ <parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_DDR3_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_DDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_DDR3_ECC_AUTO_CORRECTION_EN" value="false" />
+ <parameter name="CTRL_DDR3_ECC_EN" value="false" />
+ <parameter name="CTRL_DDR3_MMR_EN" value="false" />
+ <parameter name="CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_REORDER_EN" value="true" />
+ <parameter name="CTRL_DDR3_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR3_STARVE_LIMIT" value="10" />
+ <parameter name="CTRL_DDR3_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_DDR3_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_ADDR_ORDER_ENUM">DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG</parameter>
+ <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_DDR4_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_DDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_DDR4_ECC_AUTO_CORRECTION_EN" value="false" />
+ <parameter name="CTRL_DDR4_ECC_EN" value="false" />
+ <parameter name="CTRL_DDR4_MMR_EN" value="false" />
+ <parameter name="CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_REORDER_EN" value="true" />
+ <parameter name="CTRL_DDR4_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR4_STARVE_LIMIT" value="10" />
+ <parameter name="CTRL_DDR4_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_DDR4_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_ADDR_ORDER_ENUM">LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_LPDDR3_MMR_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_REORDER_EN" value="true" />
+ <parameter name="CTRL_LPDDR3_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_STARVE_LIMIT" value="10" />
+ <parameter name="CTRL_LPDDR3_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+ <parameter name="CTRL_QDR2_AVL_MAX_BURST_COUNT" value="4" />
+ <parameter name="CTRL_QDR2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC" value="0" />
+ <parameter name="CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC" value="0" />
+ <parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+ <parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
+ <parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
+ <parameter name="DIAG_DDR3_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_DDR3_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_DDR3_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_DDR3_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_DDR3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_DDR3_CAL_ADDR0" value="0" />
+ <parameter name="DIAG_DDR3_CAL_ADDR1" value="8" />
+ <parameter name="DIAG_DDR3_CAL_ENABLE_NON_DES" value="false" />
+ <parameter name="DIAG_DDR3_CAL_FULL_CAL_ON_RESET" value="true" />
+ <parameter name="DIAG_DDR3_CA_LEVEL_EN" value="false" />
+ <parameter name="DIAG_DDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR3_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_DDR3_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR3_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR3_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_DDR4_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_DDR4_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_DDR4_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_DDR4_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_DDR4_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_DDR4_CAL_ADDR0" value="0" />
+ <parameter name="DIAG_DDR4_CAL_ADDR1" value="8" />
+ <parameter name="DIAG_DDR4_CAL_ENABLE_NON_DES" value="false" />
+ <parameter name="DIAG_DDR4_CAL_FULL_CAL_ON_RESET" value="true" />
+ <parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR4_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_DDR4_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
+ <parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="false" />
+ <parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="true" />
+ <parameter name="DIAG_DDR4_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR4_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR4_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
+ <parameter name="DIAG_ENABLE_HPS_EMIF_DEBUG" value="false" />
+ <parameter name="DIAG_ENABLE_JTAG_UART" value="false" />
+ <parameter name="DIAG_ENABLE_JTAG_UART_HEX" value="false" />
+ <parameter name="DIAG_EXPORT_VJI" value="false" />
+ <parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
+ <parameter name="DIAG_EXTRA_CONFIGS" value="" />
+ <parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
+ <parameter name="DIAG_EX_DESIGN_SEPARATE_RESETS" value="false" />
+ <parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
+ <parameter name="DIAG_LPDDR3_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_LPDDR3_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_LPDDR3_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_LPDDR3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_LPDDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_LPDDR3_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_LPDDR3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_LPDDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_LPDDR3_SKIP_CA_DESKEW" value="false" />
+ <parameter name="DIAG_LPDDR3_SKIP_CA_LEVEL" value="false" />
+ <parameter name="DIAG_LPDDR3_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_LPDDR3_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_LPDDR3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_QDR2_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_QDR2_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_QDR2_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_QDR2_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_QDR2_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_QDR2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR2_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_QDR2_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR2_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR2_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR2_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_QDR4_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_QDR4_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_QDR4_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_QDR4_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_QDR4_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_QDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR4_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_QDR4_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR4_SKIP_VREF_CAL" value="false" />
+ <parameter name="DIAG_QDR4_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR4_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR4_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RLD2_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_RLD2_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_RLD2_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_RLD2_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_RLD2_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_RLD2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD2_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_RLD2_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD2_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD2_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD2_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RLD3_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_RLD3_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_RLD3_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_RLD3_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_RLD3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_RLD3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD3_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_RLD3_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD3_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD3_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RS232_UART_BAUDRATE" value="57600" />
+ <parameter name="DIAG_SIM_REGTEST_MODE" value="false" />
+ <parameter name="DIAG_SOFT_NIOS_CLOCK_FREQUENCY" value="100" />
+ <parameter name="DIAG_SOFT_NIOS_MODE">SOFT_NIOS_MODE_DISABLED</parameter>
+ <parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
+ <parameter name="DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE" value="false" />
+ <parameter name="DIAG_TG_AVL_2_NUM_CFG_INTERFACES" value="0" />
+ <parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
+ <parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
+ <parameter name="DIAG_USE_RS232_UART" value="false" />
+ <parameter name="DIAG_VERBOSE_IOAUX" value="false" />
+ <parameter name="EX_DESIGN_GUI_DDR3_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR3_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_DDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_DDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_DDR4_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR4_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_DDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_DDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter
+ name="EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT"
+ value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR2_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR2_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_QDR2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR4_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR4_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_QDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD2_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD2_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_RLD2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD3_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD3_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_RLD3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="INTERNAL_TESTING_MODE" value="false" />
+ <parameter name="IS_ED_SLAVE" value="false" />
+ <parameter name="MEM_DDR3_ALERT_N_DQS_GROUP" value="0" />
+ <parameter name="MEM_DDR3_ALERT_N_PLACEMENT_ENUM">DDR3_ALERT_N_PLACEMENT_AC_LANES</parameter>
+ <parameter name="MEM_DDR3_ASR_ENUM" value="DDR3_ASR_MANUAL" />
+ <parameter name="MEM_DDR3_ATCL_ENUM" value="DDR3_ATCL_DISABLED" />
+ <parameter name="MEM_DDR3_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_DDR3_BL_ENUM" value="DDR3_BL_BL8" />
+ <parameter name="MEM_DDR3_BT_ENUM" value="DDR3_BT_SEQUENTIAL" />
+ <parameter name="MEM_DDR3_CKE_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR3_CK_WIDTH" value="1" />
+ <parameter name="MEM_DDR3_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_DDR3_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR3_DLL_EN" value="true" />
+ <parameter name="MEM_DDR3_DM_EN" value="true" />
+ <parameter name="MEM_DDR3_DQ_PER_DQS" value="8" />
+ <parameter name="MEM_DDR3_DQ_WIDTH" value="72" />
+ <parameter name="MEM_DDR3_DRV_STR_ENUM" value="DDR3_DRV_STR_RZQ_7" />
+ <parameter name="MEM_DDR3_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
+ <parameter name="MEM_DDR3_HIDE_ADV_MR_SETTINGS" value="true" />
+ <parameter name="MEM_DDR3_LRDIMM_EXTENDED_CONFIG" value="000000000000000000" />
+ <parameter name="MEM_DDR3_MIRROR_ADDRESSING_EN" value="true" />
+ <parameter name="MEM_DDR3_NUM_OF_DIMMS" value="1" />
+ <parameter name="MEM_DDR3_PD_ENUM" value="DDR3_PD_OFF" />
+ <parameter name="MEM_DDR3_RANKS_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR3_RDIMM_CONFIG" value="0000000000000000" />
+ <parameter name="MEM_DDR3_ROW_ADDR_WIDTH" value="15" />
+ <parameter name="MEM_DDR3_RTT_NOM_ENUM">DDR3_RTT_NOM_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR3_RTT_WR_ENUM" value="DDR3_RTT_WR_RZQ_4" />
+ <parameter name="MEM_DDR3_R_ODT0_1X1" value="off" />
+ <parameter name="MEM_DDR3_R_ODT0_2X2" value="off,off" />
+ <parameter name="MEM_DDR3_R_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_R_ODT0_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR3_R_ODT1_2X2" value="off,off" />
+ <parameter name="MEM_DDR3_R_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_R_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_R_ODT2_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR3_R_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR3_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_SPEEDBIN_ENUM" value="DDR3_SPEEDBIN_2133" />
+ <parameter name="MEM_DDR3_SRT_ENUM" value="DDR3_SRT_NORMAL" />
+ <parameter name="MEM_DDR3_TCL" value="14" />
+ <parameter name="MEM_DDR3_TDH_DC_MV" value="100" />
+ <parameter name="MEM_DDR3_TDH_PS" value="55" />
+ <parameter name="MEM_DDR3_TDQSCK_PS" value="180" />
+ <parameter name="MEM_DDR3_TDQSQ_PS" value="75" />
+ <parameter name="MEM_DDR3_TDQSS_CYC" value="0.27" />
+ <parameter name="MEM_DDR3_TDSH_CYC" value="0.18" />
+ <parameter name="MEM_DDR3_TDSS_CYC" value="0.18" />
+ <parameter name="MEM_DDR3_TDS_AC_MV" value="135" />
+ <parameter name="MEM_DDR3_TDS_PS" value="53" />
+ <parameter name="MEM_DDR3_TFAW_NS" value="25.0" />
+ <parameter name="MEM_DDR3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_DDR3_TIH_PS" value="95" />
+ <parameter name="MEM_DDR3_TINIT_US" value="500" />
+ <parameter name="MEM_DDR3_TIS_AC_MV" value="135" />
+ <parameter name="MEM_DDR3_TIS_PS" value="60" />
+ <parameter name="MEM_DDR3_TMRD_CK_CYC" value="4" />
+ <parameter name="MEM_DDR3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_DDR3_TQSH_CYC" value="0.4" />
+ <parameter name="MEM_DDR3_TRAS_NS" value="33.0" />
+ <parameter name="MEM_DDR3_TRCD_NS" value="13.09" />
+ <parameter name="MEM_DDR3_TREFI_US" value="7.8" />
+ <parameter name="MEM_DDR3_TRFC_NS" value="160.0" />
+ <parameter name="MEM_DDR3_TRP_NS" value="13.09" />
+ <parameter name="MEM_DDR3_TRRD_CYC" value="6" />
+ <parameter name="MEM_DDR3_TRTP_CYC" value="8" />
+ <parameter name="MEM_DDR3_TWLH_PS" value="125.0" />
+ <parameter name="MEM_DDR3_TWLS_PS" value="125.0" />
+ <parameter name="MEM_DDR3_TWR_NS" value="15.0" />
+ <parameter name="MEM_DDR3_TWTR_CYC" value="8" />
+ <parameter name="MEM_DDR3_USE_DEFAULT_ODT" value="true" />
+ <parameter name="MEM_DDR3_WTCL" value="10" />
+ <parameter name="MEM_DDR3_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR3_W_ODT0_2X2" value="on,off" />
+ <parameter name="MEM_DDR3_W_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT0_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODT1_2X2" value="off,on" />
+ <parameter name="MEM_DDR3_W_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT2_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR3_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_AC_PARITY_LATENCY">DDR4_AC_PARITY_LATENCY_DISABLE</parameter>
+ <parameter name="MEM_DDR4_AC_PERSISTENT_ERROR" value="false" />
+ <parameter name="MEM_DDR4_ALERT_N_AC_LANE" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_AC_PIN" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_DQS_GROUP" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_PLACEMENT_ENUM">DDR4_ALERT_N_PLACEMENT_DATA_LANES</parameter>
+ <parameter name="MEM_DDR4_ALERT_PAR_EN" value="true" />
+ <parameter name="MEM_DDR4_ASR_ENUM">DDR4_ASR_MANUAL_NORMAL</parameter>
+ <parameter name="MEM_DDR4_ATCL_ENUM" value="DDR4_ATCL_DISABLED" />
+ <parameter name="MEM_DDR4_BANK_ADDR_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_BANK_GROUP_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_BL_ENUM" value="DDR4_BL_BL8" />
+ <parameter name="MEM_DDR4_BT_ENUM" value="DDR4_BT_SEQUENTIAL" />
+ <parameter name="MEM_DDR4_CAL_MODE" value="0" />
+ <parameter name="MEM_DDR4_CHIP_ID_WIDTH" value="0" />
+ <parameter name="MEM_DDR4_CKE_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR4_CK_WIDTH" value="1" />
+ <parameter name="MEM_DDR4_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_DDR4_DB_DQ_DRV_ENUM">DDR4_DB_DRV_STR_RZQ_7</parameter>
+ <parameter name="MEM_DDR4_DB_RTT_NOM_ENUM">DDR4_DB_RTT_NOM_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_DB_RTT_PARK_ENUM">DDR4_DB_RTT_PARK_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_DB_RTT_WR_ENUM">DDR4_DB_RTT_WR_RZQ_3</parameter>
+ <parameter name="MEM_DDR4_DEFAULT_VREFOUT" value="false" />
+ <parameter name="MEM_DDR4_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR4_DLL_EN" value="true" />
+ <parameter name="MEM_DDR4_DM_EN" value="true" />
+ <parameter name="MEM_DDR4_DQ_PER_DQS" value="8" />
+ <parameter name="MEM_DDR4_DQ_WIDTH" value="72" />
+ <parameter name="MEM_DDR4_DRV_STR_ENUM" value="DDR4_DRV_STR_RZQ_7" />
+ <parameter name="MEM_DDR4_FINE_GRANULARITY_REFRESH">DDR4_FINE_REFRESH_FIXED_1X</parameter>
+ <parameter name="MEM_DDR4_FORMAT_ENUM" value="MEM_FORMAT_SODIMM" />
+ <parameter name="MEM_DDR4_GEARDOWN" value="DDR4_GEARDOWN_HR" />
+ <parameter name="MEM_DDR4_HIDE_ADV_MR_SETTINGS" value="true" />
+ <parameter name="MEM_DDR4_INTERNAL_VREFDQ_MONITOR" value="true" />
+ <parameter name="MEM_DDR4_LRDIMM_ODT_LESS_BS" value="true" />
+ <parameter name="MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM" value="240" />
+ <parameter name="MEM_DDR4_LRDIMM_VREFDQ_VALUE" value="1D" />
+ <parameter name="MEM_DDR4_MAX_POWERDOWN" value="false" />
+ <parameter name="MEM_DDR4_MIRROR_ADDRESSING_EN" value="true" />
+ <parameter name="MEM_DDR4_MPR_READ_FORMAT">DDR4_MPR_READ_FORMAT_SERIAL</parameter>
+ <parameter name="MEM_DDR4_NUM_OF_DIMMS" value="1" />
+ <parameter name="MEM_DDR4_ODT_IN_POWERDOWN" value="true" />
+ <parameter name="MEM_DDR4_PER_DRAM_ADDR" value="false" />
+ <parameter name="MEM_DDR4_RANKS_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR4_RCD_CA_IBT_ENUM" value="DDR4_RCD_CA_IBT_100" />
+ <parameter name="MEM_DDR4_RCD_CKE_IBT_ENUM">DDR4_RCD_CKE_IBT_100</parameter>
+ <parameter name="MEM_DDR4_RCD_CS_IBT_ENUM" value="DDR4_RCD_CS_IBT_100" />
+ <parameter name="MEM_DDR4_RCD_ODT_IBT_ENUM">DDR4_RCD_ODT_IBT_100</parameter>
+ <parameter name="MEM_DDR4_READ_DBI" value="false" />
+ <parameter name="MEM_DDR4_READ_PREAMBLE" value="2" />
+ <parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
+ <parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
+ <parameter name="MEM_DDR4_RTT_NOM_ENUM" value="DDR4_RTT_NOM_RZQ_4" />
+ <parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_RTT_WR_ENUM">DDR4_RTT_WR_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_R_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR4_R_ODT0_2X2" value="off,off" />
+ <parameter name="MEM_DDR4_R_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_R_ODT0_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR4_R_ODT1_2X2" value="off,off" />
+ <parameter name="MEM_DDR4_R_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_R_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_R_ODT2_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR4_R_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR4_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR4_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_SELF_RFSH_ABORT" value="false" />
+ <parameter name="MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB" value="0" />
+ <parameter name="MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB" value="0" />
+ <parameter name="MEM_DDR4_SPD_135_RCD_REV" value="0" />
+ <parameter name="MEM_DDR4_SPD_137_RCD_CA_DRV" value="101" />
+ <parameter name="MEM_DDR4_SPD_138_RCD_CK_DRV" value="5" />
+ <parameter name="MEM_DDR4_SPD_139_DB_REV" value="0" />
+ <parameter name="MEM_DDR4_SPD_140_DRAM_VREFDQ_R0" value="29" />
+ <parameter name="MEM_DDR4_SPD_141_DRAM_VREFDQ_R1" value="29" />
+ <parameter name="MEM_DDR4_SPD_142_DRAM_VREFDQ_R2" value="29" />
+ <parameter name="MEM_DDR4_SPD_143_DRAM_VREFDQ_R3" value="29" />
+ <parameter name="MEM_DDR4_SPD_144_DB_VREFDQ" value="37" />
+ <parameter name="MEM_DDR4_SPD_145_DB_MDQ_DRV" value="21" />
+ <parameter name="MEM_DDR4_SPD_148_DRAM_DRV" value="0" />
+ <parameter name="MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM" value="20" />
+ <parameter name="MEM_DDR4_SPD_152_DRAM_RTT_PARK" value="39" />
+ <parameter name="MEM_DDR4_SPEEDBIN_ENUM" value="DDR4_SPEEDBIN_2133" />
+ <parameter name="MEM_DDR4_TCCD_L_CYC" value="5" />
+ <parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
+ <parameter name="MEM_DDR4_TCL" value="11" />
+ <parameter name="MEM_DDR4_TDIVW_DJ_CYC" value="0.1" />
+ <parameter name="MEM_DDR4_TDIVW_TOTAL_UI" value="0.2" />
+ <parameter name="MEM_DDR4_TDQSCK_PS" value="170" />
+ <parameter name="MEM_DDR4_TDQSQ_PS" value="66" />
+ <parameter name="MEM_DDR4_TDQSQ_UI" value="0.16" />
+ <parameter name="MEM_DDR4_TDQSS_CYC" value="0.27" />
+ <parameter name="MEM_DDR4_TDSH_CYC" value="0.18" />
+ <parameter name="MEM_DDR4_TDSS_CYC" value="0.18" />
+ <parameter name="MEM_DDR4_TDVWP_UI" value="0.72" />
+ <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA" value="false" />
+ <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
+ <parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
+ <parameter name="MEM_DDR4_TFAW_NS" value="21.0" />
+ <parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
+ <parameter name="MEM_DDR4_TIH_PS" value="105" />
+ <parameter name="MEM_DDR4_TINIT_US" value="500" />
+ <parameter name="MEM_DDR4_TIS_AC_MV" value="100" />
+ <parameter name="MEM_DDR4_TIS_PS" value="80" />
+ <parameter name="MEM_DDR4_TMRD_CK_CYC" value="8" />
+ <parameter name="MEM_DDR4_TQH_CYC" value="0.38" />
+ <parameter name="MEM_DDR4_TQH_UI" value="0.76" />
+ <parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
+ <parameter name="MEM_DDR4_TRAS_NS" value="33.0" />
+ <parameter name="MEM_DDR4_TRCD_NS" value="14.06" />
+ <parameter name="MEM_DDR4_TREFI_US" value="7.8" />
+ <parameter name="MEM_DDR4_TRFC_NS" value="260.0" />
+ <parameter name="MEM_DDR4_TRP_NS" value="14.06" />
+ <parameter name="MEM_DDR4_TRRD_L_CYC" value="5" />
+ <parameter name="MEM_DDR4_TRRD_S_CYC" value="3" />
+ <parameter name="MEM_DDR4_TWLH_PS" value="162.5" />
+ <parameter name="MEM_DDR4_TWLS_PS" value="162.5" />
+ <parameter name="MEM_DDR4_TWR_NS" value="15.0" />
+ <parameter name="MEM_DDR4_TWTR_L_CYC" value="6" />
+ <parameter name="MEM_DDR4_TWTR_S_CYC" value="2" />
+ <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_1</parameter>
+ <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_VALUE" value="68.0" />
+ <parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="false" />
+ <parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
+ <parameter name="MEM_DDR4_WRITE_CRC" value="false" />
+ <parameter name="MEM_DDR4_WRITE_DBI" value="false" />
+ <parameter name="MEM_DDR4_WRITE_PREAMBLE" value="1" />
+ <parameter name="MEM_DDR4_WTCL" value="9" />
+ <parameter name="MEM_DDR4_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR4_W_ODT0_2X2" value="on,off" />
+ <parameter name="MEM_DDR4_W_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT0_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODT1_2X2" value="off,on" />
+ <parameter name="MEM_DDR4_W_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT2_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR4_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR4_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_LPDDR3_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_LPDDR3_BL" value="LPDDR3_BL_BL8" />
+ <parameter name="MEM_LPDDR3_CK_WIDTH" value="1" />
+ <parameter name="MEM_LPDDR3_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_LPDDR3_DATA_LATENCY" value="LPDDR3_DL_RL12_WL6" />
+ <parameter name="MEM_LPDDR3_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_LPDDR3_DM_EN" value="true" />
+ <parameter name="MEM_LPDDR3_DQODT">LPDDR3_DQODT_DISABLE</parameter>
+ <parameter name="MEM_LPDDR3_DQ_WIDTH" value="32" />
+ <parameter name="MEM_LPDDR3_DRV_STR">LPDDR3_DRV_STR_40D_40U</parameter>
+ <parameter name="MEM_LPDDR3_NWR" value="LPDDR3_NWR_NWR10" />
+ <parameter name="MEM_LPDDR3_PDODT">LPDDR3_PDODT_DISABLED</parameter>
+ <parameter name="MEM_LPDDR3_ROW_ADDR_WIDTH" value="15" />
+ <parameter name="MEM_LPDDR3_R_ODT0_1X1" value="off" />
+ <parameter name="MEM_LPDDR3_R_ODT0_2X2" value="off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT0_4X4" value="off,off,on,on" />
+ <parameter name="MEM_LPDDR3_R_ODT1_2X2" value="off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT1_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT2_4X4" value="on,on,off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT3_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_LPDDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_LPDDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_LPDDR3_SPEEDBIN_ENUM">LPDDR3_SPEEDBIN_1600</parameter>
+ <parameter name="MEM_LPDDR3_TDH_DC_MV" value="100" />
+ <parameter name="MEM_LPDDR3_TDH_PS" value="100" />
+ <parameter name="MEM_LPDDR3_TDQSCKDL" value="614" />
+ <parameter name="MEM_LPDDR3_TDQSQ_PS" value="135" />
+ <parameter name="MEM_LPDDR3_TDQSS_CYC" value="1.25" />
+ <parameter name="MEM_LPDDR3_TDSH_CYC" value="0.2" />
+ <parameter name="MEM_LPDDR3_TDSS_CYC" value="0.2" />
+ <parameter name="MEM_LPDDR3_TDS_AC_MV" value="150" />
+ <parameter name="MEM_LPDDR3_TDS_PS" value="75" />
+ <parameter name="MEM_LPDDR3_TFAW_NS" value="50.0" />
+ <parameter name="MEM_LPDDR3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_LPDDR3_TIH_PS" value="100" />
+ <parameter name="MEM_LPDDR3_TINIT_US" value="500" />
+ <parameter name="MEM_LPDDR3_TIS_AC_MV" value="150" />
+ <parameter name="MEM_LPDDR3_TIS_PS" value="75" />
+ <parameter name="MEM_LPDDR3_TMRR_CK_CYC" value="4" />
+ <parameter name="MEM_LPDDR3_TMRW_CK_CYC" value="10" />
+ <parameter name="MEM_LPDDR3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_LPDDR3_TQSH_CYC" value="0.38" />
+ <parameter name="MEM_LPDDR3_TRAS_NS" value="42.5" />
+ <parameter name="MEM_LPDDR3_TRCD_NS" value="18.75" />
+ <parameter name="MEM_LPDDR3_TREFI_US" value="3.9" />
+ <parameter name="MEM_LPDDR3_TRFC_NS" value="210.0" />
+ <parameter name="MEM_LPDDR3_TRP_NS" value="18.75" />
+ <parameter name="MEM_LPDDR3_TRRD_CYC" value="2" />
+ <parameter name="MEM_LPDDR3_TRTP_CYC" value="4" />
+ <parameter name="MEM_LPDDR3_TWLH_PS" value="175.0" />
+ <parameter name="MEM_LPDDR3_TWLS_PS" value="175.0" />
+ <parameter name="MEM_LPDDR3_TWR_NS" value="15.0" />
+ <parameter name="MEM_LPDDR3_TWTR_CYC" value="4" />
+ <parameter name="MEM_LPDDR3_USE_DEFAULT_ODT" value="true" />
+ <parameter name="MEM_LPDDR3_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_LPDDR3_W_ODT0_2X2" value="on,off" />
+ <parameter name="MEM_LPDDR3_W_ODT0_4X4" value="on,on,on,on" />
+ <parameter name="MEM_LPDDR3_W_ODT1_2X2" value="off,on" />
+ <parameter name="MEM_LPDDR3_W_ODT1_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_W_ODT2_4X4" value="on,on,on,on" />
+ <parameter name="MEM_LPDDR3_W_ODT3_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_LPDDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_LPDDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_QDR2_ADDR_WIDTH" value="19" />
+ <parameter name="MEM_QDR2_BL" value="4" />
+ <parameter name="MEM_QDR2_BWS_EN" value="true" />
+ <parameter name="MEM_QDR2_DATA_PER_DEVICE" value="36" />
+ <parameter name="MEM_QDR2_INTERNAL_JITTER_NS" value="0.08" />
+ <parameter name="MEM_QDR2_SPEEDBIN_ENUM" value="QDR2_SPEEDBIN_633" />
+ <parameter name="MEM_QDR2_TCCQO_NS" value="0.45" />
+ <parameter name="MEM_QDR2_TCQDOH_NS" value="-0.09" />
+ <parameter name="MEM_QDR2_TCQD_NS" value="0.09" />
+ <parameter name="MEM_QDR2_TCQH_NS" value="0.71" />
+ <parameter name="MEM_QDR2_THA_NS" value="0.18" />
+ <parameter name="MEM_QDR2_THD_NS" value="0.18" />
+ <parameter name="MEM_QDR2_TRL_CYC" value="2.5" />
+ <parameter name="MEM_QDR2_TSA_NS" value="0.23" />
+ <parameter name="MEM_QDR2_TSD_NS" value="0.23" />
+ <parameter name="MEM_QDR2_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_QDR4_AC_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_ADDR_INV_ENA" value="false" />
+ <parameter name="MEM_QDR4_ADDR_WIDTH" value="21" />
+ <parameter name="MEM_QDR4_CK_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_DATA_INV_ENA" value="false" />
+ <parameter name="MEM_QDR4_DATA_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_DQ_PER_PORT_PER_DEVICE" value="36" />
+ <parameter name="MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+ <parameter name="MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+ <parameter name="MEM_QDR4_SPEEDBIN_ENUM" value="QDR4_SPEEDBIN_2133" />
+ <parameter name="MEM_QDR4_TASH_PS" value="170" />
+ <parameter name="MEM_QDR4_TCKDK_MAX_PS" value="150" />
+ <parameter name="MEM_QDR4_TCKDK_MIN_PS" value="-150" />
+ <parameter name="MEM_QDR4_TCKQK_MAX_PS" value="225" />
+ <parameter name="MEM_QDR4_TCSH_PS" value="170" />
+ <parameter name="MEM_QDR4_TISH_PS" value="150" />
+ <parameter name="MEM_QDR4_TQH_CYC" value="0.4" />
+ <parameter name="MEM_QDR4_TQKQ_MAX_PS" value="75" />
+ <parameter name="MEM_QDR4_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD2_ADDR_WIDTH" value="21" />
+ <parameter name="MEM_RLD2_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_RLD2_BL" value="4" />
+ <parameter name="MEM_RLD2_CONFIG_ENUM">RLD2_CONFIG_TRC_8_TRL_8_TWL_9</parameter>
+ <parameter name="MEM_RLD2_DM_EN" value="true" />
+ <parameter name="MEM_RLD2_DQ_PER_DEVICE" value="9" />
+ <parameter name="MEM_RLD2_DRIVE_IMPEDENCE_ENUM">RLD2_DRIVE_IMPEDENCE_INTERNAL_50</parameter>
+ <parameter name="MEM_RLD2_ODT_MODE_ENUM" value="RLD2_ODT_ON" />
+ <parameter name="MEM_RLD2_REFRESH_INTERVAL_US" value="0.24" />
+ <parameter name="MEM_RLD2_SPEEDBIN_ENUM" value="RLD2_SPEEDBIN_18" />
+ <parameter name="MEM_RLD2_TAH_NS" value="0.3" />
+ <parameter name="MEM_RLD2_TAS_NS" value="0.3" />
+ <parameter name="MEM_RLD2_TCKDK_MAX_NS" value="0.3" />
+ <parameter name="MEM_RLD2_TCKDK_MIN_NS" value="-0.3" />
+ <parameter name="MEM_RLD2_TCKH_CYC" value="0.45" />
+ <parameter name="MEM_RLD2_TCKQK_MAX_NS" value="0.2" />
+ <parameter name="MEM_RLD2_TDH_NS" value="0.17" />
+ <parameter name="MEM_RLD2_TDS_NS" value="0.17" />
+ <parameter name="MEM_RLD2_TQKH_HCYC" value="0.9" />
+ <parameter name="MEM_RLD2_TQKQ_MAX_NS" value="0.12" />
+ <parameter name="MEM_RLD2_TQKQ_MIN_NS" value="-0.12" />
+ <parameter name="MEM_RLD2_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_ADDR_WIDTH" value="20" />
+ <parameter name="MEM_RLD3_AREF_PROTOCOL_ENUM" value="RLD3_AREF_BAC" />
+ <parameter name="MEM_RLD3_BANK_ADDR_WIDTH" value="4" />
+ <parameter name="MEM_RLD3_BL" value="2" />
+ <parameter name="MEM_RLD3_DATA_LATENCY_MODE_ENUM" value="RLD3_DL_RL16_WL17" />
+ <parameter name="MEM_RLD3_DEPTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_DM_EN" value="true" />
+ <parameter name="MEM_RLD3_DQ_PER_DEVICE" value="36" />
+ <parameter name="MEM_RLD3_ODT_MODE_ENUM" value="RLD3_ODT_40" />
+ <parameter name="MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM">RLD3_OUTPUT_DRIVE_40</parameter>
+ <parameter name="MEM_RLD3_SPEEDBIN_ENUM" value="RLD3_SPEEDBIN_093E" />
+ <parameter name="MEM_RLD3_TCKDK_MAX_CYC" value="0.27" />
+ <parameter name="MEM_RLD3_TCKDK_MIN_CYC" value="-0.27" />
+ <parameter name="MEM_RLD3_TCKQK_MAX_PS" value="135" />
+ <parameter name="MEM_RLD3_TDH_DC_MV" value="100" />
+ <parameter name="MEM_RLD3_TDH_PS" value="5" />
+ <parameter name="MEM_RLD3_TDS_AC_MV" value="150" />
+ <parameter name="MEM_RLD3_TDS_PS" value="-30" />
+ <parameter name="MEM_RLD3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_RLD3_TIH_PS" value="65" />
+ <parameter name="MEM_RLD3_TIS_AC_MV" value="150" />
+ <parameter name="MEM_RLD3_TIS_PS" value="85" />
+ <parameter name="MEM_RLD3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_RLD3_TQKQ_MAX_PS" value="75" />
+ <parameter name="MEM_RLD3_T_RC_MODE_ENUM" value="RLD3_TRC_9" />
+ <parameter name="MEM_RLD3_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_WRITE_PROTOCOL_ENUM" value="RLD3_WRITE_1BANK" />
+ <parameter name="PHY_DDR3_CAL_ADDR0" value="0" />
+ <parameter name="PHY_DDR3_CAL_ADDR1" value="8" />
+ <parameter name="PHY_DDR3_CAL_ENABLE_NON_DES" value="true" />
+ <parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_DDR3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_DDR3_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_DDR3_IO_VOLTAGE" value="1.5" />
+ <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_DDR3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_DDR3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_DDR4_DEFAULT_IO" value="false" />
+ <parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="false" />
+ <parameter name="PHY_DDR4_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="800.0" />
+ <parameter name="PHY_DDR4_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_DDR4_STARTING_VREFIN" value="68.0" />
+ <parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="IO_STD_SSTL_12" />
+ <parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="OUT_OCT_40_CAL" />
+ <parameter name="PHY_DDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="IO_STD_SSTL_12" />
+ <parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="OUT_OCT_40_CAL" />
+ <parameter name="PHY_DDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="IN_OCT_120_CAL" />
+ <parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="IO_STD_POD_12" />
+ <parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="OUT_OCT_34_CAL" />
+ <parameter name="PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_DDR4_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="IO_STD_CMOS_12" />
+ <parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="25.0" />
+ <parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="IO_STD_CMOS_12" />
+ <parameter name="PHY_LPDDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_LPDDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_LPDDR3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_LPDDR3_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_LPDDR3_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_LPDDR3_MEM_CLK_FREQ_MHZ" value="800.0" />
+ <parameter name="PHY_LPDDR3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_LPDDR3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_LPDDR3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_LPDDR3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_LPDDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_LPDDR3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_LPDDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_QDR2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_QDR2_DEFAULT_IO" value="true" />
+ <parameter name="PHY_QDR2_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_QDR2_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_QDR2_IO_VOLTAGE" value="1.5" />
+ <parameter name="PHY_QDR2_MEM_CLK_FREQ_MHZ" value="633.333" />
+ <parameter name="PHY_QDR2_RATE_ENUM" value="RATE_HALF" />
+ <parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_QDR2_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_QDR2_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_QDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_QDR4_DEFAULT_IO" value="true" />
+ <parameter name="PHY_QDR4_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_QDR4_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_QDR4_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_QDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_QDR4_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_QDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR4_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_QDR4_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR4_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_QDR4_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_QDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_RLD2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_RLD2_DEFAULT_IO" value="true" />
+ <parameter name="PHY_RLD2_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_RLD2_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_RLD2_IO_VOLTAGE" value="1.8" />
+ <parameter name="PHY_RLD2_MEM_CLK_FREQ_MHZ" value="533.333" />
+ <parameter name="PHY_RLD2_RATE_ENUM" value="RATE_HALF" />
+ <parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_RLD2_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_RLD2_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_CONFIG_ENUM" value="CONFIG_PHY_ONLY" />
+ <parameter name="PHY_RLD3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_RLD3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_RLD3_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_RLD3_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_RLD3_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_RLD3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_RLD3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_RLD3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PLL_ADD_EXTRA_CLKS" value="0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8" value="0" />
+ <parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
+ <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
+ <parameter name="SHORT_QSYS_INTERFACE_NAMES" value="true" />
+ <parameter name="SYS_INFO_DEVICE" value="10AX115S2F45E1SG" />
+ <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="1" />
+ <parameter name="SYS_INFO_UNIQUE_ID">ip_arria10_e1sg_ddr4_4g_1600_emif_0</parameter>
+ <parameter name="TRAIT_SUPPORTS_VID" value="0" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d1d4ac6eee0ec9a6192832f216b159d80ab91dd4
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
@@ -0,0 +1,33 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generated/sim"
+
+# Copy ROM/RAM files to simulation directory
+if {[file isdirectory $IP_DIR]} {
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_151_mhuabmq_seq_cal_sim.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_151_mhuabmq_seq_cal_synth.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_151_mhuabmq_seq_params_sim.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_151_mhuabmq_seq_params_synth.hex ./
+}
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..64364ce034a0cc001573064b4e3faf8751f931c8
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/generate_ip.sh
@@ -0,0 +1,54 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_ddr4_4g_2000.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
+
+# Also generate the testbench IP, this is not useful because it only generates bus functional models, so not a DDR4 memory model
+#qsys-generate ip_arria10_e1sg_ddr4_4g_2000.qsys \
+# --synthesis=VHDL \
+# --simulation=VHDL \
+# --testbench=STANDARD \
+# --testbench-simulation=VHDL \
+# --output-directory=generated \
+# --allow-mixed-language-simulation \
+# --allow-mixed-language-testbench-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..629af067fcb0844b9a3dd1d7849ffd8a0f46f2a7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_ddr4_4g_2000
+hdl_library_clause_name = ip_arria10_e1sg_ddr4_4g_2000_altera_emif_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_ddr4_4g_2000.qip
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qsys b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..9b95d39c56d92aede77ab56211c4665e45ebfa1b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qsys
@@ -0,0 +1,1170 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_ddr4_4g_2000">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element emif_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>ctrl_amm_0</key>
+ <value>
+ <connectionPointName>ctrl_amm_0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='ctrl_amm_0' start='0x0' end='0x120000000' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>33</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>576</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>emif_usr_clk</key>
+ <value>
+ <connectionPointName>emif_usr_clk</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>250000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="ctrl_amm_0"
+ internal="emif_0.ctrl_amm_0"
+ type="avalon"
+ dir="end">
+ <port name="amm_address_0" internal="amm_address_0" />
+ <port name="amm_burstcount_0" internal="amm_burstcount_0" />
+ <port name="amm_byteenable_0" internal="amm_byteenable_0" />
+ <port name="amm_read_0" internal="amm_read_0" />
+ <port name="amm_readdata_0" internal="amm_readdata_0" />
+ <port name="amm_readdatavalid_0" internal="amm_readdatavalid_0" />
+ <port name="amm_ready_0" internal="amm_ready_0" />
+ <port name="amm_write_0" internal="amm_write_0" />
+ <port name="amm_writedata_0" internal="amm_writedata_0" />
+ </interface>
+ <interface name="ctrl_mmr_slave_0" internal="emif_0.ctrl_mmr_slave_0" />
+ <interface
+ name="emif_usr_clk"
+ internal="emif_0.emif_usr_clk"
+ type="clock"
+ dir="start">
+ <port name="emif_usr_clk" internal="emif_usr_clk" />
+ </interface>
+ <interface
+ name="emif_usr_reset_n"
+ internal="emif_0.emif_usr_reset_n"
+ type="reset"
+ dir="start">
+ <port name="emif_usr_reset_n" internal="emif_usr_reset_n" />
+ </interface>
+ <interface
+ name="global_reset_n"
+ internal="emif_0.global_reset_n"
+ type="reset"
+ dir="end">
+ <port name="global_reset_n" internal="global_reset_n" />
+ </interface>
+ <interface name="mem" internal="emif_0.mem" type="conduit" dir="end">
+ <port name="mem_a" internal="mem_a" />
+ <port name="mem_act_n" internal="mem_act_n" />
+ <port name="mem_alert_n" internal="mem_alert_n" />
+ <port name="mem_ba" internal="mem_ba" />
+ <port name="mem_bg" internal="mem_bg" />
+ <port name="mem_ck" internal="mem_ck" />
+ <port name="mem_ck_n" internal="mem_ck_n" />
+ <port name="mem_cke" internal="mem_cke" />
+ <port name="mem_cs_n" internal="mem_cs_n" />
+ <port name="mem_dbi_n" internal="mem_dbi_n" />
+ <port name="mem_dq" internal="mem_dq" />
+ <port name="mem_dqs" internal="mem_dqs" />
+ <port name="mem_dqs_n" internal="mem_dqs_n" />
+ <port name="mem_odt" internal="mem_odt" />
+ <port name="mem_par" internal="mem_par" />
+ <port name="mem_reset_n" internal="mem_reset_n" />
+ </interface>
+ <interface name="oct" internal="emif_0.oct" type="conduit" dir="end">
+ <port name="oct_rzqin" internal="oct_rzqin" />
+ </interface>
+ <interface
+ name="pll_ref_clk"
+ internal="emif_0.pll_ref_clk"
+ type="clock"
+ dir="end">
+ <port name="pll_ref_clk" internal="pll_ref_clk" />
+ </interface>
+ <interface name="status" internal="emif_0.status" type="conduit" dir="end">
+ <port name="local_cal_fail" internal="local_cal_fail" />
+ <port name="local_cal_success" internal="local_cal_success" />
+ </interface>
+ <module
+ name="emif_0"
+ kind="altera_emif"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR3_MAX_DQS_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_DDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR3_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR3_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_RCLK_SLEW_RATE" value="5.0" />
+ <parameter name="BOARD_DDR3_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_RDATA_SLEW_RATE" value="2.5" />
+ <parameter name="BOARD_DDR3_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR3_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_DDR3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="0.013" />
+ <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.146" />
+ <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.03" />
+ <parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="-0.21" />
+ <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.252" />
+ <parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.323" />
+ <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.072" />
+ <parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.133" />
+ <parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="8.0" />
+ <parameter name="BOARD_DDR4_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_DDR4_USE_DEFAULT_SLEW_RATES" value="false" />
+ <parameter name="BOARD_LPDDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+ <parameter name="BOARD_LPDDR3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_LPDDR3_MAX_DQS_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_LPDDR3_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_LPDDR3_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_LPDDR3_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_RDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_LPDDR3_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_LPDDR3_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_QDR2_AC_TO_K_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR2_MAX_K_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_K_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR2_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR2_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_RDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_QDR2_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_QDR4_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_DK_TO_CK_SKEW_NS" value="-0.02" />
+ <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR4_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR4_MAX_DK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_QDR4_SKEW_BETWEEN_DK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR4_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_RCLK_SLEW_RATE" value="5.0" />
+ <parameter name="BOARD_QDR4_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_RDATA_SLEW_RATE" value="2.5" />
+ <parameter name="BOARD_QDR4_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_QDR4_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_RLD3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_DK_TO_CK_SKEW_NS" value="-0.02" />
+ <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+ <parameter name="BOARD_RLD3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_RLD3_MAX_DK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_RLD3_SKEW_BETWEEN_DK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_RLD3_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_RCLK_SLEW_RATE" value="7.0" />
+ <parameter name="BOARD_RLD3_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_RDATA_SLEW_RATE" value="3.5" />
+ <parameter name="BOARD_RLD3_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="CAL_DEBUG_CLOCK_FREQUENCY" value="50000000" />
+ <parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_DDR3_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_DDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_DDR3_ECC_AUTO_CORRECTION_EN" value="false" />
+ <parameter name="CTRL_DDR3_ECC_EN" value="false" />
+ <parameter name="CTRL_DDR3_MMR_EN" value="false" />
+ <parameter name="CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_REORDER_EN" value="true" />
+ <parameter name="CTRL_DDR3_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR3_STARVE_LIMIT" value="10" />
+ <parameter name="CTRL_DDR3_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_DDR3_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_ADDR_ORDER_ENUM">DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG</parameter>
+ <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_DDR4_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_DDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_DDR4_ECC_AUTO_CORRECTION_EN" value="false" />
+ <parameter name="CTRL_DDR4_ECC_EN" value="false" />
+ <parameter name="CTRL_DDR4_MMR_EN" value="false" />
+ <parameter name="CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_REORDER_EN" value="true" />
+ <parameter name="CTRL_DDR4_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR4_STARVE_LIMIT" value="10" />
+ <parameter name="CTRL_DDR4_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_DDR4_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_ADDR_ORDER_ENUM">LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_LPDDR3_MMR_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_REORDER_EN" value="true" />
+ <parameter name="CTRL_LPDDR3_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_STARVE_LIMIT" value="10" />
+ <parameter name="CTRL_LPDDR3_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+ <parameter name="CTRL_QDR2_AVL_MAX_BURST_COUNT" value="4" />
+ <parameter name="CTRL_QDR2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC" value="0" />
+ <parameter name="CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC" value="0" />
+ <parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+ <parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
+ <parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
+ <parameter name="DIAG_DDR3_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_DDR3_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_DDR3_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_DDR3_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_DDR3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_DDR3_CAL_ADDR0" value="0" />
+ <parameter name="DIAG_DDR3_CAL_ADDR1" value="8" />
+ <parameter name="DIAG_DDR3_CAL_ENABLE_NON_DES" value="false" />
+ <parameter name="DIAG_DDR3_CAL_FULL_CAL_ON_RESET" value="true" />
+ <parameter name="DIAG_DDR3_CA_LEVEL_EN" value="false" />
+ <parameter name="DIAG_DDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR3_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_DDR3_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR3_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR3_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_DDR4_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_DDR4_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_DDR4_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_DDR4_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_DDR4_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_DDR4_CAL_ADDR0" value="0" />
+ <parameter name="DIAG_DDR4_CAL_ADDR1" value="8" />
+ <parameter name="DIAG_DDR4_CAL_ENABLE_NON_DES" value="false" />
+ <parameter name="DIAG_DDR4_CAL_FULL_CAL_ON_RESET" value="true" />
+ <parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR4_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_DDR4_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
+ <parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="false" />
+ <parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="true" />
+ <parameter name="DIAG_DDR4_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR4_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR4_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
+ <parameter name="DIAG_ENABLE_HPS_EMIF_DEBUG" value="false" />
+ <parameter name="DIAG_ENABLE_JTAG_UART" value="false" />
+ <parameter name="DIAG_ENABLE_JTAG_UART_HEX" value="false" />
+ <parameter name="DIAG_EXPORT_VJI" value="false" />
+ <parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
+ <parameter name="DIAG_EXTRA_CONFIGS" value="" />
+ <parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
+ <parameter name="DIAG_EX_DESIGN_SEPARATE_RESETS" value="false" />
+ <parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
+ <parameter name="DIAG_LPDDR3_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_LPDDR3_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_LPDDR3_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_LPDDR3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_LPDDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_LPDDR3_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_LPDDR3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_LPDDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_LPDDR3_SKIP_CA_DESKEW" value="false" />
+ <parameter name="DIAG_LPDDR3_SKIP_CA_LEVEL" value="false" />
+ <parameter name="DIAG_LPDDR3_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_LPDDR3_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_LPDDR3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_QDR2_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_QDR2_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_QDR2_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_QDR2_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_QDR2_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_QDR2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR2_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_QDR2_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR2_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR2_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR2_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_QDR4_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_QDR4_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_QDR4_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_QDR4_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_QDR4_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_QDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR4_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_QDR4_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR4_SKIP_VREF_CAL" value="false" />
+ <parameter name="DIAG_QDR4_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR4_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR4_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RLD2_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_RLD2_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_RLD2_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_RLD2_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_RLD2_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_RLD2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD2_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_RLD2_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD2_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD2_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD2_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RLD3_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_RLD3_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_RLD3_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_RLD3_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_RLD3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_RLD3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD3_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_RLD3_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD3_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD3_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RS232_UART_BAUDRATE" value="57600" />
+ <parameter name="DIAG_SIM_REGTEST_MODE" value="false" />
+ <parameter name="DIAG_SOFT_NIOS_CLOCK_FREQUENCY" value="100" />
+ <parameter name="DIAG_SOFT_NIOS_MODE">SOFT_NIOS_MODE_DISABLED</parameter>
+ <parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
+ <parameter name="DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE" value="false" />
+ <parameter name="DIAG_TG_AVL_2_NUM_CFG_INTERFACES" value="0" />
+ <parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
+ <parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
+ <parameter name="DIAG_USE_RS232_UART" value="false" />
+ <parameter name="DIAG_VERBOSE_IOAUX" value="false" />
+ <parameter name="EX_DESIGN_GUI_DDR3_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR3_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_DDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_DDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_DDR4_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR4_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_DDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_DDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter
+ name="EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT"
+ value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR2_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR2_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_QDR2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR4_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR4_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_QDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD2_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD2_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_RLD2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD3_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD3_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_RLD3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="INTERNAL_TESTING_MODE" value="false" />
+ <parameter name="IS_ED_SLAVE" value="false" />
+ <parameter name="MEM_DDR3_ALERT_N_DQS_GROUP" value="0" />
+ <parameter name="MEM_DDR3_ALERT_N_PLACEMENT_ENUM">DDR3_ALERT_N_PLACEMENT_AC_LANES</parameter>
+ <parameter name="MEM_DDR3_ASR_ENUM" value="DDR3_ASR_MANUAL" />
+ <parameter name="MEM_DDR3_ATCL_ENUM" value="DDR3_ATCL_DISABLED" />
+ <parameter name="MEM_DDR3_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_DDR3_BL_ENUM" value="DDR3_BL_BL8" />
+ <parameter name="MEM_DDR3_BT_ENUM" value="DDR3_BT_SEQUENTIAL" />
+ <parameter name="MEM_DDR3_CKE_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR3_CK_WIDTH" value="1" />
+ <parameter name="MEM_DDR3_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_DDR3_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR3_DLL_EN" value="true" />
+ <parameter name="MEM_DDR3_DM_EN" value="true" />
+ <parameter name="MEM_DDR3_DQ_PER_DQS" value="8" />
+ <parameter name="MEM_DDR3_DQ_WIDTH" value="72" />
+ <parameter name="MEM_DDR3_DRV_STR_ENUM" value="DDR3_DRV_STR_RZQ_7" />
+ <parameter name="MEM_DDR3_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
+ <parameter name="MEM_DDR3_HIDE_ADV_MR_SETTINGS" value="true" />
+ <parameter name="MEM_DDR3_LRDIMM_EXTENDED_CONFIG" value="000000000000000000" />
+ <parameter name="MEM_DDR3_MIRROR_ADDRESSING_EN" value="true" />
+ <parameter name="MEM_DDR3_NUM_OF_DIMMS" value="1" />
+ <parameter name="MEM_DDR3_PD_ENUM" value="DDR3_PD_OFF" />
+ <parameter name="MEM_DDR3_RANKS_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR3_RDIMM_CONFIG" value="0000000000000000" />
+ <parameter name="MEM_DDR3_ROW_ADDR_WIDTH" value="15" />
+ <parameter name="MEM_DDR3_RTT_NOM_ENUM">DDR3_RTT_NOM_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR3_RTT_WR_ENUM" value="DDR3_RTT_WR_RZQ_4" />
+ <parameter name="MEM_DDR3_R_ODT0_1X1" value="off" />
+ <parameter name="MEM_DDR3_R_ODT0_2X2" value="off,off" />
+ <parameter name="MEM_DDR3_R_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_R_ODT0_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR3_R_ODT1_2X2" value="off,off" />
+ <parameter name="MEM_DDR3_R_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_R_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_R_ODT2_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR3_R_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR3_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_SPEEDBIN_ENUM" value="DDR3_SPEEDBIN_2133" />
+ <parameter name="MEM_DDR3_SRT_ENUM" value="DDR3_SRT_NORMAL" />
+ <parameter name="MEM_DDR3_TCL" value="14" />
+ <parameter name="MEM_DDR3_TDH_DC_MV" value="100" />
+ <parameter name="MEM_DDR3_TDH_PS" value="55" />
+ <parameter name="MEM_DDR3_TDQSCK_PS" value="180" />
+ <parameter name="MEM_DDR3_TDQSQ_PS" value="75" />
+ <parameter name="MEM_DDR3_TDQSS_CYC" value="0.27" />
+ <parameter name="MEM_DDR3_TDSH_CYC" value="0.18" />
+ <parameter name="MEM_DDR3_TDSS_CYC" value="0.18" />
+ <parameter name="MEM_DDR3_TDS_AC_MV" value="135" />
+ <parameter name="MEM_DDR3_TDS_PS" value="53" />
+ <parameter name="MEM_DDR3_TFAW_NS" value="25.0" />
+ <parameter name="MEM_DDR3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_DDR3_TIH_PS" value="95" />
+ <parameter name="MEM_DDR3_TINIT_US" value="500" />
+ <parameter name="MEM_DDR3_TIS_AC_MV" value="135" />
+ <parameter name="MEM_DDR3_TIS_PS" value="60" />
+ <parameter name="MEM_DDR3_TMRD_CK_CYC" value="4" />
+ <parameter name="MEM_DDR3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_DDR3_TQSH_CYC" value="0.4" />
+ <parameter name="MEM_DDR3_TRAS_NS" value="33.0" />
+ <parameter name="MEM_DDR3_TRCD_NS" value="13.09" />
+ <parameter name="MEM_DDR3_TREFI_US" value="7.8" />
+ <parameter name="MEM_DDR3_TRFC_NS" value="160.0" />
+ <parameter name="MEM_DDR3_TRP_NS" value="13.09" />
+ <parameter name="MEM_DDR3_TRRD_CYC" value="6" />
+ <parameter name="MEM_DDR3_TRTP_CYC" value="8" />
+ <parameter name="MEM_DDR3_TWLH_PS" value="125.0" />
+ <parameter name="MEM_DDR3_TWLS_PS" value="125.0" />
+ <parameter name="MEM_DDR3_TWR_NS" value="15.0" />
+ <parameter name="MEM_DDR3_TWTR_CYC" value="8" />
+ <parameter name="MEM_DDR3_USE_DEFAULT_ODT" value="true" />
+ <parameter name="MEM_DDR3_WTCL" value="10" />
+ <parameter name="MEM_DDR3_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR3_W_ODT0_2X2" value="on,off" />
+ <parameter name="MEM_DDR3_W_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT0_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODT1_2X2" value="off,on" />
+ <parameter name="MEM_DDR3_W_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT2_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR3_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_AC_PARITY_LATENCY">DDR4_AC_PARITY_LATENCY_DISABLE</parameter>
+ <parameter name="MEM_DDR4_AC_PERSISTENT_ERROR" value="false" />
+ <parameter name="MEM_DDR4_ALERT_N_AC_LANE" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_AC_PIN" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_DQS_GROUP" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_PLACEMENT_ENUM">DDR4_ALERT_N_PLACEMENT_DATA_LANES</parameter>
+ <parameter name="MEM_DDR4_ALERT_PAR_EN" value="true" />
+ <parameter name="MEM_DDR4_ASR_ENUM">DDR4_ASR_MANUAL_NORMAL</parameter>
+ <parameter name="MEM_DDR4_ATCL_ENUM" value="DDR4_ATCL_DISABLED" />
+ <parameter name="MEM_DDR4_BANK_ADDR_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_BANK_GROUP_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_BL_ENUM" value="DDR4_BL_BL8" />
+ <parameter name="MEM_DDR4_BT_ENUM" value="DDR4_BT_SEQUENTIAL" />
+ <parameter name="MEM_DDR4_CAL_MODE" value="0" />
+ <parameter name="MEM_DDR4_CHIP_ID_WIDTH" value="0" />
+ <parameter name="MEM_DDR4_CKE_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR4_CK_WIDTH" value="1" />
+ <parameter name="MEM_DDR4_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_DDR4_DB_DQ_DRV_ENUM">DDR4_DB_DRV_STR_RZQ_7</parameter>
+ <parameter name="MEM_DDR4_DB_RTT_NOM_ENUM">DDR4_DB_RTT_NOM_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_DB_RTT_PARK_ENUM">DDR4_DB_RTT_PARK_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_DB_RTT_WR_ENUM">DDR4_DB_RTT_WR_RZQ_3</parameter>
+ <parameter name="MEM_DDR4_DEFAULT_VREFOUT" value="false" />
+ <parameter name="MEM_DDR4_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR4_DLL_EN" value="true" />
+ <parameter name="MEM_DDR4_DM_EN" value="true" />
+ <parameter name="MEM_DDR4_DQ_PER_DQS" value="8" />
+ <parameter name="MEM_DDR4_DQ_WIDTH" value="72" />
+ <parameter name="MEM_DDR4_DRV_STR_ENUM" value="DDR4_DRV_STR_RZQ_7" />
+ <parameter name="MEM_DDR4_FINE_GRANULARITY_REFRESH">DDR4_FINE_REFRESH_FIXED_1X</parameter>
+ <parameter name="MEM_DDR4_FORMAT_ENUM" value="MEM_FORMAT_SODIMM" />
+ <parameter name="MEM_DDR4_GEARDOWN" value="DDR4_GEARDOWN_HR" />
+ <parameter name="MEM_DDR4_HIDE_ADV_MR_SETTINGS" value="true" />
+ <parameter name="MEM_DDR4_INTERNAL_VREFDQ_MONITOR" value="true" />
+ <parameter name="MEM_DDR4_LRDIMM_ODT_LESS_BS" value="true" />
+ <parameter name="MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM" value="240" />
+ <parameter name="MEM_DDR4_LRDIMM_VREFDQ_VALUE" value="1D" />
+ <parameter name="MEM_DDR4_MAX_POWERDOWN" value="false" />
+ <parameter name="MEM_DDR4_MIRROR_ADDRESSING_EN" value="true" />
+ <parameter name="MEM_DDR4_MPR_READ_FORMAT">DDR4_MPR_READ_FORMAT_SERIAL</parameter>
+ <parameter name="MEM_DDR4_NUM_OF_DIMMS" value="1" />
+ <parameter name="MEM_DDR4_ODT_IN_POWERDOWN" value="true" />
+ <parameter name="MEM_DDR4_PER_DRAM_ADDR" value="false" />
+ <parameter name="MEM_DDR4_RANKS_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR4_RCD_CA_IBT_ENUM" value="DDR4_RCD_CA_IBT_100" />
+ <parameter name="MEM_DDR4_RCD_CKE_IBT_ENUM">DDR4_RCD_CKE_IBT_100</parameter>
+ <parameter name="MEM_DDR4_RCD_CS_IBT_ENUM" value="DDR4_RCD_CS_IBT_100" />
+ <parameter name="MEM_DDR4_RCD_ODT_IBT_ENUM">DDR4_RCD_ODT_IBT_100</parameter>
+ <parameter name="MEM_DDR4_READ_DBI" value="false" />
+ <parameter name="MEM_DDR4_READ_PREAMBLE" value="2" />
+ <parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
+ <parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
+ <parameter name="MEM_DDR4_RTT_NOM_ENUM" value="DDR4_RTT_NOM_RZQ_4" />
+ <parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_RTT_WR_ENUM">DDR4_RTT_WR_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_R_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR4_R_ODT0_2X2" value="off,off" />
+ <parameter name="MEM_DDR4_R_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_R_ODT0_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR4_R_ODT1_2X2" value="off,off" />
+ <parameter name="MEM_DDR4_R_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_R_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_R_ODT2_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR4_R_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR4_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR4_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_SELF_RFSH_ABORT" value="false" />
+ <parameter name="MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB" value="0" />
+ <parameter name="MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB" value="0" />
+ <parameter name="MEM_DDR4_SPD_135_RCD_REV" value="0" />
+ <parameter name="MEM_DDR4_SPD_137_RCD_CA_DRV" value="101" />
+ <parameter name="MEM_DDR4_SPD_138_RCD_CK_DRV" value="5" />
+ <parameter name="MEM_DDR4_SPD_139_DB_REV" value="0" />
+ <parameter name="MEM_DDR4_SPD_140_DRAM_VREFDQ_R0" value="29" />
+ <parameter name="MEM_DDR4_SPD_141_DRAM_VREFDQ_R1" value="29" />
+ <parameter name="MEM_DDR4_SPD_142_DRAM_VREFDQ_R2" value="29" />
+ <parameter name="MEM_DDR4_SPD_143_DRAM_VREFDQ_R3" value="29" />
+ <parameter name="MEM_DDR4_SPD_144_DB_VREFDQ" value="37" />
+ <parameter name="MEM_DDR4_SPD_145_DB_MDQ_DRV" value="21" />
+ <parameter name="MEM_DDR4_SPD_148_DRAM_DRV" value="0" />
+ <parameter name="MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM" value="20" />
+ <parameter name="MEM_DDR4_SPD_152_DRAM_RTT_PARK" value="39" />
+ <parameter name="MEM_DDR4_SPEEDBIN_ENUM" value="DDR4_SPEEDBIN_2133" />
+ <parameter name="MEM_DDR4_TCCD_L_CYC" value="6" />
+ <parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
+ <parameter name="MEM_DDR4_TCL" value="15" />
+ <parameter name="MEM_DDR4_TDIVW_DJ_CYC" value="0.1" />
+ <parameter name="MEM_DDR4_TDIVW_TOTAL_UI" value="0.2" />
+ <parameter name="MEM_DDR4_TDQSCK_PS" value="170" />
+ <parameter name="MEM_DDR4_TDQSQ_PS" value="66" />
+ <parameter name="MEM_DDR4_TDQSQ_UI" value="0.16" />
+ <parameter name="MEM_DDR4_TDQSS_CYC" value="0.27" />
+ <parameter name="MEM_DDR4_TDSH_CYC" value="0.18" />
+ <parameter name="MEM_DDR4_TDSS_CYC" value="0.18" />
+ <parameter name="MEM_DDR4_TDVWP_UI" value="0.72" />
+ <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA" value="false" />
+ <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
+ <parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
+ <parameter name="MEM_DDR4_TFAW_NS" value="21.0" />
+ <parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
+ <parameter name="MEM_DDR4_TIH_PS" value="105" />
+ <parameter name="MEM_DDR4_TINIT_US" value="500" />
+ <parameter name="MEM_DDR4_TIS_AC_MV" value="100" />
+ <parameter name="MEM_DDR4_TIS_PS" value="80" />
+ <parameter name="MEM_DDR4_TMRD_CK_CYC" value="8" />
+ <parameter name="MEM_DDR4_TQH_CYC" value="0.38" />
+ <parameter name="MEM_DDR4_TQH_UI" value="0.76" />
+ <parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
+ <parameter name="MEM_DDR4_TRAS_NS" value="33.0" />
+ <parameter name="MEM_DDR4_TRCD_NS" value="14.06" />
+ <parameter name="MEM_DDR4_TREFI_US" value="7.8" />
+ <parameter name="MEM_DDR4_TRFC_NS" value="260.0" />
+ <parameter name="MEM_DDR4_TRP_NS" value="14.06" />
+ <parameter name="MEM_DDR4_TRRD_L_CYC" value="6" />
+ <parameter name="MEM_DDR4_TRRD_S_CYC" value="4" />
+ <parameter name="MEM_DDR4_TWLH_PS" value="130.0" />
+ <parameter name="MEM_DDR4_TWLS_PS" value="130.0" />
+ <parameter name="MEM_DDR4_TWR_NS" value="15.0" />
+ <parameter name="MEM_DDR4_TWTR_L_CYC" value="8" />
+ <parameter name="MEM_DDR4_TWTR_S_CYC" value="3" />
+ <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_1</parameter>
+ <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_VALUE" value="68.0" />
+ <parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="false" />
+ <parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
+ <parameter name="MEM_DDR4_WRITE_CRC" value="false" />
+ <parameter name="MEM_DDR4_WRITE_DBI" value="false" />
+ <parameter name="MEM_DDR4_WRITE_PREAMBLE" value="1" />
+ <parameter name="MEM_DDR4_WTCL" value="11" />
+ <parameter name="MEM_DDR4_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR4_W_ODT0_2X2" value="on,off" />
+ <parameter name="MEM_DDR4_W_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT0_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODT1_2X2" value="off,on" />
+ <parameter name="MEM_DDR4_W_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT2_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR4_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR4_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_LPDDR3_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_LPDDR3_BL" value="LPDDR3_BL_BL8" />
+ <parameter name="MEM_LPDDR3_CK_WIDTH" value="1" />
+ <parameter name="MEM_LPDDR3_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_LPDDR3_DATA_LATENCY" value="LPDDR3_DL_RL12_WL6" />
+ <parameter name="MEM_LPDDR3_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_LPDDR3_DM_EN" value="true" />
+ <parameter name="MEM_LPDDR3_DQODT">LPDDR3_DQODT_DISABLE</parameter>
+ <parameter name="MEM_LPDDR3_DQ_WIDTH" value="32" />
+ <parameter name="MEM_LPDDR3_DRV_STR">LPDDR3_DRV_STR_40D_40U</parameter>
+ <parameter name="MEM_LPDDR3_NWR" value="LPDDR3_NWR_NWR10" />
+ <parameter name="MEM_LPDDR3_PDODT">LPDDR3_PDODT_DISABLED</parameter>
+ <parameter name="MEM_LPDDR3_ROW_ADDR_WIDTH" value="15" />
+ <parameter name="MEM_LPDDR3_R_ODT0_1X1" value="off" />
+ <parameter name="MEM_LPDDR3_R_ODT0_2X2" value="off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT0_4X4" value="off,off,on,on" />
+ <parameter name="MEM_LPDDR3_R_ODT1_2X2" value="off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT1_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT2_4X4" value="on,on,off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT3_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_LPDDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_LPDDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_LPDDR3_SPEEDBIN_ENUM">LPDDR3_SPEEDBIN_1600</parameter>
+ <parameter name="MEM_LPDDR3_TDH_DC_MV" value="100" />
+ <parameter name="MEM_LPDDR3_TDH_PS" value="100" />
+ <parameter name="MEM_LPDDR3_TDQSCKDL" value="614" />
+ <parameter name="MEM_LPDDR3_TDQSQ_PS" value="135" />
+ <parameter name="MEM_LPDDR3_TDQSS_CYC" value="1.25" />
+ <parameter name="MEM_LPDDR3_TDSH_CYC" value="0.2" />
+ <parameter name="MEM_LPDDR3_TDSS_CYC" value="0.2" />
+ <parameter name="MEM_LPDDR3_TDS_AC_MV" value="150" />
+ <parameter name="MEM_LPDDR3_TDS_PS" value="75" />
+ <parameter name="MEM_LPDDR3_TFAW_NS" value="50.0" />
+ <parameter name="MEM_LPDDR3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_LPDDR3_TIH_PS" value="100" />
+ <parameter name="MEM_LPDDR3_TINIT_US" value="500" />
+ <parameter name="MEM_LPDDR3_TIS_AC_MV" value="150" />
+ <parameter name="MEM_LPDDR3_TIS_PS" value="75" />
+ <parameter name="MEM_LPDDR3_TMRR_CK_CYC" value="4" />
+ <parameter name="MEM_LPDDR3_TMRW_CK_CYC" value="10" />
+ <parameter name="MEM_LPDDR3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_LPDDR3_TQSH_CYC" value="0.38" />
+ <parameter name="MEM_LPDDR3_TRAS_NS" value="42.5" />
+ <parameter name="MEM_LPDDR3_TRCD_NS" value="18.75" />
+ <parameter name="MEM_LPDDR3_TREFI_US" value="3.9" />
+ <parameter name="MEM_LPDDR3_TRFC_NS" value="210.0" />
+ <parameter name="MEM_LPDDR3_TRP_NS" value="18.75" />
+ <parameter name="MEM_LPDDR3_TRRD_CYC" value="2" />
+ <parameter name="MEM_LPDDR3_TRTP_CYC" value="4" />
+ <parameter name="MEM_LPDDR3_TWLH_PS" value="175.0" />
+ <parameter name="MEM_LPDDR3_TWLS_PS" value="175.0" />
+ <parameter name="MEM_LPDDR3_TWR_NS" value="15.0" />
+ <parameter name="MEM_LPDDR3_TWTR_CYC" value="4" />
+ <parameter name="MEM_LPDDR3_USE_DEFAULT_ODT" value="true" />
+ <parameter name="MEM_LPDDR3_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_LPDDR3_W_ODT0_2X2" value="on,off" />
+ <parameter name="MEM_LPDDR3_W_ODT0_4X4" value="on,on,on,on" />
+ <parameter name="MEM_LPDDR3_W_ODT1_2X2" value="off,on" />
+ <parameter name="MEM_LPDDR3_W_ODT1_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_W_ODT2_4X4" value="on,on,on,on" />
+ <parameter name="MEM_LPDDR3_W_ODT3_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_LPDDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_LPDDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_QDR2_ADDR_WIDTH" value="19" />
+ <parameter name="MEM_QDR2_BL" value="4" />
+ <parameter name="MEM_QDR2_BWS_EN" value="true" />
+ <parameter name="MEM_QDR2_DATA_PER_DEVICE" value="36" />
+ <parameter name="MEM_QDR2_INTERNAL_JITTER_NS" value="0.08" />
+ <parameter name="MEM_QDR2_SPEEDBIN_ENUM" value="QDR2_SPEEDBIN_633" />
+ <parameter name="MEM_QDR2_TCCQO_NS" value="0.45" />
+ <parameter name="MEM_QDR2_TCQDOH_NS" value="-0.09" />
+ <parameter name="MEM_QDR2_TCQD_NS" value="0.09" />
+ <parameter name="MEM_QDR2_TCQH_NS" value="0.71" />
+ <parameter name="MEM_QDR2_THA_NS" value="0.18" />
+ <parameter name="MEM_QDR2_THD_NS" value="0.18" />
+ <parameter name="MEM_QDR2_TRL_CYC" value="2.5" />
+ <parameter name="MEM_QDR2_TSA_NS" value="0.23" />
+ <parameter name="MEM_QDR2_TSD_NS" value="0.23" />
+ <parameter name="MEM_QDR2_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_QDR4_AC_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_ADDR_INV_ENA" value="false" />
+ <parameter name="MEM_QDR4_ADDR_WIDTH" value="21" />
+ <parameter name="MEM_QDR4_CK_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_DATA_INV_ENA" value="false" />
+ <parameter name="MEM_QDR4_DATA_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_DQ_PER_PORT_PER_DEVICE" value="36" />
+ <parameter name="MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+ <parameter name="MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+ <parameter name="MEM_QDR4_SPEEDBIN_ENUM" value="QDR4_SPEEDBIN_2133" />
+ <parameter name="MEM_QDR4_TASH_PS" value="170" />
+ <parameter name="MEM_QDR4_TCKDK_MAX_PS" value="150" />
+ <parameter name="MEM_QDR4_TCKDK_MIN_PS" value="-150" />
+ <parameter name="MEM_QDR4_TCKQK_MAX_PS" value="225" />
+ <parameter name="MEM_QDR4_TCSH_PS" value="170" />
+ <parameter name="MEM_QDR4_TISH_PS" value="150" />
+ <parameter name="MEM_QDR4_TQH_CYC" value="0.4" />
+ <parameter name="MEM_QDR4_TQKQ_MAX_PS" value="75" />
+ <parameter name="MEM_QDR4_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD2_ADDR_WIDTH" value="21" />
+ <parameter name="MEM_RLD2_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_RLD2_BL" value="4" />
+ <parameter name="MEM_RLD2_CONFIG_ENUM">RLD2_CONFIG_TRC_8_TRL_8_TWL_9</parameter>
+ <parameter name="MEM_RLD2_DM_EN" value="true" />
+ <parameter name="MEM_RLD2_DQ_PER_DEVICE" value="9" />
+ <parameter name="MEM_RLD2_DRIVE_IMPEDENCE_ENUM">RLD2_DRIVE_IMPEDENCE_INTERNAL_50</parameter>
+ <parameter name="MEM_RLD2_ODT_MODE_ENUM" value="RLD2_ODT_ON" />
+ <parameter name="MEM_RLD2_REFRESH_INTERVAL_US" value="0.24" />
+ <parameter name="MEM_RLD2_SPEEDBIN_ENUM" value="RLD2_SPEEDBIN_18" />
+ <parameter name="MEM_RLD2_TAH_NS" value="0.3" />
+ <parameter name="MEM_RLD2_TAS_NS" value="0.3" />
+ <parameter name="MEM_RLD2_TCKDK_MAX_NS" value="0.3" />
+ <parameter name="MEM_RLD2_TCKDK_MIN_NS" value="-0.3" />
+ <parameter name="MEM_RLD2_TCKH_CYC" value="0.45" />
+ <parameter name="MEM_RLD2_TCKQK_MAX_NS" value="0.2" />
+ <parameter name="MEM_RLD2_TDH_NS" value="0.17" />
+ <parameter name="MEM_RLD2_TDS_NS" value="0.17" />
+ <parameter name="MEM_RLD2_TQKH_HCYC" value="0.9" />
+ <parameter name="MEM_RLD2_TQKQ_MAX_NS" value="0.12" />
+ <parameter name="MEM_RLD2_TQKQ_MIN_NS" value="-0.12" />
+ <parameter name="MEM_RLD2_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_ADDR_WIDTH" value="20" />
+ <parameter name="MEM_RLD3_AREF_PROTOCOL_ENUM" value="RLD3_AREF_BAC" />
+ <parameter name="MEM_RLD3_BANK_ADDR_WIDTH" value="4" />
+ <parameter name="MEM_RLD3_BL" value="2" />
+ <parameter name="MEM_RLD3_DATA_LATENCY_MODE_ENUM" value="RLD3_DL_RL16_WL17" />
+ <parameter name="MEM_RLD3_DEPTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_DM_EN" value="true" />
+ <parameter name="MEM_RLD3_DQ_PER_DEVICE" value="36" />
+ <parameter name="MEM_RLD3_ODT_MODE_ENUM" value="RLD3_ODT_40" />
+ <parameter name="MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM">RLD3_OUTPUT_DRIVE_40</parameter>
+ <parameter name="MEM_RLD3_SPEEDBIN_ENUM" value="RLD3_SPEEDBIN_093E" />
+ <parameter name="MEM_RLD3_TCKDK_MAX_CYC" value="0.27" />
+ <parameter name="MEM_RLD3_TCKDK_MIN_CYC" value="-0.27" />
+ <parameter name="MEM_RLD3_TCKQK_MAX_PS" value="135" />
+ <parameter name="MEM_RLD3_TDH_DC_MV" value="100" />
+ <parameter name="MEM_RLD3_TDH_PS" value="5" />
+ <parameter name="MEM_RLD3_TDS_AC_MV" value="150" />
+ <parameter name="MEM_RLD3_TDS_PS" value="-30" />
+ <parameter name="MEM_RLD3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_RLD3_TIH_PS" value="65" />
+ <parameter name="MEM_RLD3_TIS_AC_MV" value="150" />
+ <parameter name="MEM_RLD3_TIS_PS" value="85" />
+ <parameter name="MEM_RLD3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_RLD3_TQKQ_MAX_PS" value="75" />
+ <parameter name="MEM_RLD3_T_RC_MODE_ENUM" value="RLD3_TRC_9" />
+ <parameter name="MEM_RLD3_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_WRITE_PROTOCOL_ENUM" value="RLD3_WRITE_1BANK" />
+ <parameter name="PHY_DDR3_CAL_ADDR0" value="0" />
+ <parameter name="PHY_DDR3_CAL_ADDR1" value="8" />
+ <parameter name="PHY_DDR3_CAL_ENABLE_NON_DES" value="true" />
+ <parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_DDR3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_DDR3_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_DDR3_IO_VOLTAGE" value="1.5" />
+ <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_DDR3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_DDR3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_DDR4_DEFAULT_IO" value="false" />
+ <parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="false" />
+ <parameter name="PHY_DDR4_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="1000.0" />
+ <parameter name="PHY_DDR4_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_DDR4_STARTING_VREFIN" value="68.0" />
+ <parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="IO_STD_SSTL_12" />
+ <parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="OUT_OCT_40_CAL" />
+ <parameter name="PHY_DDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="IO_STD_SSTL_12" />
+ <parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="OUT_OCT_40_CAL" />
+ <parameter name="PHY_DDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="IN_OCT_120_CAL" />
+ <parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="IO_STD_POD_12" />
+ <parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="OUT_OCT_34_CAL" />
+ <parameter name="PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_DDR4_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="IO_STD_CMOS_12" />
+ <parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="25.0" />
+ <parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="IO_STD_CMOS_12" />
+ <parameter name="PHY_LPDDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_LPDDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_LPDDR3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_LPDDR3_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_LPDDR3_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_LPDDR3_MEM_CLK_FREQ_MHZ" value="800.0" />
+ <parameter name="PHY_LPDDR3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_LPDDR3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_LPDDR3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_LPDDR3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_LPDDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_LPDDR3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_LPDDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_QDR2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_QDR2_DEFAULT_IO" value="true" />
+ <parameter name="PHY_QDR2_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_QDR2_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_QDR2_IO_VOLTAGE" value="1.5" />
+ <parameter name="PHY_QDR2_MEM_CLK_FREQ_MHZ" value="633.333" />
+ <parameter name="PHY_QDR2_RATE_ENUM" value="RATE_HALF" />
+ <parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_QDR2_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_QDR2_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_QDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_QDR4_DEFAULT_IO" value="true" />
+ <parameter name="PHY_QDR4_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_QDR4_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_QDR4_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_QDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_QDR4_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_QDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR4_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_QDR4_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR4_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_QDR4_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_QDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_RLD2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_RLD2_DEFAULT_IO" value="true" />
+ <parameter name="PHY_RLD2_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_RLD2_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_RLD2_IO_VOLTAGE" value="1.8" />
+ <parameter name="PHY_RLD2_MEM_CLK_FREQ_MHZ" value="533.333" />
+ <parameter name="PHY_RLD2_RATE_ENUM" value="RATE_HALF" />
+ <parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_RLD2_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_RLD2_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_CONFIG_ENUM" value="CONFIG_PHY_ONLY" />
+ <parameter name="PHY_RLD3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_RLD3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_RLD3_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_RLD3_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_RLD3_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_RLD3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_RLD3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_RLD3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PLL_ADD_EXTRA_CLKS" value="0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8" value="0" />
+ <parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
+ <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
+ <parameter name="SHORT_QSYS_INTERFACE_NAMES" value="true" />
+ <parameter name="SYS_INFO_DEVICE" value="10AX115S2F45E1SG" />
+ <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="1" />
+ <parameter name="SYS_INFO_UNIQUE_ID">ip_arria10_e1sg_ddr4_4g_2000_emif_0</parameter>
+ <parameter name="TRAIT_SUPPORTS_VID" value="0" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7999771512bdcf2d6865c503a905d6e0c248bf60
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
@@ -0,0 +1,33 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generated/sim"
+
+# Copy ROM/RAM files to simulation directory
+if {[file isdirectory $IP_DIR]} {
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_151_4thorvi_seq_cal_sim.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_151_4thorvi_seq_cal_synth.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_151_4thorvi_seq_params_sim.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_151_4thorvi_seq_params_synth.hex ./
+}
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..cf24b8c0fc07ed16ecd535e3207b97793ffa5e4b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/generate_ip.sh
@@ -0,0 +1,54 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_ddr4_8g_1600.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
+
+# Also generate the testbench IP, this is not useful because it only generates bus functional models, so not a DDR4 memory model
+#qsys-generate ip_arria10_e1sg_ddr4_8g_1600.qsys \
+# --synthesis=VHDL \
+# --simulation=VHDL \
+# --testbench=STANDARD \
+# --testbench-simulation=VHDL \
+# --output-directory=generated \
+# --allow-mixed-language-simulation \
+# --allow-mixed-language-testbench-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..5944db188699984646b4f5615d7d5f79e684d46f
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_ddr4_8g_1600
+hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_1600_altera_emif_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_ddr4_8g_1600.qip
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qsys b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..d19120978d76a3b61e7d4cf40b251de56be2e988
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qsys
@@ -0,0 +1,1207 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_ddr4_8g_1600">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element emif_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>ctrl_amm_0</key>
+ <value>
+ <connectionPointName>ctrl_amm_0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='ctrl_amm_0' start='0x0' end='0x240000000' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>34</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>576</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>ctrl_mmr_slave_0</key>
+ <value>
+ <connectionPointName>ctrl_mmr_slave_0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='ctrl_mmr_slave_0' start='0x0' end='0x1000' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>12</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>emif_usr_clk</key>
+ <value>
+ <connectionPointName>emif_usr_clk</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>200000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="ctrl_amm_0"
+ internal="emif_0.ctrl_amm_0"
+ type="avalon"
+ dir="end">
+ <port name="amm_address_0" internal="amm_address_0" />
+ <port name="amm_burstcount_0" internal="amm_burstcount_0" />
+ <port name="amm_byteenable_0" internal="amm_byteenable_0" />
+ <port name="amm_read_0" internal="amm_read_0" />
+ <port name="amm_readdata_0" internal="amm_readdata_0" />
+ <port name="amm_readdatavalid_0" internal="amm_readdatavalid_0" />
+ <port name="amm_ready_0" internal="amm_ready_0" />
+ <port name="amm_write_0" internal="amm_write_0" />
+ <port name="amm_writedata_0" internal="amm_writedata_0" />
+ </interface>
+ <interface
+ name="ctrl_mmr_slave_0"
+ internal="emif_0.ctrl_mmr_slave_0"
+ type="avalon"
+ dir="end">
+ <port name="mmr_slave_address_0" internal="mmr_slave_address_0" />
+ <port
+ name="mmr_slave_beginbursttransfer_0"
+ internal="mmr_slave_beginbursttransfer_0" />
+ <port name="mmr_slave_burstcount_0" internal="mmr_slave_burstcount_0" />
+ <port name="mmr_slave_read_0" internal="mmr_slave_read_0" />
+ <port name="mmr_slave_readdata_0" internal="mmr_slave_readdata_0" />
+ <port name="mmr_slave_readdatavalid_0" internal="mmr_slave_readdatavalid_0" />
+ <port name="mmr_slave_waitrequest_0" internal="mmr_slave_waitrequest_0" />
+ <port name="mmr_slave_write_0" internal="mmr_slave_write_0" />
+ <port name="mmr_slave_writedata_0" internal="mmr_slave_writedata_0" />
+ </interface>
+ <interface
+ name="emif_usr_clk"
+ internal="emif_0.emif_usr_clk"
+ type="clock"
+ dir="start">
+ <port name="emif_usr_clk" internal="emif_usr_clk" />
+ </interface>
+ <interface
+ name="emif_usr_reset_n"
+ internal="emif_0.emif_usr_reset_n"
+ type="reset"
+ dir="start">
+ <port name="emif_usr_reset_n" internal="emif_usr_reset_n" />
+ </interface>
+ <interface
+ name="global_reset_n"
+ internal="emif_0.global_reset_n"
+ type="reset"
+ dir="end">
+ <port name="global_reset_n" internal="global_reset_n" />
+ </interface>
+ <interface name="mem" internal="emif_0.mem" type="conduit" dir="end">
+ <port name="mem_a" internal="mem_a" />
+ <port name="mem_act_n" internal="mem_act_n" />
+ <port name="mem_alert_n" internal="mem_alert_n" />
+ <port name="mem_ba" internal="mem_ba" />
+ <port name="mem_bg" internal="mem_bg" />
+ <port name="mem_ck" internal="mem_ck" />
+ <port name="mem_ck_n" internal="mem_ck_n" />
+ <port name="mem_cke" internal="mem_cke" />
+ <port name="mem_cs_n" internal="mem_cs_n" />
+ <port name="mem_dbi_n" internal="mem_dbi_n" />
+ <port name="mem_dq" internal="mem_dq" />
+ <port name="mem_dqs" internal="mem_dqs" />
+ <port name="mem_dqs_n" internal="mem_dqs_n" />
+ <port name="mem_odt" internal="mem_odt" />
+ <port name="mem_par" internal="mem_par" />
+ <port name="mem_reset_n" internal="mem_reset_n" />
+ </interface>
+ <interface name="oct" internal="emif_0.oct" type="conduit" dir="end">
+ <port name="oct_rzqin" internal="oct_rzqin" />
+ </interface>
+ <interface
+ name="pll_ref_clk"
+ internal="emif_0.pll_ref_clk"
+ type="clock"
+ dir="end">
+ <port name="pll_ref_clk" internal="pll_ref_clk" />
+ </interface>
+ <interface name="status" internal="emif_0.status" type="conduit" dir="end">
+ <port name="local_cal_fail" internal="local_cal_fail" />
+ <port name="local_cal_success" internal="local_cal_success" />
+ </interface>
+ <module
+ name="emif_0"
+ kind="altera_emif"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR3_MAX_DQS_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_DDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR3_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR3_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_RCLK_SLEW_RATE" value="5.0" />
+ <parameter name="BOARD_DDR3_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_RDATA_SLEW_RATE" value="2.5" />
+ <parameter name="BOARD_DDR3_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR3_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_DDR3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="5.0E-4" />
+ <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.0055" />
+ <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.006" />
+ <parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="-0.2285" />
+ <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.231" />
+ <parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.291" />
+ <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.072" />
+ <parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.137" />
+ <parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="1.16" />
+ <parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="2.43" />
+ <parameter name="BOARD_DDR4_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="3.7" />
+ <parameter name="BOARD_DDR4_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="2.2" />
+ <parameter name="BOARD_DDR4_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_WCLK_SLEW_RATE" value="3.7" />
+ <parameter name="BOARD_DDR4_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.16" />
+ <parameter name="BOARD_DDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_DDR4_USE_DEFAULT_SLEW_RATES" value="false" />
+ <parameter name="BOARD_LPDDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+ <parameter name="BOARD_LPDDR3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_LPDDR3_MAX_DQS_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_LPDDR3_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_LPDDR3_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_LPDDR3_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_RDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_LPDDR3_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_LPDDR3_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_QDR2_AC_TO_K_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR2_MAX_K_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_K_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR2_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR2_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_RDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_QDR2_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_QDR4_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_DK_TO_CK_SKEW_NS" value="-0.02" />
+ <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR4_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR4_MAX_DK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_QDR4_SKEW_BETWEEN_DK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR4_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_RCLK_SLEW_RATE" value="5.0" />
+ <parameter name="BOARD_QDR4_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_RDATA_SLEW_RATE" value="2.5" />
+ <parameter name="BOARD_QDR4_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_QDR4_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_RLD3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_DK_TO_CK_SKEW_NS" value="-0.02" />
+ <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+ <parameter name="BOARD_RLD3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_RLD3_MAX_DK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_RLD3_SKEW_BETWEEN_DK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_RLD3_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_RCLK_SLEW_RATE" value="7.0" />
+ <parameter name="BOARD_RLD3_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_RDATA_SLEW_RATE" value="3.5" />
+ <parameter name="BOARD_RLD3_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="CAL_DEBUG_CLOCK_FREQUENCY" value="50000000" />
+ <parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_DDR3_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_DDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_DDR3_ECC_AUTO_CORRECTION_EN" value="false" />
+ <parameter name="CTRL_DDR3_ECC_EN" value="false" />
+ <parameter name="CTRL_DDR3_MMR_EN" value="false" />
+ <parameter name="CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_REORDER_EN" value="true" />
+ <parameter name="CTRL_DDR3_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR3_STARVE_LIMIT" value="10" />
+ <parameter name="CTRL_DDR3_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_DDR3_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_ADDR_ORDER_ENUM">DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG</parameter>
+ <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_DDR4_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_DDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_DDR4_ECC_AUTO_CORRECTION_EN" value="false" />
+ <parameter name="CTRL_DDR4_ECC_EN" value="false" />
+ <parameter name="CTRL_DDR4_MMR_EN" value="true" />
+ <parameter name="CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_REORDER_EN" value="true" />
+ <parameter name="CTRL_DDR4_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR4_STARVE_LIMIT" value="10" />
+ <parameter name="CTRL_DDR4_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_DDR4_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_ADDR_ORDER_ENUM">LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_LPDDR3_MMR_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_REORDER_EN" value="true" />
+ <parameter name="CTRL_LPDDR3_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_STARVE_LIMIT" value="10" />
+ <parameter name="CTRL_LPDDR3_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+ <parameter name="CTRL_QDR2_AVL_MAX_BURST_COUNT" value="4" />
+ <parameter name="CTRL_QDR2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC" value="0" />
+ <parameter name="CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC" value="0" />
+ <parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+ <parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
+ <parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
+ <parameter name="DIAG_DDR3_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_DDR3_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_DDR3_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_DDR3_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_DDR3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_DDR3_CAL_ADDR0" value="0" />
+ <parameter name="DIAG_DDR3_CAL_ADDR1" value="8" />
+ <parameter name="DIAG_DDR3_CAL_ENABLE_NON_DES" value="false" />
+ <parameter name="DIAG_DDR3_CAL_FULL_CAL_ON_RESET" value="true" />
+ <parameter name="DIAG_DDR3_CA_LEVEL_EN" value="false" />
+ <parameter name="DIAG_DDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR3_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_DDR3_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR3_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR3_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_DDR4_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_DDR4_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_DDR4_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_DDR4_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_DDR4_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_DDR4_CAL_ADDR0" value="0" />
+ <parameter name="DIAG_DDR4_CAL_ADDR1" value="8" />
+ <parameter name="DIAG_DDR4_CAL_ENABLE_NON_DES" value="false" />
+ <parameter name="DIAG_DDR4_CAL_FULL_CAL_ON_RESET" value="true" />
+ <parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_JTAG</parameter>
+ <parameter name="DIAG_DDR4_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_DDR4_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
+ <parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="false" />
+ <parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="true" />
+ <parameter name="DIAG_DDR4_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR4_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR4_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
+ <parameter name="DIAG_ENABLE_HPS_EMIF_DEBUG" value="false" />
+ <parameter name="DIAG_ENABLE_JTAG_UART" value="false" />
+ <parameter name="DIAG_ENABLE_JTAG_UART_HEX" value="false" />
+ <parameter name="DIAG_EXPORT_VJI" value="false" />
+ <parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
+ <parameter name="DIAG_EXTRA_CONFIGS" value="" />
+ <parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
+ <parameter name="DIAG_EX_DESIGN_SEPARATE_RESETS" value="false" />
+ <parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
+ <parameter name="DIAG_LPDDR3_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_LPDDR3_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_LPDDR3_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_LPDDR3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_LPDDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_LPDDR3_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_LPDDR3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_LPDDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_LPDDR3_SKIP_CA_DESKEW" value="false" />
+ <parameter name="DIAG_LPDDR3_SKIP_CA_LEVEL" value="false" />
+ <parameter name="DIAG_LPDDR3_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_LPDDR3_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_LPDDR3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_QDR2_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_QDR2_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_QDR2_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_QDR2_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_QDR2_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_QDR2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR2_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_QDR2_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR2_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR2_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR2_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_QDR4_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_QDR4_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_QDR4_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_QDR4_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_QDR4_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_QDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR4_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_QDR4_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR4_SKIP_VREF_CAL" value="false" />
+ <parameter name="DIAG_QDR4_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR4_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR4_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RLD2_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_RLD2_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_RLD2_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_RLD2_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_RLD2_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_RLD2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD2_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_RLD2_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD2_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD2_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD2_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RLD3_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_RLD3_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_RLD3_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_RLD3_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_RLD3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_RLD3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD3_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_RLD3_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD3_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD3_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RS232_UART_BAUDRATE" value="57600" />
+ <parameter name="DIAG_SIM_REGTEST_MODE" value="false" />
+ <parameter name="DIAG_SOFT_NIOS_CLOCK_FREQUENCY" value="100" />
+ <parameter name="DIAG_SOFT_NIOS_MODE">SOFT_NIOS_MODE_DISABLED</parameter>
+ <parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
+ <parameter name="DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE" value="false" />
+ <parameter name="DIAG_TG_AVL_2_NUM_CFG_INTERFACES" value="0" />
+ <parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
+ <parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
+ <parameter name="DIAG_USE_RS232_UART" value="false" />
+ <parameter name="DIAG_VERBOSE_IOAUX" value="false" />
+ <parameter name="EX_DESIGN_GUI_DDR3_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR3_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_DDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_DDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_DDR4_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR4_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_DDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_DDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter
+ name="EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT"
+ value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR2_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR2_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_QDR2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR4_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR4_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_QDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD2_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD2_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_RLD2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD3_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD3_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_RLD3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="INTERNAL_TESTING_MODE" value="false" />
+ <parameter name="IS_ED_SLAVE" value="false" />
+ <parameter name="MEM_DDR3_ALERT_N_DQS_GROUP" value="0" />
+ <parameter name="MEM_DDR3_ALERT_N_PLACEMENT_ENUM">DDR3_ALERT_N_PLACEMENT_AC_LANES</parameter>
+ <parameter name="MEM_DDR3_ASR_ENUM" value="DDR3_ASR_MANUAL" />
+ <parameter name="MEM_DDR3_ATCL_ENUM" value="DDR3_ATCL_DISABLED" />
+ <parameter name="MEM_DDR3_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_DDR3_BL_ENUM" value="DDR3_BL_BL8" />
+ <parameter name="MEM_DDR3_BT_ENUM" value="DDR3_BT_SEQUENTIAL" />
+ <parameter name="MEM_DDR3_CKE_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR3_CK_WIDTH" value="1" />
+ <parameter name="MEM_DDR3_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_DDR3_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR3_DLL_EN" value="true" />
+ <parameter name="MEM_DDR3_DM_EN" value="true" />
+ <parameter name="MEM_DDR3_DQ_PER_DQS" value="8" />
+ <parameter name="MEM_DDR3_DQ_WIDTH" value="72" />
+ <parameter name="MEM_DDR3_DRV_STR_ENUM" value="DDR3_DRV_STR_RZQ_7" />
+ <parameter name="MEM_DDR3_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
+ <parameter name="MEM_DDR3_HIDE_ADV_MR_SETTINGS" value="true" />
+ <parameter name="MEM_DDR3_LRDIMM_EXTENDED_CONFIG" value="000000000000000000" />
+ <parameter name="MEM_DDR3_MIRROR_ADDRESSING_EN" value="true" />
+ <parameter name="MEM_DDR3_NUM_OF_DIMMS" value="1" />
+ <parameter name="MEM_DDR3_PD_ENUM" value="DDR3_PD_OFF" />
+ <parameter name="MEM_DDR3_RANKS_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR3_RDIMM_CONFIG" value="0000000000000000" />
+ <parameter name="MEM_DDR3_ROW_ADDR_WIDTH" value="15" />
+ <parameter name="MEM_DDR3_RTT_NOM_ENUM">DDR3_RTT_NOM_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR3_RTT_WR_ENUM" value="DDR3_RTT_WR_RZQ_4" />
+ <parameter name="MEM_DDR3_R_ODT0_1X1" value="off" />
+ <parameter name="MEM_DDR3_R_ODT0_2X2" value="off,off" />
+ <parameter name="MEM_DDR3_R_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_R_ODT0_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR3_R_ODT1_2X2" value="off,off" />
+ <parameter name="MEM_DDR3_R_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_R_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_R_ODT2_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR3_R_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR3_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_SPEEDBIN_ENUM" value="DDR3_SPEEDBIN_2133" />
+ <parameter name="MEM_DDR3_SRT_ENUM" value="DDR3_SRT_NORMAL" />
+ <parameter name="MEM_DDR3_TCL" value="14" />
+ <parameter name="MEM_DDR3_TDH_DC_MV" value="100" />
+ <parameter name="MEM_DDR3_TDH_PS" value="55" />
+ <parameter name="MEM_DDR3_TDQSCK_PS" value="180" />
+ <parameter name="MEM_DDR3_TDQSQ_PS" value="75" />
+ <parameter name="MEM_DDR3_TDQSS_CYC" value="0.27" />
+ <parameter name="MEM_DDR3_TDSH_CYC" value="0.18" />
+ <parameter name="MEM_DDR3_TDSS_CYC" value="0.18" />
+ <parameter name="MEM_DDR3_TDS_AC_MV" value="135" />
+ <parameter name="MEM_DDR3_TDS_PS" value="53" />
+ <parameter name="MEM_DDR3_TFAW_NS" value="25.0" />
+ <parameter name="MEM_DDR3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_DDR3_TIH_PS" value="95" />
+ <parameter name="MEM_DDR3_TINIT_US" value="500" />
+ <parameter name="MEM_DDR3_TIS_AC_MV" value="135" />
+ <parameter name="MEM_DDR3_TIS_PS" value="60" />
+ <parameter name="MEM_DDR3_TMRD_CK_CYC" value="4" />
+ <parameter name="MEM_DDR3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_DDR3_TQSH_CYC" value="0.4" />
+ <parameter name="MEM_DDR3_TRAS_NS" value="33.0" />
+ <parameter name="MEM_DDR3_TRCD_NS" value="13.09" />
+ <parameter name="MEM_DDR3_TREFI_US" value="7.8" />
+ <parameter name="MEM_DDR3_TRFC_NS" value="160.0" />
+ <parameter name="MEM_DDR3_TRP_NS" value="13.09" />
+ <parameter name="MEM_DDR3_TRRD_CYC" value="6" />
+ <parameter name="MEM_DDR3_TRTP_CYC" value="8" />
+ <parameter name="MEM_DDR3_TWLH_PS" value="125.0" />
+ <parameter name="MEM_DDR3_TWLS_PS" value="125.0" />
+ <parameter name="MEM_DDR3_TWR_NS" value="15.0" />
+ <parameter name="MEM_DDR3_TWTR_CYC" value="8" />
+ <parameter name="MEM_DDR3_USE_DEFAULT_ODT" value="true" />
+ <parameter name="MEM_DDR3_WTCL" value="10" />
+ <parameter name="MEM_DDR3_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR3_W_ODT0_2X2" value="on,off" />
+ <parameter name="MEM_DDR3_W_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT0_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODT1_2X2" value="off,on" />
+ <parameter name="MEM_DDR3_W_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT2_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR3_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_AC_PARITY_LATENCY">DDR4_AC_PARITY_LATENCY_DISABLE</parameter>
+ <parameter name="MEM_DDR4_AC_PERSISTENT_ERROR" value="false" />
+ <parameter name="MEM_DDR4_ALERT_N_AC_LANE" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_AC_PIN" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_DQS_GROUP" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_PLACEMENT_ENUM">DDR4_ALERT_N_PLACEMENT_DATA_LANES</parameter>
+ <parameter name="MEM_DDR4_ALERT_PAR_EN" value="true" />
+ <parameter name="MEM_DDR4_ASR_ENUM">DDR4_ASR_MANUAL_NORMAL</parameter>
+ <parameter name="MEM_DDR4_ATCL_ENUM" value="DDR4_ATCL_DISABLED" />
+ <parameter name="MEM_DDR4_BANK_ADDR_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_BANK_GROUP_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_BL_ENUM" value="DDR4_BL_BL8" />
+ <parameter name="MEM_DDR4_BT_ENUM" value="DDR4_BT_SEQUENTIAL" />
+ <parameter name="MEM_DDR4_CAL_MODE" value="0" />
+ <parameter name="MEM_DDR4_CHIP_ID_WIDTH" value="0" />
+ <parameter name="MEM_DDR4_CKE_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR4_CK_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_DDR4_DB_DQ_DRV_ENUM">DDR4_DB_DRV_STR_RZQ_7</parameter>
+ <parameter name="MEM_DDR4_DB_RTT_NOM_ENUM">DDR4_DB_RTT_NOM_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_DB_RTT_PARK_ENUM">DDR4_DB_RTT_PARK_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_DB_RTT_WR_ENUM">DDR4_DB_RTT_WR_RZQ_3</parameter>
+ <parameter name="MEM_DDR4_DEFAULT_VREFOUT" value="false" />
+ <parameter name="MEM_DDR4_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR4_DLL_EN" value="true" />
+ <parameter name="MEM_DDR4_DM_EN" value="true" />
+ <parameter name="MEM_DDR4_DQ_PER_DQS" value="8" />
+ <parameter name="MEM_DDR4_DQ_WIDTH" value="72" />
+ <parameter name="MEM_DDR4_DRV_STR_ENUM" value="DDR4_DRV_STR_RZQ_7" />
+ <parameter name="MEM_DDR4_FINE_GRANULARITY_REFRESH">DDR4_FINE_REFRESH_FIXED_1X</parameter>
+ <parameter name="MEM_DDR4_FORMAT_ENUM" value="MEM_FORMAT_SODIMM" />
+ <parameter name="MEM_DDR4_GEARDOWN" value="DDR4_GEARDOWN_HR" />
+ <parameter name="MEM_DDR4_HIDE_ADV_MR_SETTINGS" value="true" />
+ <parameter name="MEM_DDR4_INTERNAL_VREFDQ_MONITOR" value="false" />
+ <parameter name="MEM_DDR4_LRDIMM_ODT_LESS_BS" value="true" />
+ <parameter name="MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM" value="240" />
+ <parameter name="MEM_DDR4_LRDIMM_VREFDQ_VALUE" value="1D" />
+ <parameter name="MEM_DDR4_MAX_POWERDOWN" value="false" />
+ <parameter name="MEM_DDR4_MIRROR_ADDRESSING_EN" value="true" />
+ <parameter name="MEM_DDR4_MPR_READ_FORMAT">DDR4_MPR_READ_FORMAT_SERIAL</parameter>
+ <parameter name="MEM_DDR4_NUM_OF_DIMMS" value="1" />
+ <parameter name="MEM_DDR4_ODT_IN_POWERDOWN" value="true" />
+ <parameter name="MEM_DDR4_PER_DRAM_ADDR" value="false" />
+ <parameter name="MEM_DDR4_RANKS_PER_DIMM" value="2" />
+ <parameter name="MEM_DDR4_RCD_CA_IBT_ENUM" value="DDR4_RCD_CA_IBT_100" />
+ <parameter name="MEM_DDR4_RCD_CKE_IBT_ENUM">DDR4_RCD_CKE_IBT_100</parameter>
+ <parameter name="MEM_DDR4_RCD_CS_IBT_ENUM" value="DDR4_RCD_CS_IBT_100" />
+ <parameter name="MEM_DDR4_RCD_ODT_IBT_ENUM">DDR4_RCD_ODT_IBT_100</parameter>
+ <parameter name="MEM_DDR4_READ_DBI" value="false" />
+ <parameter name="MEM_DDR4_READ_PREAMBLE" value="2" />
+ <parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
+ <parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
+ <parameter name="MEM_DDR4_RTT_NOM_ENUM" value="DDR4_RTT_NOM_RZQ_4" />
+ <parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_RTT_WR_ENUM">DDR4_RTT_WR_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_R_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR4_R_ODT0_2X2" value="on,off" />
+ <parameter name="MEM_DDR4_R_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_R_ODT0_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR4_R_ODT1_2X2" value="off,on" />
+ <parameter name="MEM_DDR4_R_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_R_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_R_ODT2_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR4_R_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR4_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR4_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_SELF_RFSH_ABORT" value="false" />
+ <parameter name="MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB" value="0" />
+ <parameter name="MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB" value="0" />
+ <parameter name="MEM_DDR4_SPD_135_RCD_REV" value="0" />
+ <parameter name="MEM_DDR4_SPD_137_RCD_CA_DRV" value="101" />
+ <parameter name="MEM_DDR4_SPD_138_RCD_CK_DRV" value="5" />
+ <parameter name="MEM_DDR4_SPD_139_DB_REV" value="0" />
+ <parameter name="MEM_DDR4_SPD_140_DRAM_VREFDQ_R0" value="29" />
+ <parameter name="MEM_DDR4_SPD_141_DRAM_VREFDQ_R1" value="29" />
+ <parameter name="MEM_DDR4_SPD_142_DRAM_VREFDQ_R2" value="29" />
+ <parameter name="MEM_DDR4_SPD_143_DRAM_VREFDQ_R3" value="29" />
+ <parameter name="MEM_DDR4_SPD_144_DB_VREFDQ" value="37" />
+ <parameter name="MEM_DDR4_SPD_145_DB_MDQ_DRV" value="21" />
+ <parameter name="MEM_DDR4_SPD_148_DRAM_DRV" value="0" />
+ <parameter name="MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM" value="20" />
+ <parameter name="MEM_DDR4_SPD_152_DRAM_RTT_PARK" value="39" />
+ <parameter name="MEM_DDR4_SPEEDBIN_ENUM" value="DDR4_SPEEDBIN_2133" />
+ <parameter name="MEM_DDR4_TCCD_L_CYC" value="5" />
+ <parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
+ <parameter name="MEM_DDR4_TCL" value="11" />
+ <parameter name="MEM_DDR4_TDIVW_DJ_CYC" value="0.1" />
+ <parameter name="MEM_DDR4_TDIVW_TOTAL_UI" value="0.1" />
+ <parameter name="MEM_DDR4_TDQSCK_PS" value="170" />
+ <parameter name="MEM_DDR4_TDQSQ_PS" value="66" />
+ <parameter name="MEM_DDR4_TDQSQ_UI" value="0.16" />
+ <parameter name="MEM_DDR4_TDQSS_CYC" value="0.27" />
+ <parameter name="MEM_DDR4_TDSH_CYC" value="0.18" />
+ <parameter name="MEM_DDR4_TDSS_CYC" value="0.18" />
+ <parameter name="MEM_DDR4_TDVWP_UI" value="0.72" />
+ <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA" value="false" />
+ <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
+ <parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
+ <parameter name="MEM_DDR4_TFAW_NS" value="21.0" />
+ <parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
+ <parameter name="MEM_DDR4_TIH_PS" value="105" />
+ <parameter name="MEM_DDR4_TINIT_US" value="500" />
+ <parameter name="MEM_DDR4_TIS_AC_MV" value="100" />
+ <parameter name="MEM_DDR4_TIS_PS" value="80" />
+ <parameter name="MEM_DDR4_TMRD_CK_CYC" value="8" />
+ <parameter name="MEM_DDR4_TQH_CYC" value="0.38" />
+ <parameter name="MEM_DDR4_TQH_UI" value="0.76" />
+ <parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
+ <parameter name="MEM_DDR4_TRAS_NS" value="33.0" />
+ <parameter name="MEM_DDR4_TRCD_NS" value="14.06" />
+ <parameter name="MEM_DDR4_TREFI_US" value="7.8" />
+ <parameter name="MEM_DDR4_TRFC_NS" value="260.0" />
+ <parameter name="MEM_DDR4_TRP_NS" value="14.06" />
+ <parameter name="MEM_DDR4_TRRD_L_CYC" value="5" />
+ <parameter name="MEM_DDR4_TRRD_S_CYC" value="3" />
+ <parameter name="MEM_DDR4_TWLH_PS" value="185.7" />
+ <parameter name="MEM_DDR4_TWLS_PS" value="185.7" />
+ <parameter name="MEM_DDR4_TWR_NS" value="15.0" />
+ <parameter name="MEM_DDR4_TWTR_L_CYC" value="6" />
+ <parameter name="MEM_DDR4_TWTR_S_CYC" value="2" />
+ <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_1</parameter>
+ <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_VALUE" value="68.0" />
+ <parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="false" />
+ <parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
+ <parameter name="MEM_DDR4_WRITE_CRC" value="false" />
+ <parameter name="MEM_DDR4_WRITE_DBI" value="false" />
+ <parameter name="MEM_DDR4_WRITE_PREAMBLE" value="1" />
+ <parameter name="MEM_DDR4_WTCL" value="9" />
+ <parameter name="MEM_DDR4_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR4_W_ODT0_2X2" value="on,off" />
+ <parameter name="MEM_DDR4_W_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT0_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODT1_2X2" value="off,on" />
+ <parameter name="MEM_DDR4_W_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT2_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR4_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR4_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_LPDDR3_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_LPDDR3_BL" value="LPDDR3_BL_BL8" />
+ <parameter name="MEM_LPDDR3_CK_WIDTH" value="1" />
+ <parameter name="MEM_LPDDR3_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_LPDDR3_DATA_LATENCY" value="LPDDR3_DL_RL12_WL6" />
+ <parameter name="MEM_LPDDR3_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_LPDDR3_DM_EN" value="true" />
+ <parameter name="MEM_LPDDR3_DQODT">LPDDR3_DQODT_DISABLE</parameter>
+ <parameter name="MEM_LPDDR3_DQ_WIDTH" value="32" />
+ <parameter name="MEM_LPDDR3_DRV_STR">LPDDR3_DRV_STR_40D_40U</parameter>
+ <parameter name="MEM_LPDDR3_NWR" value="LPDDR3_NWR_NWR10" />
+ <parameter name="MEM_LPDDR3_PDODT">LPDDR3_PDODT_DISABLED</parameter>
+ <parameter name="MEM_LPDDR3_ROW_ADDR_WIDTH" value="15" />
+ <parameter name="MEM_LPDDR3_R_ODT0_1X1" value="off" />
+ <parameter name="MEM_LPDDR3_R_ODT0_2X2" value="off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT0_4X4" value="off,off,on,on" />
+ <parameter name="MEM_LPDDR3_R_ODT1_2X2" value="off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT1_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT2_4X4" value="on,on,off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT3_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_LPDDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_LPDDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_LPDDR3_SPEEDBIN_ENUM">LPDDR3_SPEEDBIN_1600</parameter>
+ <parameter name="MEM_LPDDR3_TDH_DC_MV" value="100" />
+ <parameter name="MEM_LPDDR3_TDH_PS" value="100" />
+ <parameter name="MEM_LPDDR3_TDQSCKDL" value="614" />
+ <parameter name="MEM_LPDDR3_TDQSQ_PS" value="135" />
+ <parameter name="MEM_LPDDR3_TDQSS_CYC" value="1.25" />
+ <parameter name="MEM_LPDDR3_TDSH_CYC" value="0.2" />
+ <parameter name="MEM_LPDDR3_TDSS_CYC" value="0.2" />
+ <parameter name="MEM_LPDDR3_TDS_AC_MV" value="150" />
+ <parameter name="MEM_LPDDR3_TDS_PS" value="75" />
+ <parameter name="MEM_LPDDR3_TFAW_NS" value="50.0" />
+ <parameter name="MEM_LPDDR3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_LPDDR3_TIH_PS" value="100" />
+ <parameter name="MEM_LPDDR3_TINIT_US" value="500" />
+ <parameter name="MEM_LPDDR3_TIS_AC_MV" value="150" />
+ <parameter name="MEM_LPDDR3_TIS_PS" value="75" />
+ <parameter name="MEM_LPDDR3_TMRR_CK_CYC" value="4" />
+ <parameter name="MEM_LPDDR3_TMRW_CK_CYC" value="10" />
+ <parameter name="MEM_LPDDR3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_LPDDR3_TQSH_CYC" value="0.38" />
+ <parameter name="MEM_LPDDR3_TRAS_NS" value="42.5" />
+ <parameter name="MEM_LPDDR3_TRCD_NS" value="18.75" />
+ <parameter name="MEM_LPDDR3_TREFI_US" value="3.9" />
+ <parameter name="MEM_LPDDR3_TRFC_NS" value="210.0" />
+ <parameter name="MEM_LPDDR3_TRP_NS" value="18.75" />
+ <parameter name="MEM_LPDDR3_TRRD_CYC" value="2" />
+ <parameter name="MEM_LPDDR3_TRTP_CYC" value="4" />
+ <parameter name="MEM_LPDDR3_TWLH_PS" value="175.0" />
+ <parameter name="MEM_LPDDR3_TWLS_PS" value="175.0" />
+ <parameter name="MEM_LPDDR3_TWR_NS" value="15.0" />
+ <parameter name="MEM_LPDDR3_TWTR_CYC" value="4" />
+ <parameter name="MEM_LPDDR3_USE_DEFAULT_ODT" value="true" />
+ <parameter name="MEM_LPDDR3_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_LPDDR3_W_ODT0_2X2" value="on,off" />
+ <parameter name="MEM_LPDDR3_W_ODT0_4X4" value="on,on,on,on" />
+ <parameter name="MEM_LPDDR3_W_ODT1_2X2" value="off,on" />
+ <parameter name="MEM_LPDDR3_W_ODT1_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_W_ODT2_4X4" value="on,on,on,on" />
+ <parameter name="MEM_LPDDR3_W_ODT3_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_LPDDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_LPDDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_QDR2_ADDR_WIDTH" value="19" />
+ <parameter name="MEM_QDR2_BL" value="4" />
+ <parameter name="MEM_QDR2_BWS_EN" value="true" />
+ <parameter name="MEM_QDR2_DATA_PER_DEVICE" value="36" />
+ <parameter name="MEM_QDR2_INTERNAL_JITTER_NS" value="0.08" />
+ <parameter name="MEM_QDR2_SPEEDBIN_ENUM" value="QDR2_SPEEDBIN_633" />
+ <parameter name="MEM_QDR2_TCCQO_NS" value="0.45" />
+ <parameter name="MEM_QDR2_TCQDOH_NS" value="-0.09" />
+ <parameter name="MEM_QDR2_TCQD_NS" value="0.09" />
+ <parameter name="MEM_QDR2_TCQH_NS" value="0.71" />
+ <parameter name="MEM_QDR2_THA_NS" value="0.18" />
+ <parameter name="MEM_QDR2_THD_NS" value="0.18" />
+ <parameter name="MEM_QDR2_TRL_CYC" value="2.5" />
+ <parameter name="MEM_QDR2_TSA_NS" value="0.23" />
+ <parameter name="MEM_QDR2_TSD_NS" value="0.23" />
+ <parameter name="MEM_QDR2_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_QDR4_AC_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_ADDR_INV_ENA" value="false" />
+ <parameter name="MEM_QDR4_ADDR_WIDTH" value="21" />
+ <parameter name="MEM_QDR4_CK_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_DATA_INV_ENA" value="false" />
+ <parameter name="MEM_QDR4_DATA_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_DQ_PER_PORT_PER_DEVICE" value="36" />
+ <parameter name="MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+ <parameter name="MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+ <parameter name="MEM_QDR4_SPEEDBIN_ENUM" value="QDR4_SPEEDBIN_2133" />
+ <parameter name="MEM_QDR4_TASH_PS" value="170" />
+ <parameter name="MEM_QDR4_TCKDK_MAX_PS" value="150" />
+ <parameter name="MEM_QDR4_TCKDK_MIN_PS" value="-150" />
+ <parameter name="MEM_QDR4_TCKQK_MAX_PS" value="225" />
+ <parameter name="MEM_QDR4_TCSH_PS" value="170" />
+ <parameter name="MEM_QDR4_TISH_PS" value="150" />
+ <parameter name="MEM_QDR4_TQH_CYC" value="0.4" />
+ <parameter name="MEM_QDR4_TQKQ_MAX_PS" value="75" />
+ <parameter name="MEM_QDR4_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD2_ADDR_WIDTH" value="21" />
+ <parameter name="MEM_RLD2_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_RLD2_BL" value="4" />
+ <parameter name="MEM_RLD2_CONFIG_ENUM">RLD2_CONFIG_TRC_8_TRL_8_TWL_9</parameter>
+ <parameter name="MEM_RLD2_DM_EN" value="true" />
+ <parameter name="MEM_RLD2_DQ_PER_DEVICE" value="9" />
+ <parameter name="MEM_RLD2_DRIVE_IMPEDENCE_ENUM">RLD2_DRIVE_IMPEDENCE_INTERNAL_50</parameter>
+ <parameter name="MEM_RLD2_ODT_MODE_ENUM" value="RLD2_ODT_ON" />
+ <parameter name="MEM_RLD2_REFRESH_INTERVAL_US" value="0.24" />
+ <parameter name="MEM_RLD2_SPEEDBIN_ENUM" value="RLD2_SPEEDBIN_18" />
+ <parameter name="MEM_RLD2_TAH_NS" value="0.3" />
+ <parameter name="MEM_RLD2_TAS_NS" value="0.3" />
+ <parameter name="MEM_RLD2_TCKDK_MAX_NS" value="0.3" />
+ <parameter name="MEM_RLD2_TCKDK_MIN_NS" value="-0.3" />
+ <parameter name="MEM_RLD2_TCKH_CYC" value="0.45" />
+ <parameter name="MEM_RLD2_TCKQK_MAX_NS" value="0.2" />
+ <parameter name="MEM_RLD2_TDH_NS" value="0.17" />
+ <parameter name="MEM_RLD2_TDS_NS" value="0.17" />
+ <parameter name="MEM_RLD2_TQKH_HCYC" value="0.9" />
+ <parameter name="MEM_RLD2_TQKQ_MAX_NS" value="0.12" />
+ <parameter name="MEM_RLD2_TQKQ_MIN_NS" value="-0.12" />
+ <parameter name="MEM_RLD2_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_ADDR_WIDTH" value="20" />
+ <parameter name="MEM_RLD3_AREF_PROTOCOL_ENUM" value="RLD3_AREF_BAC" />
+ <parameter name="MEM_RLD3_BANK_ADDR_WIDTH" value="4" />
+ <parameter name="MEM_RLD3_BL" value="2" />
+ <parameter name="MEM_RLD3_DATA_LATENCY_MODE_ENUM" value="RLD3_DL_RL16_WL17" />
+ <parameter name="MEM_RLD3_DEPTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_DM_EN" value="true" />
+ <parameter name="MEM_RLD3_DQ_PER_DEVICE" value="36" />
+ <parameter name="MEM_RLD3_ODT_MODE_ENUM" value="RLD3_ODT_40" />
+ <parameter name="MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM">RLD3_OUTPUT_DRIVE_40</parameter>
+ <parameter name="MEM_RLD3_SPEEDBIN_ENUM" value="RLD3_SPEEDBIN_093E" />
+ <parameter name="MEM_RLD3_TCKDK_MAX_CYC" value="0.27" />
+ <parameter name="MEM_RLD3_TCKDK_MIN_CYC" value="-0.27" />
+ <parameter name="MEM_RLD3_TCKQK_MAX_PS" value="135" />
+ <parameter name="MEM_RLD3_TDH_DC_MV" value="100" />
+ <parameter name="MEM_RLD3_TDH_PS" value="5" />
+ <parameter name="MEM_RLD3_TDS_AC_MV" value="150" />
+ <parameter name="MEM_RLD3_TDS_PS" value="-30" />
+ <parameter name="MEM_RLD3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_RLD3_TIH_PS" value="65" />
+ <parameter name="MEM_RLD3_TIS_AC_MV" value="150" />
+ <parameter name="MEM_RLD3_TIS_PS" value="85" />
+ <parameter name="MEM_RLD3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_RLD3_TQKQ_MAX_PS" value="75" />
+ <parameter name="MEM_RLD3_T_RC_MODE_ENUM" value="RLD3_TRC_9" />
+ <parameter name="MEM_RLD3_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_WRITE_PROTOCOL_ENUM" value="RLD3_WRITE_1BANK" />
+ <parameter name="PHY_DDR3_CAL_ADDR0" value="0" />
+ <parameter name="PHY_DDR3_CAL_ADDR1" value="8" />
+ <parameter name="PHY_DDR3_CAL_ENABLE_NON_DES" value="true" />
+ <parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_DDR3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_DDR3_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_DDR3_IO_VOLTAGE" value="1.5" />
+ <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_DDR3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_DDR3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_DDR4_DEFAULT_IO" value="false" />
+ <parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="false" />
+ <parameter name="PHY_DDR4_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="800.0" />
+ <parameter name="PHY_DDR4_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_DDR4_STARTING_VREFIN" value="68.0" />
+ <parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="IO_STD_SSTL_12" />
+ <parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="OUT_OCT_40_CAL" />
+ <parameter name="PHY_DDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="IO_STD_SSTL_12" />
+ <parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="OUT_OCT_40_CAL" />
+ <parameter name="PHY_DDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="IN_OCT_60_CAL" />
+ <parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="IO_STD_POD_12" />
+ <parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="OUT_OCT_34_CAL" />
+ <parameter name="PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_DDR4_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="IO_STD_CMOS_12" />
+ <parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="25.0" />
+ <parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="IO_STD_CMOS_12" />
+ <parameter name="PHY_LPDDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_LPDDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_LPDDR3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_LPDDR3_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_LPDDR3_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_LPDDR3_MEM_CLK_FREQ_MHZ" value="800.0" />
+ <parameter name="PHY_LPDDR3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_LPDDR3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_LPDDR3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_LPDDR3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_LPDDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_LPDDR3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_LPDDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_QDR2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_QDR2_DEFAULT_IO" value="true" />
+ <parameter name="PHY_QDR2_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_QDR2_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_QDR2_IO_VOLTAGE" value="1.5" />
+ <parameter name="PHY_QDR2_MEM_CLK_FREQ_MHZ" value="633.333" />
+ <parameter name="PHY_QDR2_RATE_ENUM" value="RATE_HALF" />
+ <parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_QDR2_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_QDR2_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_QDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_QDR4_DEFAULT_IO" value="true" />
+ <parameter name="PHY_QDR4_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_QDR4_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_QDR4_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_QDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_QDR4_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_QDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR4_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_QDR4_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR4_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_QDR4_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_QDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_RLD2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_RLD2_DEFAULT_IO" value="true" />
+ <parameter name="PHY_RLD2_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_RLD2_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_RLD2_IO_VOLTAGE" value="1.8" />
+ <parameter name="PHY_RLD2_MEM_CLK_FREQ_MHZ" value="533.333" />
+ <parameter name="PHY_RLD2_RATE_ENUM" value="RATE_HALF" />
+ <parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_RLD2_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_RLD2_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_CONFIG_ENUM" value="CONFIG_PHY_ONLY" />
+ <parameter name="PHY_RLD3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_RLD3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_RLD3_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_RLD3_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_RLD3_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_RLD3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_RLD3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_RLD3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PLL_ADD_EXTRA_CLKS" value="0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8" value="0" />
+ <parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
+ <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
+ <parameter name="SHORT_QSYS_INTERFACE_NAMES" value="true" />
+ <parameter name="SYS_INFO_DEVICE" value="10AX115S2F45E1SG" />
+ <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="1" />
+ <parameter name="SYS_INFO_UNIQUE_ID">ip_arria10_e1sg_ddr4_8g_1600_emif_0</parameter>
+ <parameter name="TRAIT_SUPPORTS_VID" value="0" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..474979c64cc05310799c5c096ed8d4951dee229f
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
@@ -0,0 +1,33 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generated/sim"
+
+# Copy ROM/RAM files to simulation directory
+if {[file isdirectory $IP_DIR]} {
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_151_izxxuoi_seq_cal_sim.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_151_izxxuoi_seq_cal_synth.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_151_izxxuoi_seq_params_sim.hex ./
+ file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_151_izxxuoi_seq_params_synth.hex ./
+}
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..4568aee466e37a76240a0701df64a9de8650319a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/generate_ip.sh
@@ -0,0 +1,54 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_ddr4_8g_2400.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
+
+# Also generate the testbench IP, this is not useful because it only generates bus functional models, so not a DDR4 memory model
+#qsys-generate ip_arria10_e1sg_ddr4_8g_2400.qsys \
+# --synthesis=VHDL \
+# --simulation=VHDL \
+# --testbench=STANDARD \
+# --testbench-simulation=VHDL \
+# --output-directory=generated \
+# --allow-mixed-language-simulation \
+# --allow-mixed-language-testbench-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..1a90c209c7dc0a0838c1c16aedc0c02079bb734f
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_ddr4_8g_2400
+hdl_library_clause_name = ip_arria10_e1sg_ddr4_8g_2400_altera_emif_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_ddr4_8g_2400.qip
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qsys b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..e80b5ae656efdc634c642c2e18cca6012af69875
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qsys
@@ -0,0 +1,1180 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_ddr4_8g_2400">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element ddr4_inst
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>ctrl_amm_avalon_slave_0</key>
+ <value>
+ <connectionPointName>ctrl_amm_avalon_slave_0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='ctrl_amm_avalon_slave_0' start='0x0' end='0x240000000' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>34</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>576</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>emif_usr_clk_clock_source</key>
+ <value>
+ <connectionPointName>emif_usr_clk_clock_source</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>300000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="ctrl_amm_avalon_slave_0"
+ internal="ddr4_inst.ctrl_amm_avalon_slave_0"
+ type="avalon"
+ dir="end">
+ <port name="amm_address_0" internal="amm_address_0" />
+ <port name="amm_burstcount_0" internal="amm_burstcount_0" />
+ <port name="amm_byteenable_0" internal="amm_byteenable_0" />
+ <port name="amm_read_0" internal="amm_read_0" />
+ <port name="amm_readdata_0" internal="amm_readdata_0" />
+ <port name="amm_readdatavalid_0" internal="amm_readdatavalid_0" />
+ <port name="amm_ready_0" internal="amm_ready_0" />
+ <port name="amm_write_0" internal="amm_write_0" />
+ <port name="amm_writedata_0" internal="amm_writedata_0" />
+ </interface>
+ <interface
+ name="emif_usr_clk_clock_source"
+ internal="ddr4_inst.emif_usr_clk_clock_source"
+ type="clock"
+ dir="start">
+ <port name="emif_usr_clk" internal="emif_usr_clk" />
+ </interface>
+ <interface
+ name="emif_usr_reset_reset_source"
+ internal="ddr4_inst.emif_usr_reset_reset_source"
+ type="reset"
+ dir="start">
+ <port name="emif_usr_reset_n" internal="emif_usr_reset_n" />
+ </interface>
+ <interface
+ name="global_reset_reset_sink"
+ internal="ddr4_inst.global_reset_reset_sink"
+ type="reset"
+ dir="end">
+ <port name="global_reset_n" internal="global_reset_n" />
+ </interface>
+ <interface
+ name="mem_conduit_end"
+ internal="ddr4_inst.mem_conduit_end"
+ type="conduit"
+ dir="end">
+ <port name="mem_a" internal="mem_a" />
+ <port name="mem_act_n" internal="mem_act_n" />
+ <port name="mem_alert_n" internal="mem_alert_n" />
+ <port name="mem_ba" internal="mem_ba" />
+ <port name="mem_bg" internal="mem_bg" />
+ <port name="mem_ck" internal="mem_ck" />
+ <port name="mem_ck_n" internal="mem_ck_n" />
+ <port name="mem_cke" internal="mem_cke" />
+ <port name="mem_cs_n" internal="mem_cs_n" />
+ <port name="mem_dbi_n" internal="mem_dbi_n" />
+ <port name="mem_dq" internal="mem_dq" />
+ <port name="mem_dqs" internal="mem_dqs" />
+ <port name="mem_dqs_n" internal="mem_dqs_n" />
+ <port name="mem_odt" internal="mem_odt" />
+ <port name="mem_par" internal="mem_par" />
+ <port name="mem_reset_n" internal="mem_reset_n" />
+ </interface>
+ <interface
+ name="oct_conduit_end"
+ internal="ddr4_inst.oct_conduit_end"
+ type="conduit"
+ dir="end">
+ <port name="oct_rzqin" internal="oct_rzqin" />
+ </interface>
+ <interface
+ name="pll_ref_clk_clock_sink"
+ internal="ddr4_inst.pll_ref_clk_clock_sink"
+ type="clock"
+ dir="end">
+ <port name="pll_ref_clk" internal="pll_ref_clk" />
+ </interface>
+ <interface
+ name="status_conduit_end"
+ internal="ddr4_inst.status_conduit_end"
+ type="conduit"
+ dir="end">
+ <port name="local_cal_fail" internal="local_cal_fail" />
+ <port name="local_cal_success" internal="local_cal_success" />
+ </interface>
+ <module
+ name="ddr4_inst"
+ kind="altera_emif"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR3_MAX_DQS_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_DDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR3_USER_AC_ISI_NS" value="0.094" />
+ <parameter name="BOARD_DDR3_USER_AC_SLEW_RATE" value="1.0" />
+ <parameter name="BOARD_DDR3_USER_CK_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR3_USER_RCLK_ISI_NS" value="0.094" />
+ <parameter name="BOARD_DDR3_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR3_USER_RDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_DDR3_USER_RDATA_SLEW_RATE" value="2.5" />
+ <parameter name="BOARD_DDR3_USER_WCLK_ISI_NS" value="0.031" />
+ <parameter name="BOARD_DDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR3_USER_WDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_DDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_DDR3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
+ <parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="true" />
+ <parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.094" />
+ <parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_RCLK_ISI_NS" value="0.094" />
+ <parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_RDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_WCLK_ISI_NS" value="0.031" />
+ <parameter name="BOARD_DDR4_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_DDR4_USER_WDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_DDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_DDR4_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_LPDDR3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
+ <parameter name="BOARD_LPDDR3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_LPDDR3_MAX_DQS_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
+ <parameter name="BOARD_LPDDR3_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_LPDDR3_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_LPDDR3_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_LPDDR3_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_RDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_LPDDR3_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_LPDDR3_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_LPDDR3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_QDR2_AC_TO_K_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR2_MAX_K_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
+ <parameter name="BOARD_QDR2_USER_AC_ISI_NS" value="0.094" />
+ <parameter name="BOARD_QDR2_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_K_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR2_USER_RCLK_ISI_NS" value="0.094" />
+ <parameter name="BOARD_QDR2_USER_RCLK_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_RDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_QDR2_USER_RDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USER_WCLK_ISI_NS" value="0.031" />
+ <parameter name="BOARD_QDR2_USER_WDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_QDR2_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR2_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_QDR2_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_QDR4_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_DK_TO_CK_SKEW_NS" value="-0.02" />
+ <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+ <parameter name="BOARD_QDR4_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR4_MAX_DK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_QDR4_SKEW_BETWEEN_DK_NS" value="0.02" />
+ <parameter name="BOARD_QDR4_USER_AC_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR4_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_RCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_RDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_RDATA_SLEW_RATE" value="3.5" />
+ <parameter name="BOARD_QDR4_USER_WCLK_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_QDR4_USER_WDATA_ISI_NS" value="0.0" />
+ <parameter name="BOARD_QDR4_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_QDR4_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_QDR4_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="BOARD_RLD3_AC_TO_CK_SKEW_NS" value="0.0" />
+ <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_DK_TO_CK_SKEW_NS" value="-0.02" />
+ <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
+ <parameter name="BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
+ <parameter name="BOARD_RLD3_MAX_CK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_RLD3_MAX_DK_DELAY_NS" value="0.6" />
+ <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
+ <parameter name="BOARD_RLD3_SKEW_BETWEEN_DK_NS" value="0.02" />
+ <parameter name="BOARD_RLD3_USER_AC_ISI_NS" value="0.094" />
+ <parameter name="BOARD_RLD3_USER_AC_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_RLD3_USER_CK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_RCLK_ISI_NS" value="0.094" />
+ <parameter name="BOARD_RLD3_USER_RCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_RDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_RLD3_USER_RDATA_SLEW_RATE" value="3.5" />
+ <parameter name="BOARD_RLD3_USER_WCLK_ISI_NS" value="0.031" />
+ <parameter name="BOARD_RLD3_USER_WCLK_SLEW_RATE" value="4.0" />
+ <parameter name="BOARD_RLD3_USER_WDATA_ISI_NS" value="0.063" />
+ <parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
+ <parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
+ <parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
+ <parameter name="CAL_DEBUG_CLOCK_FREQUENCY" value="50000000" />
+ <parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_DDR3_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_DDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_DDR3_ECC_AUTO_CORRECTION_EN" value="false" />
+ <parameter name="CTRL_DDR3_ECC_EN" value="false" />
+ <parameter name="CTRL_DDR3_MMR_EN" value="false" />
+ <parameter name="CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_REORDER_EN" value="true" />
+ <parameter name="CTRL_DDR3_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR3_STARVE_LIMIT" value="63" />
+ <parameter name="CTRL_DDR3_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_DDR3_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_ADDR_ORDER_ENUM">DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG</parameter>
+ <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_DDR4_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_DDR4_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_DDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_DDR4_ECC_AUTO_CORRECTION_EN" value="false" />
+ <parameter name="CTRL_DDR4_ECC_EN" value="false" />
+ <parameter name="CTRL_DDR4_MMR_EN" value="false" />
+ <parameter name="CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_REORDER_EN" value="true" />
+ <parameter name="CTRL_DDR4_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR4_STARVE_LIMIT" value="63" />
+ <parameter name="CTRL_DDR4_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_DDR4_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_ADDR_ORDER_ENUM">LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS" value="32" />
+ <parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_AUTO_PRECHARGE_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_LPDDR3_MMR_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_REORDER_EN" value="true" />
+ <parameter name="CTRL_LPDDR3_SELF_REFRESH_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_STARVE_LIMIT" value="10" />
+ <parameter name="CTRL_LPDDR3_USER_PRIORITY_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_USER_REFRESH_EN" value="false" />
+ <parameter name="CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
+ <parameter name="CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+ <parameter name="CTRL_QDR2_AVL_MAX_BURST_COUNT" value="4" />
+ <parameter name="CTRL_QDR2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC" value="0" />
+ <parameter name="CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC" value="0" />
+ <parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
+ <parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
+ <parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
+ <parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
+ <parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
+ <parameter name="DIAG_DDR3_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_DDR3_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_DDR3_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_DDR3_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_DDR3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_DDR3_CAL_ADDR0" value="0" />
+ <parameter name="DIAG_DDR3_CAL_ADDR1" value="8" />
+ <parameter name="DIAG_DDR3_CAL_ENABLE_NON_DES" value="false" />
+ <parameter name="DIAG_DDR3_CAL_FULL_CAL_ON_RESET" value="true" />
+ <parameter name="DIAG_DDR3_CA_LEVEL_EN" value="false" />
+ <parameter name="DIAG_DDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR3_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_DDR3_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR3_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR3_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_DDR4_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_DDR4_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_DDR4_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_DDR4_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_DDR4_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_DDR4_CAL_ADDR0" value="0" />
+ <parameter name="DIAG_DDR4_CAL_ADDR1" value="8" />
+ <parameter name="DIAG_DDR4_CAL_ENABLE_NON_DES" value="false" />
+ <parameter name="DIAG_DDR4_CAL_FULL_CAL_ON_RESET" value="true" />
+ <parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_DDR4_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_DDR4_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
+ <parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="false" />
+ <parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="true" />
+ <parameter name="DIAG_DDR4_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR4_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_DDR4_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
+ <parameter name="DIAG_ENABLE_HPS_EMIF_DEBUG" value="false" />
+ <parameter name="DIAG_ENABLE_JTAG_UART" value="false" />
+ <parameter name="DIAG_ENABLE_JTAG_UART_HEX" value="false" />
+ <parameter name="DIAG_EXPORT_VJI" value="false" />
+ <parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
+ <parameter name="DIAG_EXTRA_CONFIGS" value="" />
+ <parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
+ <parameter name="DIAG_EX_DESIGN_SEPARATE_RESETS" value="false" />
+ <parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
+ <parameter name="DIAG_LPDDR3_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_LPDDR3_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_LPDDR3_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_LPDDR3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_LPDDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
+ <parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_LPDDR3_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_LPDDR3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_LPDDR3_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_LPDDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_LPDDR3_SKIP_CA_DESKEW" value="false" />
+ <parameter name="DIAG_LPDDR3_SKIP_CA_LEVEL" value="false" />
+ <parameter name="DIAG_LPDDR3_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_LPDDR3_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_LPDDR3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_QDR2_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_QDR2_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_QDR2_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_QDR2_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_QDR2_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_QDR2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR2_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_QDR2_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR2_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR2_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR2_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_QDR4_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_QDR4_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_QDR4_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_QDR4_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_QDR4_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_QDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_QDR4_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_QDR4_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_QDR4_SKIP_VREF_CAL" value="false" />
+ <parameter name="DIAG_QDR4_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR4_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_QDR4_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RLD2_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_RLD2_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_RLD2_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_RLD2_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_RLD2_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_RLD2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD2_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_RLD2_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD2_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD2_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD2_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RLD3_ABSTRACT_PHY" value="false" />
+ <parameter name="DIAG_RLD3_BYPASS_DEFAULT_PATTERN" value="false" />
+ <parameter name="DIAG_RLD3_BYPASS_REPEAT_STAGE" value="true" />
+ <parameter name="DIAG_RLD3_BYPASS_STRESS_STAGE" value="true" />
+ <parameter name="DIAG_RLD3_BYPASS_USER_STAGE" value="true" />
+ <parameter name="DIAG_RLD3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="true" />
+ <parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
+ <parameter name="DIAG_RLD3_EX_DESIGN_ISSP_EN" value="true" />
+ <parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
+ <parameter name="DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS" value="false" />
+ <parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
+ <parameter name="DIAG_RLD3_SEPARATE_READ_WRITE_ITFS" value="false" />
+ <parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
+ <parameter name="DIAG_RLD3_TG_BE_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD3_TG_DATA_PATTERN_LENGTH" value="8" />
+ <parameter name="DIAG_RLD3_USE_TG_AVL_2" value="false" />
+ <parameter name="DIAG_RS232_UART_BAUDRATE" value="57600" />
+ <parameter name="DIAG_SIM_REGTEST_MODE" value="false" />
+ <parameter name="DIAG_SOFT_NIOS_CLOCK_FREQUENCY" value="100" />
+ <parameter name="DIAG_SOFT_NIOS_MODE">SOFT_NIOS_MODE_DISABLED</parameter>
+ <parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
+ <parameter name="DIAG_TG_AVL_2_EXPORT_CFG_INTERFACE" value="false" />
+ <parameter name="DIAG_TG_AVL_2_NUM_CFG_INTERFACES" value="0" />
+ <parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
+ <parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
+ <parameter name="DIAG_USE_RS232_UART" value="false" />
+ <parameter name="DIAG_VERBOSE_IOAUX" value="false" />
+ <parameter name="EX_DESIGN_GUI_DDR3_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR3_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_DDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_DDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_DDR4_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR4_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_DDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_DDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_DDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_LPDDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter
+ name="EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT"
+ value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR2_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR2_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_QDR2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR4_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR4_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_QDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_QDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_QDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD2_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD2_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_RLD2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD3_GEN_SIM" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD3_GEN_SYNTH" value="true" />
+ <parameter name="EX_DESIGN_GUI_RLD3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
+ <parameter name="EX_DESIGN_GUI_RLD3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="EX_DESIGN_GUI_RLD3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
+ <parameter name="EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
+ <parameter name="INTERNAL_TESTING_MODE" value="false" />
+ <parameter name="IS_ED_SLAVE" value="false" />
+ <parameter name="MEM_DDR3_ALERT_N_DQS_GROUP" value="0" />
+ <parameter name="MEM_DDR3_ALERT_N_PLACEMENT_ENUM">DDR3_ALERT_N_PLACEMENT_AC_LANES</parameter>
+ <parameter name="MEM_DDR3_ASR_ENUM" value="DDR3_ASR_MANUAL" />
+ <parameter name="MEM_DDR3_ATCL_ENUM" value="DDR3_ATCL_DISABLED" />
+ <parameter name="MEM_DDR3_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_DDR3_BL_ENUM" value="DDR3_BL_BL8" />
+ <parameter name="MEM_DDR3_BT_ENUM" value="DDR3_BT_SEQUENTIAL" />
+ <parameter name="MEM_DDR3_CKE_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR3_CK_WIDTH" value="1" />
+ <parameter name="MEM_DDR3_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_DDR3_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_DDR3_DISCRETE_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR3_DLL_EN" value="true" />
+ <parameter name="MEM_DDR3_DM_EN" value="true" />
+ <parameter name="MEM_DDR3_DQ_PER_DQS" value="8" />
+ <parameter name="MEM_DDR3_DQ_WIDTH" value="72" />
+ <parameter name="MEM_DDR3_DRV_STR_ENUM" value="DDR3_DRV_STR_RZQ_6" />
+ <parameter name="MEM_DDR3_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
+ <parameter name="MEM_DDR3_HIDE_ADV_MR_SETTINGS" value="true" />
+ <parameter name="MEM_DDR3_LRDIMM_EXTENDED_CONFIG">0x000000000000000000</parameter>
+ <parameter name="MEM_DDR3_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR3_NUM_OF_DIMMS" value="1" />
+ <parameter name="MEM_DDR3_PD_ENUM" value="DDR3_PD_OFF" />
+ <parameter name="MEM_DDR3_RANKS_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR3_RDIMM_CONFIG" value="0000000000000000" />
+ <parameter name="MEM_DDR3_ROW_ADDR_WIDTH" value="14" />
+ <parameter name="MEM_DDR3_RTT_NOM_ENUM">DDR3_RTT_NOM_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR3_RTT_WR_ENUM">DDR3_RTT_WR_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR3_R_ODT0_1X1" value="off" />
+ <parameter name="MEM_DDR3_R_ODT0_2X2" value="off,on" />
+ <parameter name="MEM_DDR3_R_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_R_ODT0_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR3_R_ODT1_2X2" value="on,off" />
+ <parameter name="MEM_DDR3_R_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_R_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_R_ODT2_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR3_R_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR3_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_SPEEDBIN_ENUM" value="DDR3_SPEEDBIN_2133" />
+ <parameter name="MEM_DDR3_SRT_ENUM" value="DDR3_SRT_NORMAL" />
+ <parameter name="MEM_DDR3_TCL" value="7" />
+ <parameter name="MEM_DDR3_TDH_DC_MV" value="100" />
+ <parameter name="MEM_DDR3_TDH_PS" value="55" />
+ <parameter name="MEM_DDR3_TDQSCK_PS" value="180" />
+ <parameter name="MEM_DDR3_TDQSQ_PS" value="75" />
+ <parameter name="MEM_DDR3_TDQSS_CYC" value="0.27" />
+ <parameter name="MEM_DDR3_TDSH_CYC" value="0.18" />
+ <parameter name="MEM_DDR3_TDSS_CYC" value="0.18" />
+ <parameter name="MEM_DDR3_TDS_AC_MV" value="135" />
+ <parameter name="MEM_DDR3_TDS_PS" value="53" />
+ <parameter name="MEM_DDR3_TFAW_NS" value="25.0" />
+ <parameter name="MEM_DDR3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_DDR3_TIH_PS" value="95" />
+ <parameter name="MEM_DDR3_TINIT_US" value="500" />
+ <parameter name="MEM_DDR3_TIS_AC_MV" value="135" />
+ <parameter name="MEM_DDR3_TIS_PS" value="60" />
+ <parameter name="MEM_DDR3_TMRD_CK_CYC" value="4" />
+ <parameter name="MEM_DDR3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_DDR3_TQSH_CYC" value="0.4" />
+ <parameter name="MEM_DDR3_TRAS_NS" value="33.0" />
+ <parameter name="MEM_DDR3_TRCD_NS" value="13.09" />
+ <parameter name="MEM_DDR3_TREFI_US" value="7.8" />
+ <parameter name="MEM_DDR3_TRFC_NS" value="160.0" />
+ <parameter name="MEM_DDR3_TRP_NS" value="13.09" />
+ <parameter name="MEM_DDR3_TRRD_CYC" value="6" />
+ <parameter name="MEM_DDR3_TRTP_CYC" value="8" />
+ <parameter name="MEM_DDR3_TWLH_PS" value="125.0" />
+ <parameter name="MEM_DDR3_TWLS_PS" value="125.0" />
+ <parameter name="MEM_DDR3_TWR_NS" value="15.0" />
+ <parameter name="MEM_DDR3_TWTR_CYC" value="4" />
+ <parameter name="MEM_DDR3_USE_DEFAULT_ODT" value="true" />
+ <parameter name="MEM_DDR3_WTCL" value="6" />
+ <parameter name="MEM_DDR3_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR3_W_ODT0_2X2" value="on,on" />
+ <parameter name="MEM_DDR3_W_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT0_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODT1_2X2" value="on,on" />
+ <parameter name="MEM_DDR3_W_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT2_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR3_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR3_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR3_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_AC_PARITY_LATENCY">DDR4_AC_PARITY_LATENCY_DISABLE</parameter>
+ <parameter name="MEM_DDR4_AC_PERSISTENT_ERROR" value="false" />
+ <parameter name="MEM_DDR4_ALERT_N_AC_LANE" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_AC_PIN" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_DQS_GROUP" value="0" />
+ <parameter name="MEM_DDR4_ALERT_N_PLACEMENT_ENUM">DDR4_ALERT_N_PLACEMENT_DATA_LANES</parameter>
+ <parameter name="MEM_DDR4_ALERT_PAR_EN" value="true" />
+ <parameter name="MEM_DDR4_ASR_ENUM">DDR4_ASR_MANUAL_NORMAL</parameter>
+ <parameter name="MEM_DDR4_ATCL_ENUM" value="DDR4_ATCL_DISABLED" />
+ <parameter name="MEM_DDR4_BANK_ADDR_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_BANK_GROUP_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_BL_ENUM" value="DDR4_BL_BL8" />
+ <parameter name="MEM_DDR4_BT_ENUM" value="DDR4_BT_SEQUENTIAL" />
+ <parameter name="MEM_DDR4_CAL_MODE" value="0" />
+ <parameter name="MEM_DDR4_CHIP_ID_WIDTH" value="0" />
+ <parameter name="MEM_DDR4_CKE_PER_DIMM" value="1" />
+ <parameter name="MEM_DDR4_CK_WIDTH" value="2" />
+ <parameter name="MEM_DDR4_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_DDR4_DB_DQ_DRV_ENUM">DDR4_DB_DRV_STR_RZQ_7</parameter>
+ <parameter name="MEM_DDR4_DB_RTT_NOM_ENUM">DDR4_DB_RTT_NOM_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_DB_RTT_PARK_ENUM">DDR4_DB_RTT_PARK_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_DB_RTT_WR_ENUM">DDR4_DB_RTT_WR_RZQ_3</parameter>
+ <parameter name="MEM_DDR4_DEFAULT_VREFOUT" value="false" />
+ <parameter name="MEM_DDR4_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_DDR4_DISCRETE_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR4_DLL_EN" value="true" />
+ <parameter name="MEM_DDR4_DM_EN" value="true" />
+ <parameter name="MEM_DDR4_DQ_PER_DQS" value="8" />
+ <parameter name="MEM_DDR4_DQ_WIDTH" value="72" />
+ <parameter name="MEM_DDR4_DRV_STR_ENUM" value="DDR4_DRV_STR_RZQ_7" />
+ <parameter name="MEM_DDR4_FINE_GRANULARITY_REFRESH">DDR4_FINE_REFRESH_FIXED_1X</parameter>
+ <parameter name="MEM_DDR4_FORMAT_ENUM" value="MEM_FORMAT_SODIMM" />
+ <parameter name="MEM_DDR4_GEARDOWN" value="DDR4_GEARDOWN_HR" />
+ <parameter name="MEM_DDR4_HIDE_ADV_MR_SETTINGS" value="true" />
+ <parameter name="MEM_DDR4_INTERNAL_VREFDQ_MONITOR" value="false" />
+ <parameter name="MEM_DDR4_LRDIMM_ODT_LESS_BS" value="true" />
+ <parameter name="MEM_DDR4_LRDIMM_ODT_LESS_BS_PARK_OHM" value="240" />
+ <parameter name="MEM_DDR4_LRDIMM_VREFDQ_VALUE" value="1D" />
+ <parameter name="MEM_DDR4_MAX_POWERDOWN" value="false" />
+ <parameter name="MEM_DDR4_MIRROR_ADDRESSING_EN" value="false" />
+ <parameter name="MEM_DDR4_MPR_READ_FORMAT">DDR4_MPR_READ_FORMAT_SERIAL</parameter>
+ <parameter name="MEM_DDR4_NUM_OF_DIMMS" value="1" />
+ <parameter name="MEM_DDR4_ODT_IN_POWERDOWN" value="true" />
+ <parameter name="MEM_DDR4_PER_DRAM_ADDR" value="false" />
+ <parameter name="MEM_DDR4_RANKS_PER_DIMM" value="2" />
+ <parameter name="MEM_DDR4_RCD_CA_IBT_ENUM" value="DDR4_RCD_CA_IBT_100" />
+ <parameter name="MEM_DDR4_RCD_CKE_IBT_ENUM">DDR4_RCD_CKE_IBT_100</parameter>
+ <parameter name="MEM_DDR4_RCD_CS_IBT_ENUM" value="DDR4_RCD_CS_IBT_100" />
+ <parameter name="MEM_DDR4_RCD_ODT_IBT_ENUM">DDR4_RCD_ODT_IBT_100</parameter>
+ <parameter name="MEM_DDR4_READ_DBI" value="false" />
+ <parameter name="MEM_DDR4_READ_PREAMBLE" value="1" />
+ <parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
+ <parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
+ <parameter name="MEM_DDR4_RTT_NOM_ENUM">DDR4_RTT_NOM_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_RTT_WR_ENUM">DDR4_RTT_WR_ODT_DISABLED</parameter>
+ <parameter name="MEM_DDR4_R_ODT0_1X1" value="off" />
+ <parameter name="MEM_DDR4_R_ODT0_2X2" value="off,on" />
+ <parameter name="MEM_DDR4_R_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_R_ODT0_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR4_R_ODT1_2X2" value="on,off" />
+ <parameter name="MEM_DDR4_R_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_R_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_R_ODT2_4X4" value="off,off,off,off" />
+ <parameter name="MEM_DDR4_R_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR4_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR4_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_SELF_RFSH_ABORT" value="false" />
+ <parameter name="MEM_DDR4_SPD_133_RCD_DB_VENDOR_LSB" value="0" />
+ <parameter name="MEM_DDR4_SPD_134_RCD_DB_VENDOR_MSB" value="0" />
+ <parameter name="MEM_DDR4_SPD_135_RCD_REV" value="0" />
+ <parameter name="MEM_DDR4_SPD_137_RCD_CA_DRV" value="101" />
+ <parameter name="MEM_DDR4_SPD_138_RCD_CK_DRV" value="5" />
+ <parameter name="MEM_DDR4_SPD_139_DB_REV" value="0" />
+ <parameter name="MEM_DDR4_SPD_140_DRAM_VREFDQ_R0" value="29" />
+ <parameter name="MEM_DDR4_SPD_141_DRAM_VREFDQ_R1" value="29" />
+ <parameter name="MEM_DDR4_SPD_142_DRAM_VREFDQ_R2" value="29" />
+ <parameter name="MEM_DDR4_SPD_143_DRAM_VREFDQ_R3" value="29" />
+ <parameter name="MEM_DDR4_SPD_144_DB_VREFDQ" value="37" />
+ <parameter name="MEM_DDR4_SPD_145_DB_MDQ_DRV" value="21" />
+ <parameter name="MEM_DDR4_SPD_148_DRAM_DRV" value="0" />
+ <parameter name="MEM_DDR4_SPD_149_DRAM_RTT_WR_NOM" value="20" />
+ <parameter name="MEM_DDR4_SPD_152_DRAM_RTT_PARK" value="39" />
+ <parameter name="MEM_DDR4_SPEEDBIN_ENUM" value="DDR4_SPEEDBIN_2400" />
+ <parameter name="MEM_DDR4_TCCD_L_CYC" value="5" />
+ <parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
+ <parameter name="MEM_DDR4_TCL" value="18" />
+ <parameter name="MEM_DDR4_TDIVW_DJ_CYC" value="0.1" />
+ <parameter name="MEM_DDR4_TDIVW_TOTAL_UI" value="0.2" />
+ <parameter name="MEM_DDR4_TDQSCK_PS" value="180" />
+ <parameter name="MEM_DDR4_TDQSQ_PS" value="66" />
+ <parameter name="MEM_DDR4_TDQSQ_UI" value="0.16" />
+ <parameter name="MEM_DDR4_TDQSS_CYC" value="0.27" />
+ <parameter name="MEM_DDR4_TDSH_CYC" value="0.18" />
+ <parameter name="MEM_DDR4_TDSS_CYC" value="0.18" />
+ <parameter name="MEM_DDR4_TDVWP_UI" value="0.72" />
+ <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA" value="false" />
+ <parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
+ <parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
+ <parameter name="MEM_DDR4_TFAW_NS" value="25.0" />
+ <parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
+ <parameter name="MEM_DDR4_TIH_PS" value="95" />
+ <parameter name="MEM_DDR4_TINIT_US" value="500" />
+ <parameter name="MEM_DDR4_TIS_AC_MV" value="100" />
+ <parameter name="MEM_DDR4_TIS_PS" value="60" />
+ <parameter name="MEM_DDR4_TMRD_CK_CYC" value="8" />
+ <parameter name="MEM_DDR4_TQH_CYC" value="0.38" />
+ <parameter name="MEM_DDR4_TQH_UI" value="0.76" />
+ <parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
+ <parameter name="MEM_DDR4_TRAS_NS" value="33.0" />
+ <parameter name="MEM_DDR4_TRCD_NS" value="14.06" />
+ <parameter name="MEM_DDR4_TREFI_US" value="7.8" />
+ <parameter name="MEM_DDR4_TRFC_NS" value="160.0" />
+ <parameter name="MEM_DDR4_TRP_NS" value="14.06" />
+ <parameter name="MEM_DDR4_TRRD_L_CYC" value="5" />
+ <parameter name="MEM_DDR4_TRRD_S_CYC" value="4" />
+ <parameter name="MEM_DDR4_TWLH_PS" value="122.0" />
+ <parameter name="MEM_DDR4_TWLS_PS" value="122.0" />
+ <parameter name="MEM_DDR4_TWR_NS" value="15.0" />
+ <parameter name="MEM_DDR4_TWTR_L_CYC" value="4" />
+ <parameter name="MEM_DDR4_TWTR_S_CYC" value="2" />
+ <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_1</parameter>
+ <parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_VALUE" value="60.0" />
+ <parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="true" />
+ <parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
+ <parameter name="MEM_DDR4_WRITE_CRC" value="false" />
+ <parameter name="MEM_DDR4_WRITE_DBI" value="false" />
+ <parameter name="MEM_DDR4_WRITE_PREAMBLE" value="1" />
+ <parameter name="MEM_DDR4_WTCL" value="18" />
+ <parameter name="MEM_DDR4_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_DDR4_W_ODT0_2X2" value="on,on" />
+ <parameter name="MEM_DDR4_W_ODT0_4X2" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT0_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODT1_2X2" value="on,on" />
+ <parameter name="MEM_DDR4_W_ODT1_4X2" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODT1_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT2_4X4" value="off,off,on,on" />
+ <parameter name="MEM_DDR4_W_ODT3_4X4" value="on,on,off,off" />
+ <parameter name="MEM_DDR4_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_DDR4_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_DDR4_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_DDR4_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_LPDDR3_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_LPDDR3_BL" value="LPDDR3_BL_BL8" />
+ <parameter name="MEM_LPDDR3_CK_WIDTH" value="1" />
+ <parameter name="MEM_LPDDR3_COL_ADDR_WIDTH" value="10" />
+ <parameter name="MEM_LPDDR3_DATA_LATENCY" value="LPDDR3_DL_RL12_WL6" />
+ <parameter name="MEM_LPDDR3_DISCRETE_CS_WIDTH" value="1" />
+ <parameter name="MEM_LPDDR3_DM_EN" value="true" />
+ <parameter name="MEM_LPDDR3_DQODT">LPDDR3_DQODT_DISABLE</parameter>
+ <parameter name="MEM_LPDDR3_DQ_WIDTH" value="32" />
+ <parameter name="MEM_LPDDR3_DRV_STR">LPDDR3_DRV_STR_40D_40U</parameter>
+ <parameter name="MEM_LPDDR3_NWR" value="LPDDR3_NWR_NWR10" />
+ <parameter name="MEM_LPDDR3_PDODT">LPDDR3_PDODT_DISABLED</parameter>
+ <parameter name="MEM_LPDDR3_ROW_ADDR_WIDTH" value="15" />
+ <parameter name="MEM_LPDDR3_R_ODT0_1X1" value="off" />
+ <parameter name="MEM_LPDDR3_R_ODT0_2X2" value="off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT0_4X4" value="off,off,on,on" />
+ <parameter name="MEM_LPDDR3_R_ODT1_2X2" value="off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT1_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT2_4X4" value="on,on,off,off" />
+ <parameter name="MEM_LPDDR3_R_ODT3_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_R_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_LPDDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_LPDDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_LPDDR3_SPEEDBIN_ENUM">LPDDR3_SPEEDBIN_1600</parameter>
+ <parameter name="MEM_LPDDR3_TDH_DC_MV" value="100" />
+ <parameter name="MEM_LPDDR3_TDH_PS" value="100" />
+ <parameter name="MEM_LPDDR3_TDQSCKDL" value="614" />
+ <parameter name="MEM_LPDDR3_TDQSQ_PS" value="135" />
+ <parameter name="MEM_LPDDR3_TDQSS_CYC" value="1.25" />
+ <parameter name="MEM_LPDDR3_TDSH_CYC" value="0.2" />
+ <parameter name="MEM_LPDDR3_TDSS_CYC" value="0.2" />
+ <parameter name="MEM_LPDDR3_TDS_AC_MV" value="150" />
+ <parameter name="MEM_LPDDR3_TDS_PS" value="75" />
+ <parameter name="MEM_LPDDR3_TFAW_NS" value="50.0" />
+ <parameter name="MEM_LPDDR3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_LPDDR3_TIH_PS" value="100" />
+ <parameter name="MEM_LPDDR3_TINIT_US" value="500" />
+ <parameter name="MEM_LPDDR3_TIS_AC_MV" value="150" />
+ <parameter name="MEM_LPDDR3_TIS_PS" value="75" />
+ <parameter name="MEM_LPDDR3_TMRR_CK_CYC" value="4" />
+ <parameter name="MEM_LPDDR3_TMRW_CK_CYC" value="10" />
+ <parameter name="MEM_LPDDR3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_LPDDR3_TQSH_CYC" value="0.38" />
+ <parameter name="MEM_LPDDR3_TRAS_NS" value="42.5" />
+ <parameter name="MEM_LPDDR3_TRCD_NS" value="18.75" />
+ <parameter name="MEM_LPDDR3_TREFI_US" value="3.9" />
+ <parameter name="MEM_LPDDR3_TRFC_NS" value="210.0" />
+ <parameter name="MEM_LPDDR3_TRP_NS" value="18.75" />
+ <parameter name="MEM_LPDDR3_TRRD_CYC" value="2" />
+ <parameter name="MEM_LPDDR3_TRTP_CYC" value="4" />
+ <parameter name="MEM_LPDDR3_TWLH_PS" value="175.0" />
+ <parameter name="MEM_LPDDR3_TWLS_PS" value="175.0" />
+ <parameter name="MEM_LPDDR3_TWR_NS" value="15.0" />
+ <parameter name="MEM_LPDDR3_TWTR_CYC" value="4" />
+ <parameter name="MEM_LPDDR3_USE_DEFAULT_ODT" value="true" />
+ <parameter name="MEM_LPDDR3_W_ODT0_1X1" value="on" />
+ <parameter name="MEM_LPDDR3_W_ODT0_2X2" value="on,off" />
+ <parameter name="MEM_LPDDR3_W_ODT0_4X4" value="on,on,on,on" />
+ <parameter name="MEM_LPDDR3_W_ODT1_2X2" value="off,on" />
+ <parameter name="MEM_LPDDR3_W_ODT1_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_W_ODT2_4X4" value="on,on,on,on" />
+ <parameter name="MEM_LPDDR3_W_ODT3_4X4" value="off,off,off,off" />
+ <parameter name="MEM_LPDDR3_W_ODTN_1X1" value="Rank 0" />
+ <parameter name="MEM_LPDDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
+ <parameter name="MEM_LPDDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
+ <parameter name="MEM_QDR2_ADDR_WIDTH" value="19" />
+ <parameter name="MEM_QDR2_BL" value="4" />
+ <parameter name="MEM_QDR2_BWS_EN" value="true" />
+ <parameter name="MEM_QDR2_DATA_PER_DEVICE" value="36" />
+ <parameter name="MEM_QDR2_INTERNAL_JITTER_NS" value="0.08" />
+ <parameter name="MEM_QDR2_SPEEDBIN_ENUM" value="QDR2_SPEEDBIN_633" />
+ <parameter name="MEM_QDR2_TCCQO_NS" value="0.45" />
+ <parameter name="MEM_QDR2_TCQDOH_NS" value="-0.09" />
+ <parameter name="MEM_QDR2_TCQD_NS" value="0.09" />
+ <parameter name="MEM_QDR2_TCQH_NS" value="0.71" />
+ <parameter name="MEM_QDR2_THA_NS" value="0.18" />
+ <parameter name="MEM_QDR2_THD_NS" value="0.18" />
+ <parameter name="MEM_QDR2_TRL_CYC" value="2.5" />
+ <parameter name="MEM_QDR2_TSA_NS" value="0.23" />
+ <parameter name="MEM_QDR2_TSD_NS" value="0.23" />
+ <parameter name="MEM_QDR2_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_QDR4_AC_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_ADDR_INV_ENA" value="false" />
+ <parameter name="MEM_QDR4_ADDR_WIDTH" value="21" />
+ <parameter name="MEM_QDR4_CK_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_DATA_INV_ENA" value="false" />
+ <parameter name="MEM_QDR4_DATA_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
+ <parameter name="MEM_QDR4_DQ_PER_PORT_PER_DEVICE" value="36" />
+ <parameter name="MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+ <parameter name="MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
+ <parameter name="MEM_QDR4_SPEEDBIN_ENUM" value="QDR4_SPEEDBIN_2133" />
+ <parameter name="MEM_QDR4_TASH_PS" value="170" />
+ <parameter name="MEM_QDR4_TCKDK_MAX_PS" value="150" />
+ <parameter name="MEM_QDR4_TCKDK_MIN_PS" value="-150" />
+ <parameter name="MEM_QDR4_TCKQK_MAX_PS" value="225" />
+ <parameter name="MEM_QDR4_TCSH_PS" value="170" />
+ <parameter name="MEM_QDR4_TISH_PS" value="150" />
+ <parameter name="MEM_QDR4_TQH_CYC" value="0.4" />
+ <parameter name="MEM_QDR4_TQKQ_MAX_PS" value="75" />
+ <parameter name="MEM_QDR4_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD2_ADDR_WIDTH" value="21" />
+ <parameter name="MEM_RLD2_BANK_ADDR_WIDTH" value="3" />
+ <parameter name="MEM_RLD2_BL" value="4" />
+ <parameter name="MEM_RLD2_CONFIG_ENUM">RLD2_CONFIG_TRC_8_TRL_8_TWL_9</parameter>
+ <parameter name="MEM_RLD2_DM_EN" value="true" />
+ <parameter name="MEM_RLD2_DQ_PER_DEVICE" value="9" />
+ <parameter name="MEM_RLD2_DRIVE_IMPEDENCE_ENUM">RLD2_DRIVE_IMPEDENCE_INTERNAL_50</parameter>
+ <parameter name="MEM_RLD2_ODT_MODE_ENUM" value="RLD2_ODT_ON" />
+ <parameter name="MEM_RLD2_REFRESH_INTERVAL_US" value="0.24" />
+ <parameter name="MEM_RLD2_SPEEDBIN_ENUM" value="RLD2_SPEEDBIN_18" />
+ <parameter name="MEM_RLD2_TAH_NS" value="0.3" />
+ <parameter name="MEM_RLD2_TAS_NS" value="0.3" />
+ <parameter name="MEM_RLD2_TCKDK_MAX_NS" value="0.3" />
+ <parameter name="MEM_RLD2_TCKDK_MIN_NS" value="-0.3" />
+ <parameter name="MEM_RLD2_TCKH_CYC" value="0.45" />
+ <parameter name="MEM_RLD2_TCKQK_MAX_NS" value="0.2" />
+ <parameter name="MEM_RLD2_TDH_NS" value="0.17" />
+ <parameter name="MEM_RLD2_TDS_NS" value="0.17" />
+ <parameter name="MEM_RLD2_TQKH_HCYC" value="0.9" />
+ <parameter name="MEM_RLD2_TQKQ_MAX_NS" value="0.12" />
+ <parameter name="MEM_RLD2_TQKQ_MIN_NS" value="-0.12" />
+ <parameter name="MEM_RLD2_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_ADDR_WIDTH" value="20" />
+ <parameter name="MEM_RLD3_AREF_PROTOCOL_ENUM" value="RLD3_AREF_BAC" />
+ <parameter name="MEM_RLD3_BANK_ADDR_WIDTH" value="4" />
+ <parameter name="MEM_RLD3_BL" value="2" />
+ <parameter name="MEM_RLD3_DATA_LATENCY_MODE_ENUM" value="RLD3_DL_RL16_WL17" />
+ <parameter name="MEM_RLD3_DEPTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_DM_EN" value="true" />
+ <parameter name="MEM_RLD3_DQ_PER_DEVICE" value="36" />
+ <parameter name="MEM_RLD3_ODT_MODE_ENUM" value="RLD3_ODT_40" />
+ <parameter name="MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM">RLD3_OUTPUT_DRIVE_40</parameter>
+ <parameter name="MEM_RLD3_SPEEDBIN_ENUM" value="RLD3_SPEEDBIN_093E" />
+ <parameter name="MEM_RLD3_TCKDK_MAX_CYC" value="0.27" />
+ <parameter name="MEM_RLD3_TCKDK_MIN_CYC" value="-0.27" />
+ <parameter name="MEM_RLD3_TCKQK_MAX_PS" value="135" />
+ <parameter name="MEM_RLD3_TDH_DC_MV" value="100" />
+ <parameter name="MEM_RLD3_TDH_PS" value="5" />
+ <parameter name="MEM_RLD3_TDS_AC_MV" value="150" />
+ <parameter name="MEM_RLD3_TDS_PS" value="-30" />
+ <parameter name="MEM_RLD3_TIH_DC_MV" value="100" />
+ <parameter name="MEM_RLD3_TIH_PS" value="65" />
+ <parameter name="MEM_RLD3_TIS_AC_MV" value="150" />
+ <parameter name="MEM_RLD3_TIS_PS" value="85" />
+ <parameter name="MEM_RLD3_TQH_CYC" value="0.38" />
+ <parameter name="MEM_RLD3_TQKQ_MAX_PS" value="75" />
+ <parameter name="MEM_RLD3_T_RC_MODE_ENUM" value="RLD3_TRC_9" />
+ <parameter name="MEM_RLD3_WIDTH_EXPANDED" value="false" />
+ <parameter name="MEM_RLD3_WRITE_PROTOCOL_ENUM" value="RLD3_WRITE_1BANK" />
+ <parameter name="PHY_DDR3_CAL_ADDR0" value="0" />
+ <parameter name="PHY_DDR3_CAL_ADDR1" value="8" />
+ <parameter name="PHY_DDR3_CAL_ENABLE_NON_DES" value="true" />
+ <parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_DDR3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="false" />
+ <parameter name="PHY_DDR3_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_DDR3_IO_VOLTAGE" value="1.5" />
+ <parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_DDR3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_DDR3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="133.333" />
+ <parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_DDR4_DEFAULT_IO" value="true" />
+ <parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="false" />
+ <parameter name="PHY_DDR4_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="1200.0" />
+ <parameter name="PHY_DDR4_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_DDR4_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_DDR4_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="25.0" />
+ <parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
+ <parameter name="PHY_LPDDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_LPDDR3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_LPDDR3_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_LPDDR3_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_LPDDR3_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_LPDDR3_MEM_CLK_FREQ_MHZ" value="800.0" />
+ <parameter name="PHY_LPDDR3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_LPDDR3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_LPDDR3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_LPDDR3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_LPDDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_LPDDR3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_LPDDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_QDR2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_QDR2_DEFAULT_IO" value="true" />
+ <parameter name="PHY_QDR2_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_QDR2_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_QDR2_IO_VOLTAGE" value="1.5" />
+ <parameter name="PHY_QDR2_MEM_CLK_FREQ_MHZ" value="633.333" />
+ <parameter name="PHY_QDR2_RATE_ENUM" value="RATE_HALF" />
+ <parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_QDR2_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_QDR2_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_QDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_QDR4_DEFAULT_IO" value="true" />
+ <parameter name="PHY_QDR4_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_QDR4_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_QDR4_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_QDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_QDR4_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_QDR4_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_QDR4_STARTING_VREFIN" value="70.0" />
+ <parameter name="PHY_QDR4_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR4_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_QDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_QDR4_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_QDR4_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_QDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
+ <parameter name="PHY_RLD2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_RLD2_DEFAULT_IO" value="true" />
+ <parameter name="PHY_RLD2_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_RLD2_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_RLD2_IO_VOLTAGE" value="1.8" />
+ <parameter name="PHY_RLD2_MEM_CLK_FREQ_MHZ" value="533.333" />
+ <parameter name="PHY_RLD2_RATE_ENUM" value="RATE_HALF" />
+ <parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_RLD2_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_RLD2_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_CONFIG_ENUM" value="CONFIG_PHY_ONLY" />
+ <parameter name="PHY_RLD3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
+ <parameter name="PHY_RLD3_DEFAULT_IO" value="true" />
+ <parameter name="PHY_RLD3_DEFAULT_REF_CLK_FREQ" value="true" />
+ <parameter name="PHY_RLD3_HPS_ENABLE_EARLY_RELEASE" value="false" />
+ <parameter name="PHY_RLD3_IO_VOLTAGE" value="1.2" />
+ <parameter name="PHY_RLD3_MEM_CLK_FREQ_MHZ" value="1066.667" />
+ <parameter name="PHY_RLD3_RATE_ENUM" value="RATE_QUARTER" />
+ <parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
+ <parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
+ <parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_PERIODIC_OCT_RECAL_ENUM">PERIODIC_OCT_RECAL_AUTO</parameter>
+ <parameter name="PHY_RLD3_USER_PING_PONG_EN" value="false" />
+ <parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
+ <parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
+ <parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
+ <parameter name="PLL_ADD_EXTRA_CLKS" value="0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8" value="50.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8" value="100.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8" value="0.0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7" value="0" />
+ <parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8" value="0" />
+ <parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
+ <parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
+ <parameter name="SHORT_QSYS_INTERFACE_NAMES" value="false" />
+ <parameter name="SYS_INFO_DEVICE" value="10AX115S2F45E1SG" />
+ <parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="1" />
+ <parameter name="SYS_INFO_UNIQUE_ID">ip_arria10_e1sg_ddr4_8g_2400_ddr4_inst</parameter>
+ <parameter name="TRAIT_SUPPORTS_VID" value="0" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/README.txt b/libraries/technology/ip_arria10_e1sg/fifo/README.txt
new file mode 100755
index 0000000000000000000000000000000000000000..48f19d8f0da8b25abe9f0f1f63591777534c35c5
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/fifo/README.txt
@@ -0,0 +1,61 @@
+README.txt for $RADIOHDL/libraries/technology/ip_arria10/fifo
+
+Contents:
+
+1) FIFO components
+2) Arria10 IP
+3) Implementation options (LUTs or block RAM)
+4) Synthesis trials
+5) Issues
+
+
+1) FIFO components:
+
+ ip_arria10_fifo_sc = Single clock FIFO
+ ip_arria10_fifo_dc = Dual clock FIFO
+ ip_arria10_fifo_dc_mixed_widths = Dual clock FIFO with different read and write data widths (ratio power of 2)
+
+
+2) Arria10 IP
+
+ The IP was ported from Stratix IV by:
+
+ . copy original MegaWizard <fifo_name>.vhd file
+ . rename <fifo_name>.vhd into ip_arria10_<fifo_name>.vhd (also replace name inside the file)
+ . commit the fifo/ip_arria10_<fifo_name>.vhd to preserve the MegaWizard original
+ . open in to Quartus 14, set device family to Arria10 and finish automatically convert to Qsys
+ . then generate HDL (select VHDL for both sim and synth) and finish to save it as ip_arria10_<fifo_name>.qsys
+
+ this yields:
+
+ ip_arria10_fifo_sc.qsys
+ ip_arria10_fifo_dc.qsys
+ ip_arria10_fifo_dc_mixed_widths.qsys
+
+ The Arria10 FIFO IP still uses the altera_mf package (so not the altera_lnsim package as with the block RAM). The
+ FIFOs map to the altera_mf components to scfifo, dcfifo and dcfifo_mixed_widths.
+
+ The IP only needs to be generated with ./generate_ip.sh if it need to be modified, because the ip_arria10_fifo_*.vhd
+ directly instantiates the altera_mf component.
+
+ The instantiation is copied manually from the generated/ip_arria10_fifo_*/fifo_140/sim/ip_arria10_fifo_*.vhd and
+ saved in the <fifo_name>.vhd file. So then the MegaWizard vhd file is overwritten, but that is fine because it is
+ no longer needed, it could easily be derived from the original in $UNB and it is still as a previous verion in SVN.
+
+
+3) Implementation options (LUTs or block RAM)
+
+ The IP FIFO can be set to use LUTs (MLAB) or block RAM (M20K) via g_use_eab.
+
+
+4) Synthesis trials
+
+ The quartus/fifo.qpf Quartus project was used to verify that the FIFO IP actually synthesise to the appropriate FPGA resources.
+ Use the Quartus GUI to manually select a top level component for synthesis e.g. by right clicking the entity vhd file
+ in the file tab of the Quartus project navigator window.
+ Then check the resource usage in the synthesis and fitter reports.
+
+
+5) Issues
+
+ No issues.
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..bf3d60117dc35b41f0437547bcf1ae7140023f02
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/fifo/generate_ip.sh
@@ -0,0 +1,49 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Remark:
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+# The IP only needs to be generated if it need to be modified, because the ip_arria10_e1sg_fifo_*.vhd directly instantiates
+# the FIFO altera_mf component.
+# The instantiation is copied manually from the generated/ip_arria10_e1sg_ram_*/fifo_140/sim/ip_arria10_e1sg_fifo_*.vhd.
+# It appears that the altera_mf FIFO component for Arria10 can be synthesized similar as how it worked for Stratix IV,
+# it is not necessary to use the generated qip file.
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+qsys-generate ip_arria10_e1sg_fifo_sc.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
+qsys-generate ip_arria10_e1sg_fifo_dc.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
+qsys-generate ip_arria10_e1sg_fifo_dc_mixed_widths.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fifo/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..6bbc027dd8f4d49807a564e0050d5d985311cb8a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/fifo/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_fifo
+hdl_library_clause_name = ip_arria10_e1sg_fifo_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+ ip_arria10_e1sg_fifo_sc.vhd
+ ip_arria10_e1sg_fifo_dc.vhd
+ ip_arria10_e1sg_fifo_dc_mixed_widths.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.qsys b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..8d63594ecc0214ce3697ee27b48e44fa5e350783
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.qsys
@@ -0,0 +1,117 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_fifo_dc">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element ip_arria10_fifo_dc
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="fifo_input"
+ internal="ip_arria10_fifo_dc.fifo_input"
+ type="conduit"
+ dir="end">
+ <port name="aclr" internal="aclr" />
+ <port name="data" internal="data" />
+ <port name="rdclk" internal="rdclk" />
+ <port name="rdreq" internal="rdreq" />
+ <port name="wrclk" internal="wrclk" />
+ <port name="wrreq" internal="wrreq" />
+ </interface>
+ <interface
+ name="fifo_output"
+ internal="ip_arria10_fifo_dc.fifo_output"
+ type="conduit"
+ dir="end">
+ <port name="q" internal="q" />
+ <port name="rdempty" internal="rdempty" />
+ <port name="rdusedw" internal="rdusedw" />
+ <port name="wrfull" internal="wrfull" />
+ <port name="wrusedw" internal="wrusedw" />
+ </interface>
+ <module
+ name="ip_arria10_fifo_dc"
+ kind="fifo"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_AlmostEmpty" value="false" />
+ <parameter name="GUI_AlmostEmptyThr" value="-1" />
+ <parameter name="GUI_AlmostFull" value="false" />
+ <parameter name="GUI_AlmostFullThr" value="-1" />
+ <parameter name="GUI_CLOCKS_ARE_SYNCHRONIZED" value="0" />
+ <parameter name="GUI_Clock" value="4" />
+ <parameter name="GUI_DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT" value="true" />
+ <parameter name="GUI_Depth" value="256" />
+ <parameter name="GUI_ENABLE_ECC" value="false" />
+ <parameter name="GUI_Empty" value="true" />
+ <parameter name="GUI_Full" value="true" />
+ <parameter name="GUI_LE_BasedFIFO" value="false" />
+ <parameter name="GUI_LegacyRREQ" value="1" />
+ <parameter name="GUI_MAX_DEPTH" value="Auto" />
+ <parameter name="GUI_MAX_DEPTH_BY_9" value="false" />
+ <parameter name="GUI_OVERFLOW_CHECKING" value="false" />
+ <parameter name="GUI_Optimize" value="1" />
+ <parameter name="GUI_Optimize_max" value="1" />
+ <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
+ <parameter name="GUI_UNDERFLOW_CHECKING" value="false" />
+ <parameter name="GUI_UsedW" value="true" />
+ <parameter name="GUI_Width" value="8" />
+ <parameter name="GUI_dc_aclr" value="true" />
+ <parameter name="GUI_delaypipe" value="5" />
+ <parameter name="GUI_diff_widths" value="false" />
+ <parameter name="GUI_msb_usedw" value="false" />
+ <parameter name="GUI_output_width" value="8" />
+ <parameter name="GUI_read_aclr_synch" value="false" />
+ <parameter name="GUI_rsEmpty" value="true" />
+ <parameter name="GUI_rsFull" value="false" />
+ <parameter name="GUI_rsUsedW" value="true" />
+ <parameter name="GUI_sc_aclr" value="false" />
+ <parameter name="GUI_sc_sclr" value="false" />
+ <parameter name="GUI_synStage" value="3" />
+ <parameter name="GUI_write_aclr_synch" value="true" />
+ <parameter name="GUI_wsEmpty" value="false" />
+ <parameter name="GUI_wsFull" value="true" />
+ <parameter name="GUI_wsUsedW" value="true" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.vhd b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8c648506869381c4ec3f013f9e4e2f66476c2193
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.vhd
@@ -0,0 +1,122 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Instantiate FIFO IP with generics
+-- Description:
+-- Copied component declaration and instance example from generated/fifo_140/sim/ip_arria10_e3sge3_fifo_dc_fifo_140_c4o7vda.vhd
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY ip_arria10_e3sge3_fifo_dc IS
+ GENERIC (
+ g_use_eab : STRING := "ON";
+ g_dat_w : NATURAL := 20;
+ g_nof_words : NATURAL := 1024
+ );
+ PORT (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+END ip_arria10_e3sge3_fifo_dc;
+
+
+ARCHITECTURE SYN OF ip_arria10_e3sge3_fifo_dc IS
+
+ COMPONENT dcfifo
+ GENERIC (
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ overflow_checking : STRING;
+ rdsync_delaypipe : NATURAL;
+ read_aclr_synch : STRING;
+ underflow_checking : STRING;
+ use_eab : STRING;
+ write_aclr_synch : STRING;
+ wrsync_delaypipe : NATURAL
+ );
+ PORT (
+ aclr : IN STD_LOGIC;
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC;
+ rdreq : IN STD_LOGIC;
+ wrclk : IN STD_LOGIC;
+ wrreq : IN STD_LOGIC;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC;
+ rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC;
+ wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+BEGIN
+
+ u_dcfifo : dcfifo
+ GENERIC MAP (
+ intended_device_family => "Arria 10",
+ lpm_numwords => g_nof_words,
+ lpm_showahead => "OFF",
+ lpm_type => "dcfifo",
+ lpm_width => g_dat_w,
+ lpm_widthu => tech_ceil_log2(g_nof_words),
+ overflow_checking => "ON",
+ rdsync_delaypipe => 5,
+ read_aclr_synch => "OFF",
+ underflow_checking => "ON",
+ use_eab => g_use_eab,
+ write_aclr_synch => "ON",
+ wrsync_delaypipe => 5
+ )
+ PORT MAP (
+ aclr => aclr,
+ data => data,
+ rdclk => rdclk,
+ rdreq => rdreq,
+ wrclk => wrclk,
+ wrreq => wrreq,
+ q => q,
+ rdempty => rdempty,
+ rdusedw => rdusedw,
+ wrfull => wrfull,
+ wrusedw => wrusedw
+ );
+
+END SYN;
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.qsys b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..e1b4b178ce57cc2681ca6b137d420682db05a6ba
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.qsys
@@ -0,0 +1,117 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_fifo_dc_mixed_widths">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element ip_arria10_fifo_dc_mixed_widths
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="fifo_input"
+ internal="ip_arria10_fifo_dc_mixed_widths.fifo_input"
+ type="conduit"
+ dir="end">
+ <port name="aclr" internal="aclr" />
+ <port name="data" internal="data" />
+ <port name="rdclk" internal="rdclk" />
+ <port name="rdreq" internal="rdreq" />
+ <port name="wrclk" internal="wrclk" />
+ <port name="wrreq" internal="wrreq" />
+ </interface>
+ <interface
+ name="fifo_output"
+ internal="ip_arria10_fifo_dc_mixed_widths.fifo_output"
+ type="conduit"
+ dir="end">
+ <port name="q" internal="q" />
+ <port name="rdempty" internal="rdempty" />
+ <port name="rdusedw" internal="rdusedw" />
+ <port name="wrfull" internal="wrfull" />
+ <port name="wrusedw" internal="wrusedw" />
+ </interface>
+ <module
+ name="ip_arria10_fifo_dc_mixed_widths"
+ kind="fifo"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_AlmostEmpty" value="false" />
+ <parameter name="GUI_AlmostEmptyThr" value="-1" />
+ <parameter name="GUI_AlmostFull" value="false" />
+ <parameter name="GUI_AlmostFullThr" value="-1" />
+ <parameter name="GUI_CLOCKS_ARE_SYNCHRONIZED" value="0" />
+ <parameter name="GUI_Clock" value="4" />
+ <parameter name="GUI_DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT" value="true" />
+ <parameter name="GUI_Depth" value="256" />
+ <parameter name="GUI_ENABLE_ECC" value="false" />
+ <parameter name="GUI_Empty" value="true" />
+ <parameter name="GUI_Full" value="true" />
+ <parameter name="GUI_LE_BasedFIFO" value="false" />
+ <parameter name="GUI_LegacyRREQ" value="1" />
+ <parameter name="GUI_MAX_DEPTH" value="Auto" />
+ <parameter name="GUI_MAX_DEPTH_BY_9" value="false" />
+ <parameter name="GUI_OVERFLOW_CHECKING" value="false" />
+ <parameter name="GUI_Optimize" value="1" />
+ <parameter name="GUI_Optimize_max" value="1" />
+ <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
+ <parameter name="GUI_UNDERFLOW_CHECKING" value="false" />
+ <parameter name="GUI_UsedW" value="true" />
+ <parameter name="GUI_Width" value="8" />
+ <parameter name="GUI_dc_aclr" value="true" />
+ <parameter name="GUI_delaypipe" value="5" />
+ <parameter name="GUI_diff_widths" value="true" />
+ <parameter name="GUI_msb_usedw" value="false" />
+ <parameter name="GUI_output_width" value="16" />
+ <parameter name="GUI_read_aclr_synch" value="false" />
+ <parameter name="GUI_rsEmpty" value="true" />
+ <parameter name="GUI_rsFull" value="false" />
+ <parameter name="GUI_rsUsedW" value="true" />
+ <parameter name="GUI_sc_aclr" value="false" />
+ <parameter name="GUI_sc_sclr" value="false" />
+ <parameter name="GUI_synStage" value="3" />
+ <parameter name="GUI_write_aclr_synch" value="true" />
+ <parameter name="GUI_wsEmpty" value="false" />
+ <parameter name="GUI_wsFull" value="true" />
+ <parameter name="GUI_wsUsedW" value="true" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..fabcec14d55a7da70af702d52fa4a0f166846b49
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.vhd
@@ -0,0 +1,126 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Instantiate FIFO IP with generics
+-- Description:
+-- Copied component declaration and instance example from generated/fifo_140/sim/ip_arria10_e3sge3_fifo_dc_mixed_widths_fifo_140_5csdcfa.vhd
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY ip_arria10_e3sge3_fifo_dc_mixed_widths IS
+ GENERIC (
+ g_nof_words : NATURAL := 1024; -- FIFO size in nof wr_dat words
+ g_wrdat_w : NATURAL := 20;
+ g_rddat_w : NATURAL := 10
+ );
+ PORT (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
+ wrfull : OUT STD_LOGIC ;
+ wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+END ip_arria10_e3sge3_fifo_dc_mixed_widths;
+
+
+ARCHITECTURE SYN OF ip_arria10_e3sge3_fifo_dc_mixed_widths IS
+
+ COMPONENT dcfifo_mixed_widths
+ GENERIC (
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ lpm_widthu_r : NATURAL;
+ lpm_width_r : NATURAL;
+ overflow_checking : STRING;
+ rdsync_delaypipe : NATURAL;
+ read_aclr_synch : STRING;
+ underflow_checking : STRING;
+ use_eab : STRING;
+ write_aclr_synch : STRING;
+ wrsync_delaypipe : NATURAL
+ );
+ PORT (
+ aclr : IN STD_LOGIC;
+ data : IN STD_LOGIC_VECTOR (data'RANGE);
+ rdclk : IN STD_LOGIC;
+ rdreq : IN STD_LOGIC;
+ wrclk : IN STD_LOGIC;
+ wrreq : IN STD_LOGIC;
+ q : OUT STD_LOGIC_VECTOR (q'RANGE);
+ rdempty : OUT STD_LOGIC;
+ rdusedw : OUT STD_LOGIC_VECTOR (rdusedw'RANGE);
+ wrfull : OUT STD_LOGIC;
+ wrusedw : OUT STD_LOGIC_VECTOR (wrusedw'RANGE)
+ );
+ END COMPONENT;
+
+BEGIN
+
+ dcfifo_mixed_widths_component : dcfifo_mixed_widths
+ GENERIC MAP (
+ intended_device_family => "Arria 10",
+ lpm_numwords => g_nof_words,
+ lpm_showahead => "OFF",
+ lpm_type => "dcfifo_mixed_widths",
+ lpm_width => g_wrdat_w,
+ lpm_widthu => tech_ceil_log2(g_nof_words),
+ lpm_widthu_r => tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w),
+ lpm_width_r => g_rddat_w,
+ overflow_checking => "ON",
+ rdsync_delaypipe => 5,
+ read_aclr_synch => "OFF",
+ underflow_checking => "ON",
+ use_eab => "ON",
+ write_aclr_synch => "ON",
+ wrsync_delaypipe => 5
+ )
+ PORT MAP (
+ aclr => aclr,
+ data => data,
+ rdclk => rdclk,
+ rdreq => rdreq,
+ wrclk => wrclk,
+ wrreq => wrreq,
+ q => q,
+ rdempty => rdempty,
+ rdusedw => rdusedw,
+ wrfull => wrfull,
+ wrusedw => wrusedw
+ );
+
+END SYN;
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.qsys b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..6d7da701f2845b51ab2859038c29c60d1ca28cc3
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.qsys
@@ -0,0 +1,115 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_fifo_sc">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element ip_arria10_fifo_sc
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="fifo_input"
+ internal="ip_arria10_fifo_sc.fifo_input"
+ type="conduit"
+ dir="end">
+ <port name="aclr" internal="aclr" />
+ <port name="clock" internal="clock" />
+ <port name="data" internal="data" />
+ <port name="rdreq" internal="rdreq" />
+ <port name="wrreq" internal="wrreq" />
+ </interface>
+ <interface
+ name="fifo_output"
+ internal="ip_arria10_fifo_sc.fifo_output"
+ type="conduit"
+ dir="end">
+ <port name="empty" internal="empty" />
+ <port name="full" internal="full" />
+ <port name="q" internal="q" />
+ <port name="usedw" internal="usedw" />
+ </interface>
+ <module
+ name="ip_arria10_fifo_sc"
+ kind="fifo"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_AlmostEmpty" value="false" />
+ <parameter name="GUI_AlmostEmptyThr" value="-1" />
+ <parameter name="GUI_AlmostFull" value="false" />
+ <parameter name="GUI_AlmostFullThr" value="-1" />
+ <parameter name="GUI_CLOCKS_ARE_SYNCHRONIZED" value="1" />
+ <parameter name="GUI_Clock" value="0" />
+ <parameter name="GUI_DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT" value="true" />
+ <parameter name="GUI_Depth" value="256" />
+ <parameter name="GUI_ENABLE_ECC" value="false" />
+ <parameter name="GUI_Empty" value="true" />
+ <parameter name="GUI_Full" value="true" />
+ <parameter name="GUI_LE_BasedFIFO" value="false" />
+ <parameter name="GUI_LegacyRREQ" value="1" />
+ <parameter name="GUI_MAX_DEPTH" value="Auto" />
+ <parameter name="GUI_MAX_DEPTH_BY_9" value="false" />
+ <parameter name="GUI_OVERFLOW_CHECKING" value="false" />
+ <parameter name="GUI_Optimize" value="1" />
+ <parameter name="GUI_Optimize_max" value="1" />
+ <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
+ <parameter name="GUI_UNDERFLOW_CHECKING" value="false" />
+ <parameter name="GUI_UsedW" value="true" />
+ <parameter name="GUI_Width" value="8" />
+ <parameter name="GUI_dc_aclr" value="false" />
+ <parameter name="GUI_delaypipe" value="3" />
+ <parameter name="GUI_diff_widths" value="false" />
+ <parameter name="GUI_msb_usedw" value="false" />
+ <parameter name="GUI_output_width" value="8" />
+ <parameter name="GUI_read_aclr_synch" value="false" />
+ <parameter name="GUI_rsEmpty" value="true" />
+ <parameter name="GUI_rsFull" value="false" />
+ <parameter name="GUI_rsUsedW" value="false" />
+ <parameter name="GUI_sc_aclr" value="true" />
+ <parameter name="GUI_sc_sclr" value="false" />
+ <parameter name="GUI_synStage" value="3" />
+ <parameter name="GUI_write_aclr_synch" value="false" />
+ <parameter name="GUI_wsEmpty" value="false" />
+ <parameter name="GUI_wsFull" value="true" />
+ <parameter name="GUI_wsUsedW" value="false" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.vhd b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..afaf0a91d127999dd5e6364d6b87f615c66f02e2
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.vhd
@@ -0,0 +1,110 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Instantiate FIFO IP with generics
+-- Description:
+-- Copied component declaration and instance example from generated/fifo_140/sim/ip_arria10_e3sge3_fifo_sc_fifo_140_pkqwcbi.vhd
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY technology_lib;
+USE technology_lib.technology_pkg.ALL;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY ip_arria10_e3sge3_fifo_sc IS
+ GENERIC (
+ g_use_eab : STRING := "ON";
+ g_dat_w : NATURAL := 20;
+ g_nof_words : NATURAL := 1024
+ );
+ PORT (
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdreq : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ full : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0) ;
+ usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+END ip_arria10_e3sge3_fifo_sc;
+
+
+ARCHITECTURE SYN OF ip_arria10_e3sge3_fifo_sc IS
+
+ COMPONENT scfifo
+ GENERIC (
+ add_ram_output_register : STRING;
+ intended_device_family : STRING;
+ lpm_numwords : NATURAL;
+ lpm_showahead : STRING;
+ lpm_type : STRING;
+ lpm_width : NATURAL;
+ lpm_widthu : NATURAL;
+ overflow_checking : STRING;
+ underflow_checking : STRING;
+ use_eab : STRING
+ );
+ PORT (
+ aclr : IN STD_LOGIC;
+ clock : IN STD_LOGIC;
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdreq : IN STD_LOGIC;
+ wrreq : IN STD_LOGIC;
+ empty : OUT STD_LOGIC;
+ full : OUT STD_LOGIC;
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ usedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
+ );
+ END COMPONENT;
+
+BEGIN
+
+ u_scfifo : scfifo
+ GENERIC MAP (
+ add_ram_output_register => "ON",
+ intended_device_family => "Arria 10",
+ lpm_numwords => g_nof_words,
+ lpm_showahead => "OFF",
+ lpm_type => "scfifo",
+ lpm_width => g_dat_w,
+ lpm_widthu => tech_ceil_log2(g_nof_words),
+ overflow_checking => "ON",
+ underflow_checking => "ON",
+ use_eab => g_use_eab
+ )
+ PORT MAP (
+ aclr => aclr,
+ clock => clock,
+ data => data,
+ rdreq => rdreq,
+ wrreq => wrreq,
+ empty => empty,
+ full => full,
+ q => q,
+ usedw => usedw
+ );
+
+END SYN;
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b045f247c54a99e9e74fdab64f4547aa90c3b357
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
@@ -0,0 +1,34 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generated/sim"
+
+vmap ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151 ./work/
+
+vlog "$IP_DIR/../altera_asmi_parallel_151/sim/ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151_27ndfba.v" -work ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151
+vcom "$IP_DIR/ip_arria10_e1sg_asmi_parallel.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..c5d32303594607539ab7115f55e9094052c50054
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_asmi_parallel.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..aeecf8db0a13a74623288cc21ba4ce84c668a432
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_asmi_parallel
+hdl_library_clause_name = ip_arria10_e1sg_asmi_parallel_altera_asmi_parallel_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_asmi_parallel.qip
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/ip_arria10_e1sg_asmi_parallel.qsys b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/ip_arria10_e1sg_asmi_parallel.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..66b7c4486f2b32b9f28ee238ce1e7a0f4b6f104b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/ip_arria10_e1sg_asmi_parallel.qsys
@@ -0,0 +1,177 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_asmi_parallel">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element asmi_parallel_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="addr" internal="asmi_parallel_0.addr" type="conduit" dir="end">
+ <port name="addr" internal="addr" />
+ </interface>
+ <interface name="busy" internal="asmi_parallel_0.busy" type="conduit" dir="end">
+ <port name="busy" internal="busy" />
+ </interface>
+ <interface name="clkin" internal="asmi_parallel_0.clkin" type="clock" dir="end">
+ <port name="clkin" internal="clkin" />
+ </interface>
+ <interface
+ name="data_valid"
+ internal="asmi_parallel_0.data_valid"
+ type="conduit"
+ dir="end">
+ <port name="data_valid" internal="data_valid" />
+ </interface>
+ <interface
+ name="datain"
+ internal="asmi_parallel_0.datain"
+ type="conduit"
+ dir="end">
+ <port name="datain" internal="datain" />
+ </interface>
+ <interface
+ name="dataout"
+ internal="asmi_parallel_0.dataout"
+ type="conduit"
+ dir="end">
+ <port name="dataout" internal="dataout" />
+ </interface>
+ <interface name="die_erase" internal="asmi_parallel_0.die_erase" />
+ <interface
+ name="en4b_addr"
+ internal="asmi_parallel_0.en4b_addr"
+ type="conduit"
+ dir="end">
+ <port name="en4b_addr" internal="en4b_addr" />
+ </interface>
+ <interface
+ name="ex4b_addr"
+ internal="asmi_parallel_0.ex4b_addr"
+ type="conduit"
+ dir="end">
+ <port name="ex4b_addr" internal="ex4b_addr" />
+ </interface>
+ <interface name="fast_read" internal="asmi_parallel_0.fast_read" />
+ <interface
+ name="illegal_erase"
+ internal="asmi_parallel_0.illegal_erase"
+ type="conduit"
+ dir="end">
+ <port name="illegal_erase" internal="illegal_erase" />
+ </interface>
+ <interface
+ name="illegal_write"
+ internal="asmi_parallel_0.illegal_write"
+ type="conduit"
+ dir="end">
+ <port name="illegal_write" internal="illegal_write" />
+ </interface>
+ <interface name="rden" internal="asmi_parallel_0.rden" type="conduit" dir="end">
+ <port name="rden" internal="rden" />
+ </interface>
+ <interface name="read" internal="asmi_parallel_0.read" type="conduit" dir="end">
+ <port name="read" internal="read" />
+ </interface>
+ <interface name="reset" internal="asmi_parallel_0.reset" type="reset" dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface name="sce" internal="asmi_parallel_0.sce" type="conduit" dir="end">
+ <port name="sce" internal="sce" />
+ </interface>
+ <interface
+ name="sector_erase"
+ internal="asmi_parallel_0.sector_erase"
+ type="conduit"
+ dir="end">
+ <port name="sector_erase" internal="sector_erase" />
+ </interface>
+ <interface
+ name="shift_bytes"
+ internal="asmi_parallel_0.shift_bytes"
+ type="conduit"
+ dir="end">
+ <port name="shift_bytes" internal="shift_bytes" />
+ </interface>
+ <interface name="wren" internal="asmi_parallel_0.wren" type="conduit" dir="end">
+ <port name="wren" internal="wren" />
+ </interface>
+ <interface
+ name="write"
+ internal="asmi_parallel_0.write"
+ type="conduit"
+ dir="end">
+ <port name="write" internal="write" />
+ </interface>
+ <module
+ name="asmi_parallel_0"
+ kind="altera_asmi_parallel"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
+ <parameter name="DATA_WIDTH" value="STANDARD" />
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="ENABLE_SIM" value="false" />
+ <parameter name="EPCS_TYPE" value="EPCQL1024" />
+ <parameter name="FLASH_RSTPIN" value="FALSE" />
+ <parameter name="INTENDED_DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="PAGE_SIZE" value="256" />
+ <parameter name="WRITE_DUMMY_CLK" value="0" />
+ <parameter name="gui_bulk_erase" value="false" />
+ <parameter name="gui_die_erase" value="false" />
+ <parameter name="gui_ex4b_addr" value="true" />
+ <parameter name="gui_fast_read" value="false" />
+ <parameter name="gui_page_write" value="true" />
+ <parameter name="gui_read_address" value="false" />
+ <parameter name="gui_read_dummyclk" value="false" />
+ <parameter name="gui_read_rdid" value="false" />
+ <parameter name="gui_read_sid" value="false" />
+ <parameter name="gui_read_status" value="false" />
+ <parameter name="gui_sector_erase" value="true" />
+ <parameter name="gui_sector_protect" value="false" />
+ <parameter name="gui_single_write" value="false" />
+ <parameter name="gui_use_asmiblock" value="false" />
+ <parameter name="gui_use_eab" value="false" />
+ <parameter name="gui_wren" value="true" />
+ <parameter name="gui_write" value="true" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4632c795d4221b696d6a6b907ccfa4d6bc432dfe
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
@@ -0,0 +1,36 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/flash/remote_update/generated/sim"
+
+vmap ip_arria10_e1sg_remote_update_altera_remote_update_core_151 ./work/
+vmap ip_arria10_e1sg_remote_update_altera_remote_update_151 ./work/
+
+vlog "$IP_DIR/../altera_remote_update_core_151/sim/altera_remote_update_core.sv" -work ip_arria10_e1sg_remote_update_altera_remote_update_core_151
+vlog "$IP_DIR/../altera_remote_update_151/sim/ip_arria10_e1sg_remote_update_altera_remote_update_151_fdzfjma.v" -work ip_arria10_e1sg_remote_update_altera_remote_update_151
+vcom "$IP_DIR/ip_arria10_e1sg_remote_update.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..f9d585f8bb83069e338337a5dd7892a869ea1b72
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_remote_update.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..2e9b68cce56238309c5e475b04e8aab3cf8109a2
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_remote_update
+hdl_library_clause_name = ip_arria10_e1sg_remote_update_altera_remote_update_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_remote_update.qip
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/ip_arria10_e1sg_remote_update.qsys b/libraries/technology/ip_arria10_e1sg/flash/remote_update/ip_arria10_e1sg_remote_update.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..b2650837c6274750e2f7493d3d9f7276e81eee22
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/ip_arria10_e1sg_remote_update.qsys
@@ -0,0 +1,129 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_remote_update">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element remote_update_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="busy" internal="remote_update_0.busy" type="conduit" dir="end">
+ <port name="busy" internal="busy" />
+ </interface>
+ <interface name="clock" internal="remote_update_0.clock" type="clock" dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface
+ name="ctl_nupdt"
+ internal="remote_update_0.ctl_nupdt"
+ type="conduit"
+ dir="end">
+ <port name="ctl_nupdt" internal="ctl_nupdt" />
+ </interface>
+ <interface
+ name="data_in"
+ internal="remote_update_0.data_in"
+ type="conduit"
+ dir="end">
+ <port name="data_in" internal="data_in" />
+ </interface>
+ <interface
+ name="data_out"
+ internal="remote_update_0.data_out"
+ type="conduit"
+ dir="end">
+ <port name="data_out" internal="data_out" />
+ </interface>
+ <interface
+ name="param"
+ internal="remote_update_0.param"
+ type="conduit"
+ dir="end">
+ <port name="param" internal="param" />
+ </interface>
+ <interface
+ name="read_param"
+ internal="remote_update_0.read_param"
+ type="conduit"
+ dir="end">
+ <port name="read_param" internal="read_param" />
+ </interface>
+ <interface
+ name="reconfig"
+ internal="remote_update_0.reconfig"
+ type="conduit"
+ dir="end">
+ <port name="reconfig" internal="reconfig" />
+ </interface>
+ <interface name="reset" internal="remote_update_0.reset" type="reset" dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="reset_timer"
+ internal="remote_update_0.reset_timer"
+ type="conduit"
+ dir="end">
+ <port name="reset_timer" internal="reset_timer" />
+ </interface>
+ <interface
+ name="write_param"
+ internal="remote_update_0.write_param"
+ type="conduit"
+ dir="end">
+ <port name="write_param" internal="write_param" />
+ </interface>
+ <module
+ name="remote_update_0"
+ kind="altera_remote_update"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
+ <parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
+ <parameter name="DEVICE" value="10AX115S2F45E1SG" />
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_config_device" value="EPCQL1024" />
+ <parameter name="check_app_pof" value="false" />
+ <parameter name="check_avalon_interface" value="false" />
+ <parameter name="m_support_write_config_check" value="true" />
+ <parameter name="operation_mode" value="REMOTE" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..a64d398529413e191b164a5a64c1f2e0a13730f4
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_fractional_pll_clk125.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..56be7f5e004a5a69ad2e83203e65d186b85396ea
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_fractional_pll_clk125
+hdl_library_clause_name = ip_arria10_e1sg_fractional_pll_clk125_altera_xcvr_fpll_a10_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_fractional_pll_clk125.qip
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qsys b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..8c3d37900ef36a6f86773fe7004dd9e2f6d81242
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qsys
@@ -0,0 +1,280 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_fractional_pll_clk125">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element xcvr_fpll_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>outclk0</key>
+ <value>
+ <connectionPointName>outclk0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk1</key>
+ <value>
+ <connectionPointName>outclk1</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk2</key>
+ <value>
+ <connectionPointName>outclk2</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk3</key>
+ <value>
+ <connectionPointName>outclk3</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="hssi_pll_cascade_clk"
+ internal="xcvr_fpll_a10_0.hssi_pll_cascade_clk" />
+ <interface
+ name="outclk0"
+ internal="xcvr_fpll_a10_0.outclk0"
+ type="clock"
+ dir="start">
+ <port name="outclk0" internal="outclk0" />
+ </interface>
+ <interface
+ name="outclk1"
+ internal="xcvr_fpll_a10_0.outclk1"
+ type="clock"
+ dir="start">
+ <port name="outclk1" internal="outclk1" />
+ </interface>
+ <interface
+ name="outclk2"
+ internal="xcvr_fpll_a10_0.outclk2"
+ type="clock"
+ dir="start">
+ <port name="outclk2" internal="outclk2" />
+ </interface>
+ <interface
+ name="outclk3"
+ internal="xcvr_fpll_a10_0.outclk3"
+ type="clock"
+ dir="start">
+ <port name="outclk3" internal="outclk3" />
+ </interface>
+ <interface
+ name="pll_cal_busy"
+ internal="xcvr_fpll_a10_0.pll_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="pll_cal_busy" internal="pll_cal_busy" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="xcvr_fpll_a10_0.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="xcvr_fpll_a10_0.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_refclk0"
+ internal="xcvr_fpll_a10_0.pll_refclk0"
+ type="clock"
+ dir="end">
+ <port name="pll_refclk0" internal="pll_refclk0" />
+ </interface>
+ <interface name="tx_serial_clk" internal="xcvr_fpll_a10_0.tx_serial_clk" />
+ <module
+ name="xcvr_fpll_a10_0"
+ kind="altera_xcvr_fpll_a10"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="enable_analog_resets" value="0" />
+ <parameter name="enable_bonding_clks" value="0" />
+ <parameter name="enable_ext_lockdetect_ports" value="0" />
+ <parameter name="enable_fb_comp_bonding" value="0" />
+ <parameter name="enable_hfreq_clk" value="0" />
+ <parameter name="enable_mcgb" value="0" />
+ <parameter name="enable_mcgb_pcie_clksw" value="0" />
+ <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
+ <parameter name="enable_pll_reconfig" value="0" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="gui_actual_outclk0_frequency" value="100.0" />
+ <parameter name="gui_actual_outclk1_frequency" value="100.0" />
+ <parameter name="gui_actual_outclk2_frequency" value="100.0" />
+ <parameter name="gui_actual_outclk3_frequency" value="100.0" />
+ <parameter name="gui_actual_refclk_frequency" value="100.0" />
+ <parameter name="gui_bw_sel" value="low" />
+ <parameter name="gui_cascade_outclk_index" value="0" />
+ <parameter name="gui_desired_hssi_cascade_frequency" value="100.0" />
+ <parameter name="gui_desired_outclk0_frequency" value="20.0" />
+ <parameter name="gui_desired_outclk1_frequency" value="50.0" />
+ <parameter name="gui_desired_outclk2_frequency" value="100.0" />
+ <parameter name="gui_desired_outclk3_frequency" value="125.0" />
+ <parameter name="gui_desired_refclk_frequency" value="200.0" />
+ <parameter name="gui_enable_active_clk" value="false" />
+ <parameter name="gui_enable_cascade_out" value="false" />
+ <parameter name="gui_enable_clk_bad" value="false" />
+ <parameter name="gui_enable_dps" value="false" />
+ <parameter name="gui_enable_fractional" value="false" />
+ <parameter name="gui_enable_hip_cal_done_port" value="0" />
+ <parameter name="gui_enable_manual_config" value="false" />
+ <parameter name="gui_enable_manual_hssi_counters" value="false" />
+ <parameter name="gui_enable_phase_alignment" value="false" />
+ <parameter name="gui_enable_pld_cal_busy_port" value="1" />
+ <parameter name="gui_fpll_mode" value="0" />
+ <parameter name="gui_fractional_x" value="32" />
+ <parameter name="gui_hip_cal_en" value="0" />
+ <parameter name="gui_hssi_output_clock_frequency" value="1250.0" />
+ <parameter name="gui_hssi_prot_mode" value="0" />
+ <parameter name="gui_iqtxrxclk_outclk_index" value="0" />
+ <parameter name="gui_number_of_output_clocks" value="4" />
+ <parameter name="gui_operation_mode" value="0" />
+ <parameter name="gui_outclk0_actual_phase_shift" value="0.0" />
+ <parameter name="gui_outclk0_actual_phase_shift_deg" value="0.0" />
+ <parameter name="gui_outclk0_desired_phase_shift" value="0.0" />
+ <parameter name="gui_outclk0_phase_shift_unit" value="0" />
+ <parameter name="gui_outclk1_actual_phase_shift" value="0.0" />
+ <parameter name="gui_outclk1_actual_phase_shift_deg" value="0.0" />
+ <parameter name="gui_outclk1_desired_phase_shift" value="0" />
+ <parameter name="gui_outclk1_phase_shift_unit" value="0" />
+ <parameter name="gui_outclk2_actual_phase_shift" value="0 ps" />
+ <parameter name="gui_outclk2_actual_phase_shift_deg" value="0 deg" />
+ <parameter name="gui_outclk2_desired_phase_shift" value="0" />
+ <parameter name="gui_outclk2_phase_shift_unit" value="0" />
+ <parameter name="gui_outclk3_actual_phase_shift" value="0.0" />
+ <parameter name="gui_outclk3_actual_phase_shift_deg" value="0.0" />
+ <parameter name="gui_outclk3_desired_phase_shift" value="0" />
+ <parameter name="gui_outclk3_phase_shift_unit" value="0" />
+ <parameter name="gui_pll_c_counter_0" value="1" />
+ <parameter name="gui_pll_c_counter_1" value="1" />
+ <parameter name="gui_pll_c_counter_2" value="1" />
+ <parameter name="gui_pll_c_counter_3" value="1" />
+ <parameter name="gui_pll_dsm_fractional_division" value="1" />
+ <parameter name="gui_pll_m_counter" value="1" />
+ <parameter name="gui_pll_n_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_k_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_l_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_m_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_n_counter" value="1" />
+ <parameter name="gui_refclk1_frequency" value="100.0" />
+ <parameter name="gui_refclk_cnt" value="1" />
+ <parameter name="gui_refclk_index" value="0" />
+ <parameter name="gui_refclk_switch" value="false" />
+ <parameter name="gui_reference_clock_frequency" value="125.0" />
+ <parameter name="gui_self_reset_enabled" value="false" />
+ <parameter name="gui_switchover_delay" value="0" />
+ <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+ <parameter name="mcgb_aux_clkin_cnt" value="0" />
+ <parameter name="mcgb_div" value="1" />
+ <parameter name="phase_alignment_check_var" value="false" />
+ <parameter name="pma_width" value="64" />
+ <parameter name="rcfg_debug" value="0" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_fpll_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="0" />
+ <parameter name="rcfg_mif_file_enable" value="0" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_data0" value="" />
+ <parameter name="rcfg_profile_data1" value="" />
+ <parameter name="rcfg_profile_data2" value="" />
+ <parameter name="rcfg_profile_data3" value="" />
+ <parameter name="rcfg_profile_data4" value="" />
+ <parameter name="rcfg_profile_data5" value="" />
+ <parameter name="rcfg_profile_data6" value="" />
+ <parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_sv_file_enable" value="0" />
+ <parameter name="rcfg_txt_file_enable" value="0" />
+ <parameter name="set_altera_xcvr_fpll_a10_calibration_en" value="1" />
+ <parameter name="set_capability_reg_enable" value="0" />
+ <parameter name="set_csr_soft_logic_enable" value="0" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="silicon_rev" value="false" />
+ <parameter name="support_mode" value="user_mode" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..10802670a735484a08fb1aca9eb9bc54aed6a010
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_fractional_pll_clk200.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..752ee0e48f66aae3590e43a7e082f0ed7a72b809
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_fractional_pll_clk200
+hdl_library_clause_name = ip_arria10_e1sg_fractional_pll_clk200_altera_xcvr_fpll_a10_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_fractional_pll_clk200.qip
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qsys b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..774f211521577be9a1f4d32af420e403e1be7225
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qsys
@@ -0,0 +1,260 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_fractional_pll_clk200">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element xcvr_fpll_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>outclk0</key>
+ <value>
+ <connectionPointName>outclk0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk1</key>
+ <value>
+ <connectionPointName>outclk1</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk2</key>
+ <value>
+ <connectionPointName>outclk2</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="hssi_pll_cascade_clk"
+ internal="xcvr_fpll_a10_0.hssi_pll_cascade_clk" />
+ <interface
+ name="outclk0"
+ internal="xcvr_fpll_a10_0.outclk0"
+ type="clock"
+ dir="start">
+ <port name="outclk0" internal="outclk0" />
+ </interface>
+ <interface
+ name="outclk1"
+ internal="xcvr_fpll_a10_0.outclk1"
+ type="clock"
+ dir="start">
+ <port name="outclk1" internal="outclk1" />
+ </interface>
+ <interface
+ name="outclk2"
+ internal="xcvr_fpll_a10_0.outclk2"
+ type="clock"
+ dir="start">
+ <port name="outclk2" internal="outclk2" />
+ </interface>
+ <interface
+ name="pll_cal_busy"
+ internal="xcvr_fpll_a10_0.pll_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="pll_cal_busy" internal="pll_cal_busy" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="xcvr_fpll_a10_0.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="xcvr_fpll_a10_0.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_refclk0"
+ internal="xcvr_fpll_a10_0.pll_refclk0"
+ type="clock"
+ dir="end">
+ <port name="pll_refclk0" internal="pll_refclk0" />
+ </interface>
+ <interface name="tx_serial_clk" internal="xcvr_fpll_a10_0.tx_serial_clk" />
+ <module
+ name="xcvr_fpll_a10_0"
+ kind="altera_xcvr_fpll_a10"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="enable_analog_resets" value="0" />
+ <parameter name="enable_bonding_clks" value="0" />
+ <parameter name="enable_ext_lockdetect_ports" value="0" />
+ <parameter name="enable_fb_comp_bonding" value="0" />
+ <parameter name="enable_hfreq_clk" value="0" />
+ <parameter name="enable_mcgb" value="0" />
+ <parameter name="enable_mcgb_pcie_clksw" value="0" />
+ <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
+ <parameter name="enable_pll_reconfig" value="0" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="gui_actual_outclk0_frequency" value="100.0" />
+ <parameter name="gui_actual_outclk1_frequency" value="100.0" />
+ <parameter name="gui_actual_outclk2_frequency" value="100.0" />
+ <parameter name="gui_actual_outclk3_frequency" value="100.0" />
+ <parameter name="gui_actual_refclk_frequency" value="100.0" />
+ <parameter name="gui_bw_sel" value="low" />
+ <parameter name="gui_cascade_outclk_index" value="0" />
+ <parameter name="gui_desired_hssi_cascade_frequency" value="100.0" />
+ <parameter name="gui_desired_outclk0_frequency" value="200.0" />
+ <parameter name="gui_desired_outclk1_frequency" value="200.0" />
+ <parameter name="gui_desired_outclk2_frequency" value="400.0" />
+ <parameter name="gui_desired_outclk3_frequency" value="100.0" />
+ <parameter name="gui_desired_refclk_frequency" value="200.0" />
+ <parameter name="gui_enable_active_clk" value="false" />
+ <parameter name="gui_enable_cascade_out" value="false" />
+ <parameter name="gui_enable_clk_bad" value="false" />
+ <parameter name="gui_enable_dps" value="false" />
+ <parameter name="gui_enable_fractional" value="false" />
+ <parameter name="gui_enable_hip_cal_done_port" value="0" />
+ <parameter name="gui_enable_manual_config" value="false" />
+ <parameter name="gui_enable_manual_hssi_counters" value="false" />
+ <parameter name="gui_enable_phase_alignment" value="false" />
+ <parameter name="gui_enable_pld_cal_busy_port" value="1" />
+ <parameter name="gui_fpll_mode" value="0" />
+ <parameter name="gui_fractional_x" value="32" />
+ <parameter name="gui_hip_cal_en" value="0" />
+ <parameter name="gui_hssi_output_clock_frequency" value="1250.0" />
+ <parameter name="gui_hssi_prot_mode" value="0" />
+ <parameter name="gui_iqtxrxclk_outclk_index" value="0" />
+ <parameter name="gui_number_of_output_clocks" value="3" />
+ <parameter name="gui_operation_mode" value="0" />
+ <parameter name="gui_outclk0_actual_phase_shift" value="0.0" />
+ <parameter name="gui_outclk0_actual_phase_shift_deg" value="0.0" />
+ <parameter name="gui_outclk0_desired_phase_shift" value="0.0" />
+ <parameter name="gui_outclk0_phase_shift_unit" value="0" />
+ <parameter name="gui_outclk1_actual_phase_shift" value="0.0" />
+ <parameter name="gui_outclk1_actual_phase_shift_deg" value="0.0" />
+ <parameter name="gui_outclk1_desired_phase_shift" value="90" />
+ <parameter name="gui_outclk1_phase_shift_unit" value="0" />
+ <parameter name="gui_outclk2_actual_phase_shift" value="0 ps" />
+ <parameter name="gui_outclk2_actual_phase_shift_deg" value="0 deg" />
+ <parameter name="gui_outclk2_desired_phase_shift" value="0" />
+ <parameter name="gui_outclk2_phase_shift_unit" value="0" />
+ <parameter name="gui_outclk3_actual_phase_shift" value="0.0" />
+ <parameter name="gui_outclk3_actual_phase_shift_deg" value="0.0" />
+ <parameter name="gui_outclk3_desired_phase_shift" value="0" />
+ <parameter name="gui_outclk3_phase_shift_unit" value="0" />
+ <parameter name="gui_pll_c_counter_0" value="1" />
+ <parameter name="gui_pll_c_counter_1" value="1" />
+ <parameter name="gui_pll_c_counter_2" value="1" />
+ <parameter name="gui_pll_c_counter_3" value="1" />
+ <parameter name="gui_pll_dsm_fractional_division" value="1" />
+ <parameter name="gui_pll_m_counter" value="1" />
+ <parameter name="gui_pll_n_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_k_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_l_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_m_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_n_counter" value="1" />
+ <parameter name="gui_refclk1_frequency" value="100.0" />
+ <parameter name="gui_refclk_cnt" value="1" />
+ <parameter name="gui_refclk_index" value="0" />
+ <parameter name="gui_refclk_switch" value="false" />
+ <parameter name="gui_reference_clock_frequency" value="200.0" />
+ <parameter name="gui_self_reset_enabled" value="false" />
+ <parameter name="gui_switchover_delay" value="0" />
+ <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+ <parameter name="mcgb_aux_clkin_cnt" value="0" />
+ <parameter name="mcgb_div" value="1" />
+ <parameter name="phase_alignment_check_var" value="false" />
+ <parameter name="pma_width" value="64" />
+ <parameter name="rcfg_debug" value="0" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_fpll_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="0" />
+ <parameter name="rcfg_mif_file_enable" value="0" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_data0" value="" />
+ <parameter name="rcfg_profile_data1" value="" />
+ <parameter name="rcfg_profile_data2" value="" />
+ <parameter name="rcfg_profile_data3" value="" />
+ <parameter name="rcfg_profile_data4" value="" />
+ <parameter name="rcfg_profile_data5" value="" />
+ <parameter name="rcfg_profile_data6" value="" />
+ <parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_sv_file_enable" value="0" />
+ <parameter name="rcfg_txt_file_enable" value="0" />
+ <parameter name="set_altera_xcvr_fpll_a10_calibration_en" value="1" />
+ <parameter name="set_capability_reg_enable" value="0" />
+ <parameter name="set_csr_soft_logic_enable" value="0" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="silicon_rev" value="false" />
+ <parameter name="support_mode" value="user_mode" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/generate-all-ip.sh b/libraries/technology/ip_arria10_e1sg/generate-all-ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..751252234cd571815e8517b51c5cec54144fe231
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/generate-all-ip.sh
@@ -0,0 +1,21 @@
+#!/bin/bash
+
+files=`find . -name 'generate_ip.sh' `
+
+echo -e "About to generate the following IP blocks:\n$files\n"
+
+for f in $files ; do
+ cd `dirname $f`
+
+ echo
+ echo -n "Entering directory: "
+ pwd
+ echo
+
+ rm -rf generated
+ ./`basename $f`
+
+ cd -
+done
+
+echo "Done"
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt b/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..39766e46ccf196734329497a8fd824781a9b3fc1
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
@@ -0,0 +1,55 @@
+README.txt for $RADIOHDL/libraries/technology/ip_arria10/mac_10g
+
+1) Porting
+2) IP component
+3) Compilation, simulation and verification
+4) Synthesis
+5) Remarks
+
+
+1) Porting
+
+The mac_10g IP was ported manually from Quartus v11.1 for Stratix IV to Quartus 14.0a10 for Arria10 by creating it in Qsys using
+the same parameter settings.
+
+
+2) IP component
+
+The generated IP is not kept in SVN, only the Qsys source file:
+
+ ip_arria10_mac_10g.qsys
+
+Therefore first the IP needs to be generated using:
+
+ ./generate_ip.sh
+
+
+3) Compilation, simulation and verification
+
+The genrated IP also contains a msim_setup.tcl file that was used to manually create:
+
+ compile_ip.tcl
+
+This compile_ip.tcl is in the hdllib.cfg and gets compiled before the other code.
+
+
+4) Synthesis
+
+No synthesis trials were done, because this will implicitely be done when the IP is used in a design. The QIP file:
+
+ generated/ip_arria10_mac_10g.qip
+
+is included in the hdllib.cfg and contains what is needed to synthesize the IP.
+
+
+5) Remarks
+
+a) Use generated IP specific library clause name
+
+ The generated ip_arria10_<lib_name>.vhd uses an IP specific library name. Therefore the hdllib.cfg uses the IP
+ specific library as library claus name to make it known:
+
+ hdl_lib_name = ip_arria10_<lib_name>
+ hdl_library_clause_name = ip_arria10_<lib_name>_<ip_specific>
+
+
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..510c550c2cde57fafd8285beecd7edfdd9c5c951
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/generate_ip.sh
@@ -0,0 +1,56 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2a" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_mac_10g.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
+
+# Also generate the testbench IP, but that appears not useful, because:
+# - the ip_arria10_mac_10g_tb.vhd does not apply stimuli to the MM, ST and XGMII interfaces
+# - the stimuli for the clocks seem wrong, because the period is 20 us.
+#qsys-generate ip_arria10_e1sg_mac_10g.qsys \
+# --synthesis=VHDL \
+# --simulation=VHDL \
+# --testbench=STANDARD \
+# --testbench-simulation=VHDL \
+# --output-directory=generated \
+# --allow-mixed-language-simulation \
+# --allow-mixed-language-testbench-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..e03e0207f1a7ff892486b764eef1530f476a8982
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
@@ -0,0 +1,22 @@
+hdl_lib_name = ip_arria10_e1sg_mac_10g
+hdl_library_clause_name = ip_arria10_e1sg_mac_10g_alt_em10g32_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+ # The generated testbench is listed here to create a simulation configuration for it. However
+ # the tb is commented because it is not useful, see generate_ip.sh.
+ #$RADIOHDL/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_mac_10g.qip
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/ip_arria10_e1sg_mac_10g.qsys b/libraries/technology/ip_arria10_e1sg/mac_10g/ip_arria10_e1sg_mac_10g.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..01309ddc4cf5b90df6e59b682dc59fc475e9afa1
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/ip_arria10_e1sg_mac_10g.qsys
@@ -0,0 +1,266 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_mac_10g">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element alt_em10g32_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>csr</key>
+ <value>
+ <connectionPointName>csr</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='csr' start='0x0' end='0x8000' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>15</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="avalon_st_pause"
+ internal="alt_em10g32_0.avalon_st_pause"
+ type="avalon_streaming"
+ dir="end">
+ <port name="avalon_st_pause_data" internal="avalon_st_pause_data" />
+ </interface>
+ <interface
+ name="avalon_st_rx"
+ internal="alt_em10g32_0.avalon_st_rx"
+ type="avalon_streaming"
+ dir="start">
+ <port name="avalon_st_rx_data" internal="avalon_st_rx_data" />
+ <port name="avalon_st_rx_empty" internal="avalon_st_rx_empty" />
+ <port name="avalon_st_rx_endofpacket" internal="avalon_st_rx_endofpacket" />
+ <port name="avalon_st_rx_error" internal="avalon_st_rx_error" />
+ <port name="avalon_st_rx_ready" internal="avalon_st_rx_ready" />
+ <port
+ name="avalon_st_rx_startofpacket"
+ internal="avalon_st_rx_startofpacket" />
+ <port name="avalon_st_rx_valid" internal="avalon_st_rx_valid" />
+ </interface>
+ <interface
+ name="avalon_st_rxstatus"
+ internal="alt_em10g32_0.avalon_st_rxstatus"
+ type="avalon_streaming"
+ dir="start">
+ <port name="avalon_st_rxstatus_data" internal="avalon_st_rxstatus_data" />
+ <port name="avalon_st_rxstatus_error" internal="avalon_st_rxstatus_error" />
+ <port name="avalon_st_rxstatus_valid" internal="avalon_st_rxstatus_valid" />
+ </interface>
+ <interface
+ name="avalon_st_tx"
+ internal="alt_em10g32_0.avalon_st_tx"
+ type="avalon_streaming"
+ dir="end">
+ <port name="avalon_st_tx_data" internal="avalon_st_tx_data" />
+ <port name="avalon_st_tx_empty" internal="avalon_st_tx_empty" />
+ <port name="avalon_st_tx_endofpacket" internal="avalon_st_tx_endofpacket" />
+ <port name="avalon_st_tx_error" internal="avalon_st_tx_error" />
+ <port name="avalon_st_tx_ready" internal="avalon_st_tx_ready" />
+ <port
+ name="avalon_st_tx_startofpacket"
+ internal="avalon_st_tx_startofpacket" />
+ <port name="avalon_st_tx_valid" internal="avalon_st_tx_valid" />
+ </interface>
+ <interface
+ name="avalon_st_txstatus"
+ internal="alt_em10g32_0.avalon_st_txstatus"
+ type="avalon_streaming"
+ dir="start">
+ <port name="avalon_st_txstatus_data" internal="avalon_st_txstatus_data" />
+ <port name="avalon_st_txstatus_error" internal="avalon_st_txstatus_error" />
+ <port name="avalon_st_txstatus_valid" internal="avalon_st_txstatus_valid" />
+ </interface>
+ <interface name="csr" internal="alt_em10g32_0.csr" type="avalon" dir="end">
+ <port name="csr_address" internal="csr_address" />
+ <port name="csr_read" internal="csr_read" />
+ <port name="csr_readdata" internal="csr_readdata" />
+ <port name="csr_waitrequest" internal="csr_waitrequest" />
+ <port name="csr_write" internal="csr_write" />
+ <port name="csr_writedata" internal="csr_writedata" />
+ </interface>
+ <interface
+ name="csr_clk"
+ internal="alt_em10g32_0.csr_clk"
+ type="clock"
+ dir="end">
+ <port name="csr_clk" internal="csr_clk" />
+ </interface>
+ <interface
+ name="csr_rst_n"
+ internal="alt_em10g32_0.csr_rst_n"
+ type="reset"
+ dir="end">
+ <port name="csr_rst_n" internal="csr_rst_n" />
+ </interface>
+ <interface
+ name="link_fault_status_xgmii_rx"
+ internal="alt_em10g32_0.link_fault_status_xgmii_rx"
+ type="avalon_streaming"
+ dir="start">
+ <port
+ name="link_fault_status_xgmii_rx_data"
+ internal="link_fault_status_xgmii_rx_data" />
+ </interface>
+ <interface
+ name="rx_156_25_clk"
+ internal="alt_em10g32_0.rx_156_25_clk"
+ type="clock"
+ dir="end">
+ <port name="rx_156_25_clk" internal="rx_156_25_clk" />
+ </interface>
+ <interface
+ name="rx_312_5_clk"
+ internal="alt_em10g32_0.rx_312_5_clk"
+ type="clock"
+ dir="end">
+ <port name="rx_312_5_clk" internal="rx_312_5_clk" />
+ </interface>
+ <interface
+ name="rx_rst_n"
+ internal="alt_em10g32_0.rx_rst_n"
+ type="reset"
+ dir="end">
+ <port name="rx_rst_n" internal="rx_rst_n" />
+ </interface>
+ <interface
+ name="tx_156_25_clk"
+ internal="alt_em10g32_0.tx_156_25_clk"
+ type="clock"
+ dir="end">
+ <port name="tx_156_25_clk" internal="tx_156_25_clk" />
+ </interface>
+ <interface
+ name="tx_312_5_clk"
+ internal="alt_em10g32_0.tx_312_5_clk"
+ type="clock"
+ dir="end">
+ <port name="tx_312_5_clk" internal="tx_312_5_clk" />
+ </interface>
+ <interface
+ name="tx_rst_n"
+ internal="alt_em10g32_0.tx_rst_n"
+ type="reset"
+ dir="end">
+ <port name="tx_rst_n" internal="tx_rst_n" />
+ </interface>
+ <interface
+ name="unidirectional"
+ internal="alt_em10g32_0.unidirectional"
+ type="conduit"
+ dir="end">
+ <port name="unidirectional_en" internal="unidirectional_en" />
+ <port
+ name="unidirectional_force_remote_fault"
+ internal="unidirectional_force_remote_fault" />
+ <port
+ name="unidirectional_remote_fault_dis"
+ internal="unidirectional_remote_fault_dis" />
+ </interface>
+ <interface
+ name="xgmii_rx"
+ internal="alt_em10g32_0.xgmii_rx"
+ type="avalon_streaming"
+ dir="end">
+ <port name="xgmii_rx" internal="xgmii_rx" />
+ </interface>
+ <interface name="xgmii_rx_control" internal="alt_em10g32_0.xgmii_rx_control" />
+ <interface name="xgmii_rx_data" internal="alt_em10g32_0.xgmii_rx_data" />
+ <interface
+ name="xgmii_tx"
+ internal="alt_em10g32_0.xgmii_tx"
+ type="avalon_streaming"
+ dir="start">
+ <port name="xgmii_tx" internal="xgmii_tx" />
+ </interface>
+ <interface name="xgmii_tx_control" internal="alt_em10g32_0.xgmii_tx_control" />
+ <interface name="xgmii_tx_data" internal="alt_em10g32_0.xgmii_tx_data" />
+ <module
+ name="alt_em10g32_0"
+ kind="alt_em10g32"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="DATAPATH_OPTION" value="3" />
+ <parameter name="DEVICE" value="10AX115S2F45E1SG" />
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="DEVKIT_DEVICE" value="10AX115S4F45E3SGE3" />
+ <parameter name="ENABLE_10GBASER_REG_MODE" value="0" />
+ <parameter name="ENABLE_1G10G_MAC" value="0" />
+ <parameter name="ENABLE_ED_FILESET_SIM" value="1" />
+ <parameter name="ENABLE_ED_FILESET_SYNTHESIS" value="1" />
+ <parameter name="ENABLE_MEM_ECC" value="0" />
+ <parameter name="ENABLE_PFC" value="0" />
+ <parameter name="ENABLE_PTP_1STEP" value="0" />
+ <parameter name="ENABLE_SUPP_ADDR" value="0" />
+ <parameter name="ENABLE_TIMESTAMPING" value="0" />
+ <parameter name="ENABLE_UNIDIRECTIONAL" value="1" />
+ <parameter name="INSERT_CSR_ADAPTOR" value="1" />
+ <parameter name="INSERT_ST_ADAPTOR" value="1" />
+ <parameter name="INSERT_XGMII_ADAPTOR" value="1" />
+ <parameter name="INSTANTIATE_STATISTICS" value="0" />
+ <parameter name="PFC_PRIORITY_NUMBER" value="8" />
+ <parameter name="PREAMBLE_PASSTHROUGH" value="0" />
+ <parameter name="QSF_PATH">LL10G_Ethernet_A10_10GBASER/</parameter>
+ <parameter name="REGISTER_BASED_STATISTICS" value="0" />
+ <parameter name="SELECT_CUSTOM_DEVICE" value="1" />
+ <parameter name="SELECT_ED_FILESET" value="0" />
+ <parameter name="SELECT_NUMBER_OF_CHANNEL" value="1" />
+ <parameter name="SELECT_SUPPORTED_VARIANT" value="10" />
+ <parameter name="SELECT_TARGETED_DEVICE" value="0" />
+ <parameter name="SHOW_HIDDEN_OPTIONS" value="0" />
+ <parameter name="TIME_OF_DAY_FORMAT" value="2" />
+ <parameter name="TSTAMP_FP_WIDTH" value="4" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..7e679ec72fb2adcb72f24126a5787db94a765e6b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_mult_add4.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/mult_add4/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..762c5bdef325fd0924bf91a9cb663c25904da25d
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/hdllib.cfg
@@ -0,0 +1,16 @@
+hdl_lib_name = ip_arria10_e1sg_mult_add4
+hdl_library_clause_name = ip_arria10_e1sg_mult_add4_lib
+hdl_lib_uses_synth = technology common
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+ ip_arria10_e1sg_mult_add4_rtl.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4.qsys b/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..e0898cc213cb8769ce0c05ec08d39e8c629656a3
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4.qsys
@@ -0,0 +1,215 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_mult_add4">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element mult_add_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="aclr0" internal="mult_add_0.aclr0" type="conduit" dir="end">
+ <port name="aclr0" internal="aclr0" />
+ </interface>
+ <interface name="clock0" internal="mult_add_0.clock0" type="conduit" dir="end">
+ <port name="clock0" internal="clock0" />
+ </interface>
+ <interface name="dataa_0" internal="mult_add_0.dataa_0" type="conduit" dir="end">
+ <port name="dataa_0" internal="dataa_0" />
+ </interface>
+ <interface name="dataa_1" internal="mult_add_0.dataa_1" type="conduit" dir="end">
+ <port name="dataa_1" internal="dataa_1" />
+ </interface>
+ <interface name="dataa_2" internal="mult_add_0.dataa_2" type="conduit" dir="end">
+ <port name="dataa_2" internal="dataa_2" />
+ </interface>
+ <interface name="dataa_3" internal="mult_add_0.dataa_3" type="conduit" dir="end">
+ <port name="dataa_3" internal="dataa_3" />
+ </interface>
+ <interface name="datab_0" internal="mult_add_0.datab_0" type="conduit" dir="end">
+ <port name="datab_0" internal="datab_0" />
+ </interface>
+ <interface name="datab_1" internal="mult_add_0.datab_1" type="conduit" dir="end">
+ <port name="datab_1" internal="datab_1" />
+ </interface>
+ <interface name="datab_2" internal="mult_add_0.datab_2" type="conduit" dir="end">
+ <port name="datab_2" internal="datab_2" />
+ </interface>
+ <interface name="datab_3" internal="mult_add_0.datab_3" type="conduit" dir="end">
+ <port name="datab_3" internal="datab_3" />
+ </interface>
+ <interface name="datac_0" internal="mult_add_0.datac_0" />
+ <interface name="datac_1" internal="mult_add_0.datac_1" />
+ <interface name="datac_2" internal="mult_add_0.datac_2" />
+ <interface name="datac_3" internal="mult_add_0.datac_3" />
+ <interface name="ena0" internal="mult_add_0.ena0" type="conduit" dir="end">
+ <port name="ena0" internal="ena0" />
+ </interface>
+ <interface name="result" internal="mult_add_0.result" type="conduit" dir="end">
+ <port name="result" internal="result" />
+ </interface>
+ <module
+ name="mult_add_0"
+ kind="altera_mult_add"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="accum_direction" value="ADD" />
+ <parameter name="accumulator" value="NO" />
+ <parameter name="chainout_adder" value="NO" />
+ <parameter name="chainout_adder_direction" value="ADD" />
+ <parameter name="coef0_0" value="0" />
+ <parameter name="coef0_1" value="0" />
+ <parameter name="coef0_2" value="0" />
+ <parameter name="coef0_3" value="0" />
+ <parameter name="coef0_4" value="0" />
+ <parameter name="coef0_5" value="0" />
+ <parameter name="coef0_6" value="0" />
+ <parameter name="coef0_7" value="0" />
+ <parameter name="coef1_0" value="0" />
+ <parameter name="coef1_1" value="0" />
+ <parameter name="coef1_2" value="0" />
+ <parameter name="coef1_3" value="0" />
+ <parameter name="coef1_4" value="0" />
+ <parameter name="coef1_5" value="0" />
+ <parameter name="coef1_6" value="0" />
+ <parameter name="coef1_7" value="0" />
+ <parameter name="coef2_0" value="0" />
+ <parameter name="coef2_1" value="0" />
+ <parameter name="coef2_2" value="0" />
+ <parameter name="coef2_3" value="0" />
+ <parameter name="coef2_4" value="0" />
+ <parameter name="coef2_5" value="0" />
+ <parameter name="coef2_6" value="0" />
+ <parameter name="coef2_7" value="0" />
+ <parameter name="coef3_0" value="0" />
+ <parameter name="coef3_1" value="0" />
+ <parameter name="coef3_2" value="0" />
+ <parameter name="coef3_3" value="0" />
+ <parameter name="coef3_4" value="0" />
+ <parameter name="coef3_5" value="0" />
+ <parameter name="coef3_6" value="0" />
+ <parameter name="coef3_7" value="0" />
+ <parameter name="gui_4th_asynchronous_clear" value="false" />
+ <parameter name="gui_accum_sload_register_aclr" value="NONE" />
+ <parameter name="gui_accum_sload_register_clock" value="CLOCK0" />
+ <parameter name="gui_accum_sload_register_sclr" value="NONE" />
+ <parameter name="gui_accumulate_port_select" value="0" />
+ <parameter name="gui_addnsub_multiplier_aclr1" value="NONE" />
+ <parameter name="gui_addnsub_multiplier_aclr3" value="NONE" />
+ <parameter name="gui_addnsub_multiplier_register1" value="false" />
+ <parameter name="gui_addnsub_multiplier_register1_clock" value="CLOCK0" />
+ <parameter name="gui_addnsub_multiplier_register3" value="false" />
+ <parameter name="gui_addnsub_multiplier_register3_clock" value="CLOCK0" />
+ <parameter name="gui_addnsub_multiplier_sclr1" value="NONE" />
+ <parameter name="gui_addnsub_multiplier_sclr3" value="NONE" />
+ <parameter name="gui_associated_clock_enable" value="true" />
+ <parameter name="gui_coef_register" value="false" />
+ <parameter name="gui_coef_register_aclr" value="NONE" />
+ <parameter name="gui_coef_register_clock" value="CLOCK0" />
+ <parameter name="gui_coef_register_sclr" value="NONE" />
+ <parameter name="gui_datac_input_register" value="false" />
+ <parameter name="gui_datac_input_register_aclr" value="ACLR0" />
+ <parameter name="gui_datac_input_register_clock" value="CLOCK0" />
+ <parameter name="gui_datac_input_register_sclr" value="NONE" />
+ <parameter name="gui_double_accum" value="false" />
+ <parameter name="gui_ena_preload_const" value="false" />
+ <parameter name="gui_input_latency_aclr" value="ACLR0" />
+ <parameter name="gui_input_latency_clock" value="CLOCK0" />
+ <parameter name="gui_input_latency_sclr" value="NONE" />
+ <parameter name="gui_input_register_a" value="false" />
+ <parameter name="gui_input_register_a_aclr" value="ACLR0" />
+ <parameter name="gui_input_register_a_clock" value="CLOCK0" />
+ <parameter name="gui_input_register_a_sclr" value="NONE" />
+ <parameter name="gui_input_register_b" value="false" />
+ <parameter name="gui_input_register_b_aclr" value="ACLR0" />
+ <parameter name="gui_input_register_b_clock" value="CLOCK0" />
+ <parameter name="gui_input_register_b_sclr" value="NONE" />
+ <parameter name="gui_multiplier1_direction" value="ADD" />
+ <parameter name="gui_multiplier3_direction" value="ADD" />
+ <parameter name="gui_multiplier_a_input" value="Multiplier input" />
+ <parameter name="gui_multiplier_b_input" value="Multiplier input" />
+ <parameter name="gui_multiplier_register" value="false" />
+ <parameter name="gui_multiplier_register_aclr" value="NONE" />
+ <parameter name="gui_multiplier_register_clock" value="CLOCK0" />
+ <parameter name="gui_multiplier_register_sclr" value="NONE" />
+ <parameter name="gui_output_register" value="false" />
+ <parameter name="gui_output_register_aclr" value="NONE" />
+ <parameter name="gui_output_register_clock" value="CLOCK0" />
+ <parameter name="gui_output_register_sclr" value="NONE" />
+ <parameter name="gui_pipelining" value="1" />
+ <parameter name="gui_preadder_direction" value="ADD" />
+ <parameter name="gui_register_signa" value="false" />
+ <parameter name="gui_register_signa_aclr" value="NONE" />
+ <parameter name="gui_register_signa_clock" value="CLOCK0" />
+ <parameter name="gui_register_signa_sclr" value="NONE" />
+ <parameter name="gui_register_signb" value="false" />
+ <parameter name="gui_register_signb_aclr" value="NONE" />
+ <parameter name="gui_register_signb_clock" value="CLOCK0" />
+ <parameter name="gui_register_signb_sclr" value="NONE" />
+ <parameter name="gui_representation_a" value="SIGNED" />
+ <parameter name="gui_representation_b" value="SIGNED" />
+ <parameter name="gui_scanouta_register" value="false" />
+ <parameter name="gui_scanouta_register_aclr" value="NONE" />
+ <parameter name="gui_scanouta_register_clock" value="CLOCK0" />
+ <parameter name="gui_scanouta_register_sclr" value="NONE" />
+ <parameter name="gui_systolic_delay" value="false" />
+ <parameter name="gui_systolic_delay_aclr" value="NONE" />
+ <parameter name="gui_systolic_delay_clock" value="CLOCK0" />
+ <parameter name="gui_systolic_delay_sclr" value="NONE" />
+ <parameter name="gui_use_subnadd" value="false" />
+ <parameter name="latency" value="3" />
+ <parameter name="loadconst_value" value="64" />
+ <parameter name="negate_aclr" value="NONE" />
+ <parameter name="negate_register" value="UNREGISTERED" />
+ <parameter name="negate_sclr" value="NONE" />
+ <parameter name="number_of_multipliers" value="4" />
+ <parameter name="port_negate" value="PORT_UNUSED" />
+ <parameter name="preadder_mode" value="SIMPLE" />
+ <parameter name="reg_autovec_sim" value="false" />
+ <parameter name="selected_device_family" value="Arria 10" />
+ <parameter name="width_a" value="18" />
+ <parameter name="width_b" value="18" />
+ <parameter name="width_c" value="16" />
+ <parameter name="width_coef" value="18" />
+ <parameter name="width_result" value="38" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4_rtl.vhd b/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4e5887c11b2440a3b844dbdebe091989944eebf8
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4_rtl.vhd
@@ -0,0 +1,272 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+
+-- Function:
+-- . res = (a0 * b0 +- a1 * b1) +- (a2 * b2 +- a3 * b3)
+
+ENTITY ip_arria10_e1sg_mult_add4_rtl IS
+ GENERIC (
+ g_in_a_w : POSITIVE;
+ g_in_b_w : POSITIVE;
+ g_res_w : POSITIVE; -- g_in_a_w + g_in_b_w + log2(4)
+ g_force_dsp : BOOLEAN := TRUE; -- when TRUE resize input width to >= 18
+ g_add_sub0 : STRING := "ADD"; -- or "SUB"
+ g_add_sub1 : STRING := "ADD"; -- or "SUB"
+ g_add_sub : STRING := "ADD"; -- or "SUB" only available with rtl architecture
+ g_nof_mult : INTEGER := 4; -- fixed
+ g_pipeline_input : NATURAL := 1; -- 0 or 1
+ g_pipeline_product : NATURAL := 0; -- 0 or 1
+ g_pipeline_adder : NATURAL := 1; -- 0 or 1, first sum
+ g_pipeline_output : NATURAL := 1 -- >= 0, second sum and optional rounding
+ );
+ PORT (
+ rst : IN STD_LOGIC := '0';
+ clk : IN STD_LOGIC;
+ clken : IN STD_LOGIC := '1';
+ in_a : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
+ in_b : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
+ res : OUT STD_LOGIC_VECTOR(g_res_w-1 DOWNTO 0)
+ );
+END ip_arria10_e1sg_mult_add4_rtl;
+
+ARCHITECTURE str OF ip_arria10_e1sg_mult_add4_rtl IS
+
+ -- Extra output pipelining is only needed when g_pipeline_output > 1
+ CONSTANT c_pipeline_output : NATURAL := sel_a_b(g_pipeline_output>0, g_pipeline_output-1, 0);
+
+ -- registers
+ SIGNAL reg_a0 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL reg_b0 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL reg_a1 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL reg_b1 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL reg_a2 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL reg_b2 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL reg_a3 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL reg_b3 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL reg_prod0 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL reg_prod1 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL reg_prod2 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL reg_prod3 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL reg_sum0 : SIGNED(g_in_a_w+g_in_b_w DOWNTO 0);
+ SIGNAL reg_sum1 : SIGNED(g_in_a_w+g_in_b_w DOWNTO 0);
+ SIGNAL reg_result : SIGNED(res'RANGE);
+
+ -- combinatorial
+ SIGNAL nxt_a0 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL nxt_b0 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL nxt_a1 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL nxt_b1 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL nxt_a2 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL nxt_b2 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL nxt_a3 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL nxt_b3 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL nxt_prod0 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL nxt_prod1 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL nxt_prod2 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL nxt_prod3 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL nxt_sum0 : SIGNED(g_in_a_w+g_in_b_w DOWNTO 0);
+ SIGNAL nxt_sum1 : SIGNED(g_in_a_w+g_in_b_w DOWNTO 0);
+ SIGNAL nxt_result : SIGNED(res'RANGE);
+
+ -- the active signals
+ SIGNAL a0 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL b0 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL a1 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL b1 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL a2 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL b2 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL a3 : SIGNED(g_in_a_w-1 DOWNTO 0);
+ SIGNAL b3 : SIGNED(g_in_b_w-1 DOWNTO 0);
+ SIGNAL prod0 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL prod1 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL prod2 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL prod3 : SIGNED(g_in_a_w+g_in_b_w-1 DOWNTO 0);
+ SIGNAL sum0 : SIGNED(g_in_a_w+g_in_b_w DOWNTO 0);
+ SIGNAL sum1 : SIGNED(g_in_a_w+g_in_b_w DOWNTO 0);
+ SIGNAL sum : SIGNED(g_in_a_w+g_in_b_w+1 DOWNTO 0);
+ SIGNAL result : SIGNED(res'RANGE);
+
+BEGIN
+
+ ------------------------------------------------------------------------------
+ -- Registers
+ ------------------------------------------------------------------------------
+
+ -- Put all potential registers in a single process for optimal DSP inferrence
+ -- Use rst only if it is supported by the DSP primitive, else leave it at '0'
+ p_reg : PROCESS (rst, clk)
+ BEGIN
+ IF rising_edge(clk) THEN
+ IF rst='1' THEN
+ reg_a0 <= (OTHERS=>'0');
+ reg_b0 <= (OTHERS=>'0');
+ reg_a1 <= (OTHERS=>'0');
+ reg_b1 <= (OTHERS=>'0');
+ reg_a2 <= (OTHERS=>'0');
+ reg_b2 <= (OTHERS=>'0');
+ reg_a3 <= (OTHERS=>'0');
+ reg_b3 <= (OTHERS=>'0');
+ reg_prod0 <= (OTHERS=>'0');
+ reg_prod1 <= (OTHERS=>'0');
+ reg_prod2 <= (OTHERS=>'0');
+ reg_prod3 <= (OTHERS=>'0');
+ reg_sum0 <= (OTHERS=>'0');
+ reg_sum1 <= (OTHERS=>'0');
+ reg_result <= (OTHERS=>'0');
+ ELSIF clken='1' THEN
+ reg_a0 <= nxt_a0; -- inputs
+ reg_b0 <= nxt_b0;
+ reg_a1 <= nxt_a1;
+ reg_b1 <= nxt_b1;
+ reg_a2 <= nxt_a2;
+ reg_b2 <= nxt_b2;
+ reg_a3 <= nxt_a3;
+ reg_b3 <= nxt_b3;
+ reg_prod0 <= nxt_prod0; -- products
+ reg_prod1 <= nxt_prod1;
+ reg_prod2 <= nxt_prod2;
+ reg_prod3 <= nxt_prod3;
+ reg_sum0 <= nxt_sum0; -- first sum
+ reg_sum1 <= nxt_sum1;
+ reg_result <= nxt_result; -- result second sum after optional rounding
+ END IF;
+ END IF;
+ END PROCESS;
+
+ ------------------------------------------------------------------------------
+ -- Inputs
+ ------------------------------------------------------------------------------
+
+ nxt_a0 <= SIGNED(in_a( g_in_a_w-1 DOWNTO 0));
+ nxt_b0 <= SIGNED(in_b( g_in_b_w-1 DOWNTO 0));
+ nxt_a1 <= SIGNED(in_a(2*g_in_a_w-1 DOWNTO g_in_a_w));
+ nxt_b1 <= SIGNED(in_b(2*g_in_b_w-1 DOWNTO g_in_b_w));
+ nxt_a2 <= SIGNED(in_a(3*g_in_a_w-1 DOWNTO 2*g_in_a_w));
+ nxt_b2 <= SIGNED(in_b(3*g_in_b_w-1 DOWNTO 2*g_in_b_w));
+ nxt_a3 <= SIGNED(in_a(4*g_in_a_w-1 DOWNTO 3*g_in_a_w));
+ nxt_b3 <= SIGNED(in_b(4*g_in_b_w-1 DOWNTO 3*g_in_b_w));
+
+ no_input_reg : IF g_pipeline_input=0 GENERATE -- wired
+ a0 <= nxt_a0;
+ b0 <= nxt_b0;
+ a1 <= nxt_a1;
+ b1 <= nxt_b1;
+ a2 <= nxt_a2;
+ b2 <= nxt_b2;
+ a3 <= nxt_a3;
+ b3 <= nxt_b3;
+ END GENERATE;
+
+ gen_input_reg : IF g_pipeline_input>0 GENERATE -- register input
+ a0 <= reg_a0;
+ b0 <= reg_b0;
+ a1 <= reg_a1;
+ b1 <= reg_b1;
+ a2 <= reg_a2;
+ b2 <= reg_b2;
+ a3 <= reg_a3;
+ b3 <= reg_b3;
+ END GENERATE;
+
+ ------------------------------------------------------------------------------
+ -- Products
+ ------------------------------------------------------------------------------
+
+ nxt_prod0 <= a0 * b0;
+ nxt_prod1 <= a1 * b1;
+ nxt_prod2 <= a2 * b2;
+ nxt_prod3 <= a3 * b3;
+
+ no_product_reg : IF g_pipeline_product=0 GENERATE -- wired
+ prod0 <= nxt_prod0;
+ prod1 <= nxt_prod1;
+ prod2 <= nxt_prod2;
+ prod3 <= nxt_prod3;
+ END GENERATE;
+ gen_product_reg : IF g_pipeline_product>0 GENERATE -- register
+ prod0 <= reg_prod0;
+ prod1 <= reg_prod1;
+ prod2 <= reg_prod2;
+ prod3 <= reg_prod3;
+ END GENERATE;
+
+ ------------------------------------------------------------------------------
+ -- First sum
+ ------------------------------------------------------------------------------
+ gen_add0 : IF g_add_sub0 = "ADD" GENERATE
+ nxt_sum0 <= RESIZE_NUM(prod0, sum0'LENGTH) + prod1;
+ END GENERATE;
+ gen_sub0 : IF g_add_sub0 = "SUB" GENERATE
+ nxt_sum0 <= RESIZE_NUM(prod0, sum0'LENGTH) - prod1;
+ END GENERATE;
+
+ gen_add1 : IF g_add_sub1 = "ADD" GENERATE
+ nxt_sum1 <= RESIZE_NUM(prod2, sum1'LENGTH) + prod3;
+ END GENERATE;
+ gen_sub1 : IF g_add_sub1 = "SUB" GENERATE
+ nxt_sum1 <= RESIZE_NUM(prod2, sum1'LENGTH) - prod3;
+ END GENERATE;
+
+ -- Optinal first sum register
+ no_adder_reg : IF g_pipeline_adder=0 GENERATE -- wired
+ sum0 <= nxt_sum0;
+ sum1 <= nxt_sum1;
+ END GENERATE;
+ gen_adder_reg : IF g_pipeline_adder>0 GENERATE -- register
+ sum0 <= reg_sum0;
+ sum1 <= reg_sum1;
+ END GENERATE;
+
+
+ ------------------------------------------------------------------------------
+ -- Second sum
+ ------------------------------------------------------------------------------
+
+ -- No register for second sum, gets combined with result register
+ gen_add : IF g_add_sub = "ADD" GENERATE
+ sum <= RESIZE_NUM(sum0, sum'LENGTH) + sum1;
+ END GENERATE;
+ gen_sub : IF g_add_sub = "SUB" GENERATE
+ sum <= RESIZE_NUM(sum0, sum'LENGTH) - sum1;
+ END GENERATE;
+
+
+ ------------------------------------------------------------------------------
+ -- Result sum after optional rounding
+ ------------------------------------------------------------------------------
+
+ nxt_result <= RESIZE_NUM(sum, res'LENGTH);
+
+ no_result_reg : IF g_pipeline_output=0 GENERATE -- wired
+ result <= nxt_result;
+ END GENERATE;
+ gen_result_reg : IF g_pipeline_output>0 GENERATE -- register
+ result <= reg_result;
+ END GENERATE;
+
+ res <= STD_LOGIC_VECTOR(result);
+
+END str;
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..7f651810baa949a80b1f767b82d0dab38eb6a9c7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_phy_10gbase_r.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..74e41675d4ea37c25fcce89ba646f468f7e00c3d
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_phy_10gbase_r.qip
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qsys b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..cd8f757ab64338fc1b6e823fba9e0f41ed89fc30
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qsys
@@ -0,0 +1,596 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_phy_10gbase_r">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element xcvr_native_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="reconfig_avmm" internal="xcvr_native_a10_0.reconfig_avmm" />
+ <interface name="reconfig_clk" internal="xcvr_native_a10_0.reconfig_clk" />
+ <interface name="reconfig_reset" internal="xcvr_native_a10_0.reconfig_reset" />
+ <interface
+ name="rx_analogreset"
+ internal="xcvr_native_a10_0.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="xcvr_native_a10_0.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_cdr_refclk0"
+ internal="xcvr_native_a10_0.rx_cdr_refclk0"
+ type="conduit"
+ dir="end">
+ <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
+ </interface>
+ <interface
+ name="rx_clkout"
+ internal="xcvr_native_a10_0.rx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="rx_clkout" internal="rx_clkout" />
+ </interface>
+ <interface
+ name="rx_control"
+ internal="xcvr_native_a10_0.rx_control"
+ type="conduit"
+ dir="end">
+ <port name="rx_control" internal="rx_control" />
+ </interface>
+ <interface
+ name="rx_coreclkin"
+ internal="xcvr_native_a10_0.rx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="rx_coreclkin" internal="rx_coreclkin" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="xcvr_native_a10_0.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_enh_blk_lock"
+ internal="xcvr_native_a10_0.rx_enh_blk_lock"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
+ </interface>
+ <interface
+ name="rx_enh_data_valid"
+ internal="xcvr_native_a10_0.rx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_del"
+ internal="xcvr_native_a10_0.rx_enh_fifo_del"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_del" internal="rx_enh_fifo_del" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.rx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_empty" internal="rx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_full"
+ internal="xcvr_native_a10_0.rx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_full" internal="rx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_insert"
+ internal="xcvr_native_a10_0.rx_enh_fifo_insert"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_insert" internal="rx_enh_fifo_insert" />
+ </interface>
+ <interface
+ name="rx_enh_highber"
+ internal="xcvr_native_a10_0.rx_enh_highber"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_highber" internal="rx_enh_highber" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="xcvr_native_a10_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_is_lockedtoref"
+ internal="xcvr_native_a10_0.rx_is_lockedtoref"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtoref" internal="rx_is_lockedtoref" />
+ </interface>
+ <interface
+ name="rx_parallel_data"
+ internal="xcvr_native_a10_0.rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_parallel_data" internal="rx_parallel_data" />
+ </interface>
+ <interface
+ name="rx_prbs_done"
+ internal="xcvr_native_a10_0.rx_prbs_done"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_done" internal="rx_prbs_done" />
+ </interface>
+ <interface
+ name="rx_prbs_err"
+ internal="xcvr_native_a10_0.rx_prbs_err"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err" internal="rx_prbs_err" />
+ </interface>
+ <interface
+ name="rx_prbs_err_clr"
+ internal="xcvr_native_a10_0.rx_prbs_err_clr"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err_clr" internal="rx_prbs_err_clr" />
+ </interface>
+ <interface
+ name="rx_serial_data"
+ internal="xcvr_native_a10_0.rx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_serial_data" internal="rx_serial_data" />
+ </interface>
+ <interface
+ name="rx_seriallpbken"
+ internal="xcvr_native_a10_0.rx_seriallpbken"
+ type="conduit"
+ dir="end">
+ <port name="rx_seriallpbken" internal="rx_seriallpbken" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="xcvr_native_a10_0.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="xcvr_native_a10_0.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_clkout"
+ internal="xcvr_native_a10_0.tx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="tx_clkout" internal="tx_clkout" />
+ </interface>
+ <interface
+ name="tx_control"
+ internal="xcvr_native_a10_0.tx_control"
+ type="conduit"
+ dir="end">
+ <port name="tx_control" internal="tx_control" />
+ </interface>
+ <interface
+ name="tx_coreclkin"
+ internal="xcvr_native_a10_0.tx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="tx_coreclkin" internal="tx_coreclkin" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="xcvr_native_a10_0.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_enh_data_valid"
+ internal="xcvr_native_a10_0.tx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_empty" internal="tx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_full"
+ internal="xcvr_native_a10_0.tx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_full" internal="tx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pempty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pempty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pempty" internal="tx_enh_fifo_pempty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pfull"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pfull"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pfull" internal="tx_enh_fifo_pfull" />
+ </interface>
+ <interface
+ name="tx_err_ins"
+ internal="xcvr_native_a10_0.tx_err_ins"
+ type="conduit"
+ dir="end">
+ <port name="tx_err_ins" internal="tx_err_ins" />
+ </interface>
+ <interface
+ name="tx_parallel_data"
+ internal="xcvr_native_a10_0.tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_parallel_data" internal="tx_parallel_data" />
+ </interface>
+ <interface name="tx_pma_clkout" internal="xcvr_native_a10_0.tx_pma_clkout" />
+ <interface
+ name="tx_pma_div_clkout"
+ internal="xcvr_native_a10_0.tx_pma_div_clkout" />
+ <interface
+ name="tx_serial_clk0"
+ internal="xcvr_native_a10_0.tx_serial_clk0"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ </interface>
+ <interface
+ name="tx_serial_data"
+ internal="xcvr_native_a10_0.tx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_data" internal="tx_serial_data" />
+ </interface>
+ <interface
+ name="unused_rx_control"
+ internal="xcvr_native_a10_0.unused_rx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_control" internal="unused_rx_control" />
+ </interface>
+ <interface
+ name="unused_rx_parallel_data"
+ internal="xcvr_native_a10_0.unused_rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
+ </interface>
+ <interface
+ name="unused_tx_control"
+ internal="xcvr_native_a10_0.unused_tx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_control" internal="unused_tx_control" />
+ </interface>
+ <interface
+ name="unused_tx_parallel_data"
+ internal="xcvr_native_a10_0.unused_tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ </interface>
+ <module
+ name="xcvr_native_a10_0"
+ kind="altera_xcvr_native_a10"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="anlg_enable_rx_default_ovr" value="0" />
+ <parameter name="anlg_enable_tx_default_ovr" value="0" />
+ <parameter name="anlg_link" value="sr" />
+ <parameter name="anlg_rx_adp_ctle_acgain_4s">radp_ctle_acgain_4s_1</parameter>
+ <parameter name="anlg_rx_adp_ctle_eqz_1s_sel">radp_ctle_eqz_1s_sel_3</parameter>
+ <parameter name="anlg_rx_adp_dfe_fxtap1" value="radp_dfe_fxtap1_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap10" value="radp_dfe_fxtap10_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap11" value="radp_dfe_fxtap11_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap2" value="radp_dfe_fxtap2_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap3" value="radp_dfe_fxtap3_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap4" value="radp_dfe_fxtap4_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap5" value="radp_dfe_fxtap5_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap6" value="radp_dfe_fxtap6_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap7" value="radp_dfe_fxtap7_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap8" value="radp_dfe_fxtap8_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap9" value="radp_dfe_fxtap9_0" />
+ <parameter name="anlg_rx_adp_vga_sel" value="radp_vga_sel_2" />
+ <parameter name="anlg_rx_eq_dc_gain_trim" value="stg2_gain7" />
+ <parameter name="anlg_rx_one_stage_enable" value="s1_mode" />
+ <parameter name="anlg_rx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_analog_mode" value="user_custom" />
+ <parameter name="anlg_tx_compensation_en" value="enable" />
+ <parameter name="anlg_tx_pre_emp_sign_1st_post_tap" value="fir_post_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_2nd_post_tap" value="fir_post_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_1t" value="fir_pre_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_2t" value="fir_pre_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_1st_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_2nd_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_1t" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_2t" value="0" />
+ <parameter name="anlg_tx_slew_rate_ctrl" value="slew_r7" />
+ <parameter name="anlg_tx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_vod_output_swing_ctrl" value="0" />
+ <parameter name="anlg_voltage" value="1_1V" />
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="bonded_mode" value="not_bonded" />
+ <parameter name="cdr_refclk_cnt" value="1" />
+ <parameter name="cdr_refclk_select" value="0" />
+ <parameter name="channels" value="1" />
+ <parameter name="design_environment" value="NATIVE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="duplex_mode" value="duplex" />
+ <parameter name="enable_analog_settings" value="0" />
+ <parameter name="enable_hard_reset" value="0" />
+ <parameter name="enable_hip" value="0" />
+ <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
+ <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_port_rx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enable_port_rx_enh_blk_lock" value="1" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
+ <parameter name="enable_port_rx_enh_crc32_err" value="0" />
+ <parameter name="enable_port_rx_enh_data_valid" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_del" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_insert" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
+ <parameter name="enable_port_rx_enh_frame" value="0" />
+ <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_rx_enh_frame_lock" value="0" />
+ <parameter name="enable_port_rx_enh_highber" value="1" />
+ <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
+ <parameter name="enable_port_rx_is_lockedtodata" value="1" />
+ <parameter name="enable_port_rx_is_lockedtoref" value="1" />
+ <parameter name="enable_port_rx_pma_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_clkslip" value="0" />
+ <parameter name="enable_port_rx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_rx_polinv" value="0" />
+ <parameter name="enable_port_rx_seriallpbken" value="1" />
+ <parameter name="enable_port_rx_seriallpbken_tx" value="1" />
+ <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
+ <parameter name="enable_port_rx_std_bitslip" value="0" />
+ <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_rx_std_byterev_ena" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
+ <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_tx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_tx_enh_bitslip" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pempty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pfull" value="1" />
+ <parameter name="enable_port_tx_enh_frame" value="0" />
+ <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
+ <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_tx_pma_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_elecidle" value="0" />
+ <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_tx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_tx_pma_rxfound" value="0" />
+ <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
+ <parameter name="enable_port_tx_polinv" value="0" />
+ <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
+ <parameter name="enable_ports_adaptation" value="0" />
+ <parameter name="enable_ports_pipe_g3_analog" value="0" />
+ <parameter name="enable_ports_pipe_hclk" value="0" />
+ <parameter name="enable_ports_pipe_rx_elecidle" value="0" />
+ <parameter name="enable_ports_pipe_sw" value="0" />
+ <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
+ <parameter name="enable_ports_rx_manual_ppm" value="0" />
+ <parameter name="enable_ports_rx_prbs" value="1" />
+ <parameter name="enable_simple_interface" value="1" />
+ <parameter name="enable_skp_ports" value="0" />
+ <parameter name="enable_split_interface" value="0" />
+ <parameter name="enable_transparent_pcs" value="0" />
+ <parameter name="enh_low_latency_enable" value="0" />
+ <parameter name="enh_pcs_pma_width" value="32" />
+ <parameter name="enh_pld_pcs_width" value="66" />
+ <parameter name="enh_rx_64b66b_enable" value="1" />
+ <parameter name="enh_rx_bitslip_enable" value="0" />
+ <parameter name="enh_rx_blksync_enable" value="1" />
+ <parameter name="enh_rx_crcchk_enable" value="0" />
+ <parameter name="enh_rx_descram_enable" value="1" />
+ <parameter name="enh_rx_dispchk_enable" value="0" />
+ <parameter name="enh_rx_frmsync_enable" value="0" />
+ <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
+ <parameter name="enh_rx_krfec_err_mark_enable" value="0" />
+ <parameter name="enh_rx_krfec_err_mark_type" value="10G" />
+ <parameter name="enh_rx_polinv_enable" value="0" />
+ <parameter name="enh_rxfifo_align_del" value="0" />
+ <parameter name="enh_rxfifo_control_del" value="0" />
+ <parameter name="enh_rxfifo_mode" value="10GBase-R" />
+ <parameter name="enh_rxfifo_pempty" value="2" />
+ <parameter name="enh_rxfifo_pfull" value="23" />
+ <parameter name="enh_rxtxfifo_double_width" value="0" />
+ <parameter name="enh_tx_64b66b_enable" value="1" />
+ <parameter name="enh_tx_bitslip_enable" value="0" />
+ <parameter name="enh_tx_crcerr_enable" value="0" />
+ <parameter name="enh_tx_crcgen_enable" value="0" />
+ <parameter name="enh_tx_dispgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_burst_enable" value="0" />
+ <parameter name="enh_tx_frmgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
+ <parameter name="enh_tx_krfec_burst_err_enable" value="0" />
+ <parameter name="enh_tx_krfec_burst_err_len" value="1" />
+ <parameter name="enh_tx_polinv_enable" value="0" />
+ <parameter name="enh_tx_randomdispbit_enable" value="0" />
+ <parameter name="enh_tx_scram_enable" value="1" />
+ <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_tx_sh_err" value="0" />
+ <parameter name="enh_txfifo_mode" value="Phase compensation" />
+ <parameter name="enh_txfifo_pempty" value="2" />
+ <parameter name="enh_txfifo_pfull" value="11" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="number_physical_bonding_clocks" value="1" />
+ <parameter name="pcie_rate_match" value="Bypass" />
+ <parameter name="pcs_direct_width" value="8" />
+ <parameter name="pll_select" value="0" />
+ <parameter name="plls" value="1" />
+ <parameter name="pma_mode" value="basic" />
+ <parameter name="protocol_mode" value="teng_baser_mode" />
+ <parameter name="rcfg_enable" value="0" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="0" />
+ <parameter name="rcfg_iface_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="0" />
+ <parameter name="rcfg_mif_file_enable" value="0" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_data0" value="" />
+ <parameter name="rcfg_profile_data1" value="" />
+ <parameter name="rcfg_profile_data2" value="" />
+ <parameter name="rcfg_profile_data3" value="" />
+ <parameter name="rcfg_profile_data4" value="" />
+ <parameter name="rcfg_profile_data5" value="" />
+ <parameter name="rcfg_profile_data6" value="" />
+ <parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_shared" value="0" />
+ <parameter name="rcfg_sv_file_enable" value="0" />
+ <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
+ <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
+ <parameter name="rx_pma_dfe_fixed_taps" value="3" />
+ <parameter name="rx_pma_div_clkout_divider" value="0" />
+ <parameter name="rx_ppm_detect_threshold" value="1000" />
+ <parameter name="set_capability_reg_enable" value="0" />
+ <parameter name="set_cdr_refclk_freq" value="644.531250" />
+ <parameter name="set_csr_soft_logic_enable" value="0" />
+ <parameter name="set_data_rate" value="10312.5" />
+ <parameter name="set_disconnect_analog_resets" value="0" />
+ <parameter name="set_embedded_debug_enable" value="0" />
+ <parameter name="set_enable_calibration" value="0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_odi_soft_logic_enable" value="0" />
+ <parameter name="set_pcs_bonding_master" value="Auto" />
+ <parameter name="set_prbs_soft_logic_enable" value="0" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="std_low_latency_bypass_enable" value="0" />
+ <parameter name="std_pcs_pma_width" value="10" />
+ <parameter name="std_rx_8b10b_enable" value="0" />
+ <parameter name="std_rx_bitrev_enable" value="0" />
+ <parameter name="std_rx_byte_deser_mode" value="Disabled" />
+ <parameter name="std_rx_byterev_enable" value="0" />
+ <parameter name="std_rx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_rx_polinv_enable" value="0" />
+ <parameter name="std_rx_rmfifo_mode" value="disabled" />
+ <parameter name="std_rx_rmfifo_pattern_n" value="0" />
+ <parameter name="std_rx_rmfifo_pattern_p" value="0" />
+ <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
+ <parameter name="std_rx_word_aligner_mode" value="bitslip" />
+ <parameter name="std_rx_word_aligner_pattern" value="0" />
+ <parameter name="std_rx_word_aligner_pattern_len" value="7" />
+ <parameter name="std_rx_word_aligner_renumber" value="3" />
+ <parameter name="std_rx_word_aligner_rgnumber" value="3" />
+ <parameter name="std_rx_word_aligner_rknumber" value="3" />
+ <parameter name="std_rx_word_aligner_rvnumber" value="0" />
+ <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
+ <parameter name="std_tx_8b10b_enable" value="0" />
+ <parameter name="std_tx_bitrev_enable" value="0" />
+ <parameter name="std_tx_bitslip_enable" value="0" />
+ <parameter name="std_tx_byte_ser_mode" value="Disabled" />
+ <parameter name="std_tx_byterev_enable" value="0" />
+ <parameter name="std_tx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="tx_pma_clk_div" value="1" />
+ <parameter name="tx_pma_div_clkout_divider" value="33" />
+ <parameter name="validation_rule_select" value="" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..0ecdbd7fef0dbff418e3b608dcd9b4d52f40efa2
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_phy_10gbase_r_12.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..e234ccbd1ea222d958b044f1dbb27446f3bd4939
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_12
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_phy_10gbase_r_12.qip
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qsys b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..cde50fc7d5de7094ba1d1a25d5d9c7e6e5c2dff7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qsys
@@ -0,0 +1,619 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_phy_10gbase_r_12">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element xcvr_native_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="reconfig_avmm"
+ internal="xcvr_native_a10_0.reconfig_avmm"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_address" internal="reconfig_address" />
+ <port name="reconfig_read" internal="reconfig_read" />
+ <port name="reconfig_readdata" internal="reconfig_readdata" />
+ <port name="reconfig_waitrequest" internal="reconfig_waitrequest" />
+ <port name="reconfig_write" internal="reconfig_write" />
+ <port name="reconfig_writedata" internal="reconfig_writedata" />
+ </interface>
+ <interface
+ name="reconfig_clk"
+ internal="xcvr_native_a10_0.reconfig_clk"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_clk" internal="reconfig_clk" />
+ </interface>
+ <interface
+ name="reconfig_reset"
+ internal="xcvr_native_a10_0.reconfig_reset"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_reset" internal="reconfig_reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="xcvr_native_a10_0.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="xcvr_native_a10_0.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_cdr_refclk0"
+ internal="xcvr_native_a10_0.rx_cdr_refclk0"
+ type="conduit"
+ dir="end">
+ <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
+ </interface>
+ <interface
+ name="rx_clkout"
+ internal="xcvr_native_a10_0.rx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="rx_clkout" internal="rx_clkout" />
+ </interface>
+ <interface
+ name="rx_control"
+ internal="xcvr_native_a10_0.rx_control"
+ type="conduit"
+ dir="end">
+ <port name="rx_control" internal="rx_control" />
+ </interface>
+ <interface
+ name="rx_coreclkin"
+ internal="xcvr_native_a10_0.rx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="rx_coreclkin" internal="rx_coreclkin" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="xcvr_native_a10_0.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_enh_blk_lock"
+ internal="xcvr_native_a10_0.rx_enh_blk_lock"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
+ </interface>
+ <interface
+ name="rx_enh_data_valid"
+ internal="xcvr_native_a10_0.rx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_del"
+ internal="xcvr_native_a10_0.rx_enh_fifo_del"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_del" internal="rx_enh_fifo_del" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.rx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_empty" internal="rx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_full"
+ internal="xcvr_native_a10_0.rx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_full" internal="rx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_insert"
+ internal="xcvr_native_a10_0.rx_enh_fifo_insert"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_insert" internal="rx_enh_fifo_insert" />
+ </interface>
+ <interface
+ name="rx_enh_highber"
+ internal="xcvr_native_a10_0.rx_enh_highber"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_highber" internal="rx_enh_highber" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="xcvr_native_a10_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_is_lockedtoref"
+ internal="xcvr_native_a10_0.rx_is_lockedtoref"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtoref" internal="rx_is_lockedtoref" />
+ </interface>
+ <interface
+ name="rx_parallel_data"
+ internal="xcvr_native_a10_0.rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_parallel_data" internal="rx_parallel_data" />
+ </interface>
+ <interface
+ name="rx_prbs_done"
+ internal="xcvr_native_a10_0.rx_prbs_done"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_done" internal="rx_prbs_done" />
+ </interface>
+ <interface
+ name="rx_prbs_err"
+ internal="xcvr_native_a10_0.rx_prbs_err"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err" internal="rx_prbs_err" />
+ </interface>
+ <interface
+ name="rx_prbs_err_clr"
+ internal="xcvr_native_a10_0.rx_prbs_err_clr"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err_clr" internal="rx_prbs_err_clr" />
+ </interface>
+ <interface
+ name="rx_serial_data"
+ internal="xcvr_native_a10_0.rx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_serial_data" internal="rx_serial_data" />
+ </interface>
+ <interface
+ name="rx_seriallpbken"
+ internal="xcvr_native_a10_0.rx_seriallpbken"
+ type="conduit"
+ dir="end">
+ <port name="rx_seriallpbken" internal="rx_seriallpbken" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="xcvr_native_a10_0.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="xcvr_native_a10_0.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_clkout"
+ internal="xcvr_native_a10_0.tx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="tx_clkout" internal="tx_clkout" />
+ </interface>
+ <interface
+ name="tx_control"
+ internal="xcvr_native_a10_0.tx_control"
+ type="conduit"
+ dir="end">
+ <port name="tx_control" internal="tx_control" />
+ </interface>
+ <interface
+ name="tx_coreclkin"
+ internal="xcvr_native_a10_0.tx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="tx_coreclkin" internal="tx_coreclkin" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="xcvr_native_a10_0.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_enh_data_valid"
+ internal="xcvr_native_a10_0.tx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_empty" internal="tx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_full"
+ internal="xcvr_native_a10_0.tx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_full" internal="tx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pempty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pempty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pempty" internal="tx_enh_fifo_pempty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pfull"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pfull"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pfull" internal="tx_enh_fifo_pfull" />
+ </interface>
+ <interface
+ name="tx_err_ins"
+ internal="xcvr_native_a10_0.tx_err_ins"
+ type="conduit"
+ dir="end">
+ <port name="tx_err_ins" internal="tx_err_ins" />
+ </interface>
+ <interface
+ name="tx_parallel_data"
+ internal="xcvr_native_a10_0.tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_parallel_data" internal="tx_parallel_data" />
+ </interface>
+ <interface name="tx_pma_clkout" internal="xcvr_native_a10_0.tx_pma_clkout" />
+ <interface
+ name="tx_pma_div_clkout"
+ internal="xcvr_native_a10_0.tx_pma_div_clkout" />
+ <interface
+ name="tx_serial_clk0"
+ internal="xcvr_native_a10_0.tx_serial_clk0"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ </interface>
+ <interface
+ name="tx_serial_data"
+ internal="xcvr_native_a10_0.tx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_data" internal="tx_serial_data" />
+ </interface>
+ <interface
+ name="unused_rx_control"
+ internal="xcvr_native_a10_0.unused_rx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_control" internal="unused_rx_control" />
+ </interface>
+ <interface
+ name="unused_rx_parallel_data"
+ internal="xcvr_native_a10_0.unused_rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
+ </interface>
+ <interface
+ name="unused_tx_control"
+ internal="xcvr_native_a10_0.unused_tx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_control" internal="unused_tx_control" />
+ </interface>
+ <interface
+ name="unused_tx_parallel_data"
+ internal="xcvr_native_a10_0.unused_tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ </interface>
+ <module
+ name="xcvr_native_a10_0"
+ kind="altera_xcvr_native_a10"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="anlg_enable_rx_default_ovr" value="0" />
+ <parameter name="anlg_enable_tx_default_ovr" value="0" />
+ <parameter name="anlg_link" value="sr" />
+ <parameter name="anlg_rx_adp_ctle_acgain_4s">radp_ctle_acgain_4s_1</parameter>
+ <parameter name="anlg_rx_adp_ctle_eqz_1s_sel">radp_ctle_eqz_1s_sel_3</parameter>
+ <parameter name="anlg_rx_adp_dfe_fxtap1" value="radp_dfe_fxtap1_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap10" value="radp_dfe_fxtap10_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap11" value="radp_dfe_fxtap11_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap2" value="radp_dfe_fxtap2_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap3" value="radp_dfe_fxtap3_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap4" value="radp_dfe_fxtap4_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap5" value="radp_dfe_fxtap5_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap6" value="radp_dfe_fxtap6_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap7" value="radp_dfe_fxtap7_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap8" value="radp_dfe_fxtap8_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap9" value="radp_dfe_fxtap9_0" />
+ <parameter name="anlg_rx_adp_vga_sel" value="radp_vga_sel_2" />
+ <parameter name="anlg_rx_eq_dc_gain_trim" value="stg2_gain7" />
+ <parameter name="anlg_rx_one_stage_enable" value="s1_mode" />
+ <parameter name="anlg_rx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_analog_mode" value="user_custom" />
+ <parameter name="anlg_tx_compensation_en" value="enable" />
+ <parameter name="anlg_tx_pre_emp_sign_1st_post_tap" value="fir_post_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_2nd_post_tap" value="fir_post_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_1t" value="fir_pre_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_2t" value="fir_pre_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_1st_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_2nd_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_1t" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_2t" value="0" />
+ <parameter name="anlg_tx_slew_rate_ctrl" value="slew_r7" />
+ <parameter name="anlg_tx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_vod_output_swing_ctrl" value="0" />
+ <parameter name="anlg_voltage" value="1_1V" />
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="bonded_mode" value="not_bonded" />
+ <parameter name="cdr_refclk_cnt" value="1" />
+ <parameter name="cdr_refclk_select" value="0" />
+ <parameter name="channels" value="12" />
+ <parameter name="design_environment" value="NATIVE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="duplex_mode" value="duplex" />
+ <parameter name="enable_analog_settings" value="0" />
+ <parameter name="enable_hard_reset" value="0" />
+ <parameter name="enable_hip" value="0" />
+ <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
+ <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_port_rx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enable_port_rx_enh_blk_lock" value="1" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
+ <parameter name="enable_port_rx_enh_crc32_err" value="0" />
+ <parameter name="enable_port_rx_enh_data_valid" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_del" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_insert" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
+ <parameter name="enable_port_rx_enh_frame" value="0" />
+ <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_rx_enh_frame_lock" value="0" />
+ <parameter name="enable_port_rx_enh_highber" value="1" />
+ <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
+ <parameter name="enable_port_rx_is_lockedtodata" value="1" />
+ <parameter name="enable_port_rx_is_lockedtoref" value="1" />
+ <parameter name="enable_port_rx_pma_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_clkslip" value="0" />
+ <parameter name="enable_port_rx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_rx_polinv" value="0" />
+ <parameter name="enable_port_rx_seriallpbken" value="1" />
+ <parameter name="enable_port_rx_seriallpbken_tx" value="1" />
+ <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
+ <parameter name="enable_port_rx_std_bitslip" value="0" />
+ <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_rx_std_byterev_ena" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
+ <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_tx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_tx_enh_bitslip" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pempty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pfull" value="1" />
+ <parameter name="enable_port_tx_enh_frame" value="0" />
+ <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
+ <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_tx_pma_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_elecidle" value="0" />
+ <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_tx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_tx_pma_rxfound" value="0" />
+ <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
+ <parameter name="enable_port_tx_polinv" value="0" />
+ <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
+ <parameter name="enable_ports_adaptation" value="0" />
+ <parameter name="enable_ports_pipe_g3_analog" value="0" />
+ <parameter name="enable_ports_pipe_hclk" value="0" />
+ <parameter name="enable_ports_pipe_rx_elecidle" value="0" />
+ <parameter name="enable_ports_pipe_sw" value="0" />
+ <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
+ <parameter name="enable_ports_rx_manual_ppm" value="0" />
+ <parameter name="enable_ports_rx_prbs" value="1" />
+ <parameter name="enable_simple_interface" value="1" />
+ <parameter name="enable_skp_ports" value="0" />
+ <parameter name="enable_split_interface" value="0" />
+ <parameter name="enable_transparent_pcs" value="0" />
+ <parameter name="enh_low_latency_enable" value="0" />
+ <parameter name="enh_pcs_pma_width" value="32" />
+ <parameter name="enh_pld_pcs_width" value="66" />
+ <parameter name="enh_rx_64b66b_enable" value="1" />
+ <parameter name="enh_rx_bitslip_enable" value="0" />
+ <parameter name="enh_rx_blksync_enable" value="1" />
+ <parameter name="enh_rx_crcchk_enable" value="0" />
+ <parameter name="enh_rx_descram_enable" value="1" />
+ <parameter name="enh_rx_dispchk_enable" value="0" />
+ <parameter name="enh_rx_frmsync_enable" value="0" />
+ <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
+ <parameter name="enh_rx_krfec_err_mark_enable" value="0" />
+ <parameter name="enh_rx_krfec_err_mark_type" value="10G" />
+ <parameter name="enh_rx_polinv_enable" value="0" />
+ <parameter name="enh_rxfifo_align_del" value="0" />
+ <parameter name="enh_rxfifo_control_del" value="0" />
+ <parameter name="enh_rxfifo_mode" value="10GBase-R" />
+ <parameter name="enh_rxfifo_pempty" value="2" />
+ <parameter name="enh_rxfifo_pfull" value="23" />
+ <parameter name="enh_rxtxfifo_double_width" value="0" />
+ <parameter name="enh_tx_64b66b_enable" value="1" />
+ <parameter name="enh_tx_bitslip_enable" value="0" />
+ <parameter name="enh_tx_crcerr_enable" value="0" />
+ <parameter name="enh_tx_crcgen_enable" value="0" />
+ <parameter name="enh_tx_dispgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_burst_enable" value="0" />
+ <parameter name="enh_tx_frmgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
+ <parameter name="enh_tx_krfec_burst_err_enable" value="0" />
+ <parameter name="enh_tx_krfec_burst_err_len" value="1" />
+ <parameter name="enh_tx_polinv_enable" value="0" />
+ <parameter name="enh_tx_randomdispbit_enable" value="0" />
+ <parameter name="enh_tx_scram_enable" value="1" />
+ <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_tx_sh_err" value="0" />
+ <parameter name="enh_txfifo_mode" value="Phase compensation" />
+ <parameter name="enh_txfifo_pempty" value="2" />
+ <parameter name="enh_txfifo_pfull" value="11" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="number_physical_bonding_clocks" value="1" />
+ <parameter name="pcie_rate_match" value="Bypass" />
+ <parameter name="pcs_direct_width" value="8" />
+ <parameter name="pll_select" value="0" />
+ <parameter name="plls" value="1" />
+ <parameter name="pma_mode" value="basic" />
+ <parameter name="protocol_mode" value="teng_baser_mode" />
+ <parameter name="rcfg_enable" value="1" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="1" />
+ <parameter name="rcfg_iface_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="1" />
+ <parameter name="rcfg_mif_file_enable" value="1" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_data0" value="" />
+ <parameter name="rcfg_profile_data1" value="" />
+ <parameter name="rcfg_profile_data2" value="" />
+ <parameter name="rcfg_profile_data3" value="" />
+ <parameter name="rcfg_profile_data4" value="" />
+ <parameter name="rcfg_profile_data5" value="" />
+ <parameter name="rcfg_profile_data6" value="" />
+ <parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_shared" value="1" />
+ <parameter name="rcfg_sv_file_enable" value="1" />
+ <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
+ <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
+ <parameter name="rx_pma_dfe_fixed_taps" value="3" />
+ <parameter name="rx_pma_div_clkout_divider" value="0" />
+ <parameter name="rx_ppm_detect_threshold" value="1000" />
+ <parameter name="set_capability_reg_enable" value="1" />
+ <parameter name="set_cdr_refclk_freq" value="644.531250" />
+ <parameter name="set_csr_soft_logic_enable" value="1" />
+ <parameter name="set_data_rate" value="10312.5" />
+ <parameter name="set_disconnect_analog_resets" value="0" />
+ <parameter name="set_embedded_debug_enable" value="0" />
+ <parameter name="set_enable_calibration" value="0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_odi_soft_logic_enable" value="0" />
+ <parameter name="set_pcs_bonding_master" value="Auto" />
+ <parameter name="set_prbs_soft_logic_enable" value="1" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="std_low_latency_bypass_enable" value="0" />
+ <parameter name="std_pcs_pma_width" value="10" />
+ <parameter name="std_rx_8b10b_enable" value="0" />
+ <parameter name="std_rx_bitrev_enable" value="0" />
+ <parameter name="std_rx_byte_deser_mode" value="Disabled" />
+ <parameter name="std_rx_byterev_enable" value="0" />
+ <parameter name="std_rx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_rx_polinv_enable" value="0" />
+ <parameter name="std_rx_rmfifo_mode" value="disabled" />
+ <parameter name="std_rx_rmfifo_pattern_n" value="0" />
+ <parameter name="std_rx_rmfifo_pattern_p" value="0" />
+ <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
+ <parameter name="std_rx_word_aligner_mode" value="bitslip" />
+ <parameter name="std_rx_word_aligner_pattern" value="0" />
+ <parameter name="std_rx_word_aligner_pattern_len" value="7" />
+ <parameter name="std_rx_word_aligner_renumber" value="3" />
+ <parameter name="std_rx_word_aligner_rgnumber" value="3" />
+ <parameter name="std_rx_word_aligner_rknumber" value="3" />
+ <parameter name="std_rx_word_aligner_rvnumber" value="0" />
+ <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
+ <parameter name="std_tx_8b10b_enable" value="0" />
+ <parameter name="std_tx_bitrev_enable" value="0" />
+ <parameter name="std_tx_bitslip_enable" value="0" />
+ <parameter name="std_tx_byte_ser_mode" value="Disabled" />
+ <parameter name="std_tx_byterev_enable" value="0" />
+ <parameter name="std_tx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="tx_pma_clk_div" value="1" />
+ <parameter name="tx_pma_div_clkout_divider" value="33" />
+ <parameter name="validation_rule_select" value="" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..32c3254360f24ef9a15f1372ca50500e1be94abc
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_phy_10gbase_r_24.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..36af90e16d4089860a8581ffb390ec1f2e265bff
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_24
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_phy_10gbase_r_24.qip
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qsys b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..de05809f7d3466689c785bbe87cb3b186ee1359e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qsys
@@ -0,0 +1,619 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_phy_10gbase_r_24">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element xcvr_native_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="reconfig_avmm"
+ internal="xcvr_native_a10_0.reconfig_avmm"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_address" internal="reconfig_address" />
+ <port name="reconfig_read" internal="reconfig_read" />
+ <port name="reconfig_readdata" internal="reconfig_readdata" />
+ <port name="reconfig_waitrequest" internal="reconfig_waitrequest" />
+ <port name="reconfig_write" internal="reconfig_write" />
+ <port name="reconfig_writedata" internal="reconfig_writedata" />
+ </interface>
+ <interface
+ name="reconfig_clk"
+ internal="xcvr_native_a10_0.reconfig_clk"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_clk" internal="reconfig_clk" />
+ </interface>
+ <interface
+ name="reconfig_reset"
+ internal="xcvr_native_a10_0.reconfig_reset"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_reset" internal="reconfig_reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="xcvr_native_a10_0.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="xcvr_native_a10_0.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_cdr_refclk0"
+ internal="xcvr_native_a10_0.rx_cdr_refclk0"
+ type="conduit"
+ dir="end">
+ <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
+ </interface>
+ <interface
+ name="rx_clkout"
+ internal="xcvr_native_a10_0.rx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="rx_clkout" internal="rx_clkout" />
+ </interface>
+ <interface
+ name="rx_control"
+ internal="xcvr_native_a10_0.rx_control"
+ type="conduit"
+ dir="end">
+ <port name="rx_control" internal="rx_control" />
+ </interface>
+ <interface
+ name="rx_coreclkin"
+ internal="xcvr_native_a10_0.rx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="rx_coreclkin" internal="rx_coreclkin" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="xcvr_native_a10_0.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_enh_blk_lock"
+ internal="xcvr_native_a10_0.rx_enh_blk_lock"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
+ </interface>
+ <interface
+ name="rx_enh_data_valid"
+ internal="xcvr_native_a10_0.rx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_del"
+ internal="xcvr_native_a10_0.rx_enh_fifo_del"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_del" internal="rx_enh_fifo_del" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.rx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_empty" internal="rx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_full"
+ internal="xcvr_native_a10_0.rx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_full" internal="rx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_insert"
+ internal="xcvr_native_a10_0.rx_enh_fifo_insert"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_insert" internal="rx_enh_fifo_insert" />
+ </interface>
+ <interface
+ name="rx_enh_highber"
+ internal="xcvr_native_a10_0.rx_enh_highber"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_highber" internal="rx_enh_highber" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="xcvr_native_a10_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_is_lockedtoref"
+ internal="xcvr_native_a10_0.rx_is_lockedtoref"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtoref" internal="rx_is_lockedtoref" />
+ </interface>
+ <interface
+ name="rx_parallel_data"
+ internal="xcvr_native_a10_0.rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_parallel_data" internal="rx_parallel_data" />
+ </interface>
+ <interface
+ name="rx_prbs_done"
+ internal="xcvr_native_a10_0.rx_prbs_done"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_done" internal="rx_prbs_done" />
+ </interface>
+ <interface
+ name="rx_prbs_err"
+ internal="xcvr_native_a10_0.rx_prbs_err"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err" internal="rx_prbs_err" />
+ </interface>
+ <interface
+ name="rx_prbs_err_clr"
+ internal="xcvr_native_a10_0.rx_prbs_err_clr"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err_clr" internal="rx_prbs_err_clr" />
+ </interface>
+ <interface
+ name="rx_serial_data"
+ internal="xcvr_native_a10_0.rx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_serial_data" internal="rx_serial_data" />
+ </interface>
+ <interface
+ name="rx_seriallpbken"
+ internal="xcvr_native_a10_0.rx_seriallpbken"
+ type="conduit"
+ dir="end">
+ <port name="rx_seriallpbken" internal="rx_seriallpbken" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="xcvr_native_a10_0.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="xcvr_native_a10_0.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_clkout"
+ internal="xcvr_native_a10_0.tx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="tx_clkout" internal="tx_clkout" />
+ </interface>
+ <interface
+ name="tx_control"
+ internal="xcvr_native_a10_0.tx_control"
+ type="conduit"
+ dir="end">
+ <port name="tx_control" internal="tx_control" />
+ </interface>
+ <interface
+ name="tx_coreclkin"
+ internal="xcvr_native_a10_0.tx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="tx_coreclkin" internal="tx_coreclkin" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="xcvr_native_a10_0.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_enh_data_valid"
+ internal="xcvr_native_a10_0.tx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_empty" internal="tx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_full"
+ internal="xcvr_native_a10_0.tx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_full" internal="tx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pempty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pempty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pempty" internal="tx_enh_fifo_pempty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pfull"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pfull"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pfull" internal="tx_enh_fifo_pfull" />
+ </interface>
+ <interface
+ name="tx_err_ins"
+ internal="xcvr_native_a10_0.tx_err_ins"
+ type="conduit"
+ dir="end">
+ <port name="tx_err_ins" internal="tx_err_ins" />
+ </interface>
+ <interface
+ name="tx_parallel_data"
+ internal="xcvr_native_a10_0.tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_parallel_data" internal="tx_parallel_data" />
+ </interface>
+ <interface name="tx_pma_clkout" internal="xcvr_native_a10_0.tx_pma_clkout" />
+ <interface
+ name="tx_pma_div_clkout"
+ internal="xcvr_native_a10_0.tx_pma_div_clkout" />
+ <interface
+ name="tx_serial_clk0"
+ internal="xcvr_native_a10_0.tx_serial_clk0"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ </interface>
+ <interface
+ name="tx_serial_data"
+ internal="xcvr_native_a10_0.tx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_data" internal="tx_serial_data" />
+ </interface>
+ <interface
+ name="unused_rx_control"
+ internal="xcvr_native_a10_0.unused_rx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_control" internal="unused_rx_control" />
+ </interface>
+ <interface
+ name="unused_rx_parallel_data"
+ internal="xcvr_native_a10_0.unused_rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
+ </interface>
+ <interface
+ name="unused_tx_control"
+ internal="xcvr_native_a10_0.unused_tx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_control" internal="unused_tx_control" />
+ </interface>
+ <interface
+ name="unused_tx_parallel_data"
+ internal="xcvr_native_a10_0.unused_tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ </interface>
+ <module
+ name="xcvr_native_a10_0"
+ kind="altera_xcvr_native_a10"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="anlg_enable_rx_default_ovr" value="0" />
+ <parameter name="anlg_enable_tx_default_ovr" value="0" />
+ <parameter name="anlg_link" value="sr" />
+ <parameter name="anlg_rx_adp_ctle_acgain_4s">radp_ctle_acgain_4s_1</parameter>
+ <parameter name="anlg_rx_adp_ctle_eqz_1s_sel">radp_ctle_eqz_1s_sel_3</parameter>
+ <parameter name="anlg_rx_adp_dfe_fxtap1" value="radp_dfe_fxtap1_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap10" value="radp_dfe_fxtap10_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap11" value="radp_dfe_fxtap11_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap2" value="radp_dfe_fxtap2_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap3" value="radp_dfe_fxtap3_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap4" value="radp_dfe_fxtap4_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap5" value="radp_dfe_fxtap5_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap6" value="radp_dfe_fxtap6_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap7" value="radp_dfe_fxtap7_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap8" value="radp_dfe_fxtap8_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap9" value="radp_dfe_fxtap9_0" />
+ <parameter name="anlg_rx_adp_vga_sel" value="radp_vga_sel_2" />
+ <parameter name="anlg_rx_eq_dc_gain_trim" value="stg2_gain7" />
+ <parameter name="anlg_rx_one_stage_enable" value="s1_mode" />
+ <parameter name="anlg_rx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_analog_mode" value="user_custom" />
+ <parameter name="anlg_tx_compensation_en" value="enable" />
+ <parameter name="anlg_tx_pre_emp_sign_1st_post_tap" value="fir_post_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_2nd_post_tap" value="fir_post_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_1t" value="fir_pre_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_2t" value="fir_pre_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_1st_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_2nd_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_1t" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_2t" value="0" />
+ <parameter name="anlg_tx_slew_rate_ctrl" value="slew_r7" />
+ <parameter name="anlg_tx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_vod_output_swing_ctrl" value="0" />
+ <parameter name="anlg_voltage" value="1_1V" />
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="bonded_mode" value="not_bonded" />
+ <parameter name="cdr_refclk_cnt" value="1" />
+ <parameter name="cdr_refclk_select" value="0" />
+ <parameter name="channels" value="24" />
+ <parameter name="design_environment" value="NATIVE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="duplex_mode" value="duplex" />
+ <parameter name="enable_analog_settings" value="0" />
+ <parameter name="enable_hard_reset" value="0" />
+ <parameter name="enable_hip" value="0" />
+ <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
+ <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_port_rx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enable_port_rx_enh_blk_lock" value="1" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
+ <parameter name="enable_port_rx_enh_crc32_err" value="0" />
+ <parameter name="enable_port_rx_enh_data_valid" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_del" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_insert" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
+ <parameter name="enable_port_rx_enh_frame" value="0" />
+ <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_rx_enh_frame_lock" value="0" />
+ <parameter name="enable_port_rx_enh_highber" value="1" />
+ <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
+ <parameter name="enable_port_rx_is_lockedtodata" value="1" />
+ <parameter name="enable_port_rx_is_lockedtoref" value="1" />
+ <parameter name="enable_port_rx_pma_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_clkslip" value="0" />
+ <parameter name="enable_port_rx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_rx_polinv" value="0" />
+ <parameter name="enable_port_rx_seriallpbken" value="1" />
+ <parameter name="enable_port_rx_seriallpbken_tx" value="1" />
+ <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
+ <parameter name="enable_port_rx_std_bitslip" value="0" />
+ <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_rx_std_byterev_ena" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
+ <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_tx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_tx_enh_bitslip" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pempty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pfull" value="1" />
+ <parameter name="enable_port_tx_enh_frame" value="0" />
+ <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
+ <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_tx_pma_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_elecidle" value="0" />
+ <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_tx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_tx_pma_rxfound" value="0" />
+ <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
+ <parameter name="enable_port_tx_polinv" value="0" />
+ <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
+ <parameter name="enable_ports_adaptation" value="0" />
+ <parameter name="enable_ports_pipe_g3_analog" value="0" />
+ <parameter name="enable_ports_pipe_hclk" value="0" />
+ <parameter name="enable_ports_pipe_rx_elecidle" value="0" />
+ <parameter name="enable_ports_pipe_sw" value="0" />
+ <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
+ <parameter name="enable_ports_rx_manual_ppm" value="0" />
+ <parameter name="enable_ports_rx_prbs" value="1" />
+ <parameter name="enable_simple_interface" value="1" />
+ <parameter name="enable_skp_ports" value="0" />
+ <parameter name="enable_split_interface" value="0" />
+ <parameter name="enable_transparent_pcs" value="0" />
+ <parameter name="enh_low_latency_enable" value="0" />
+ <parameter name="enh_pcs_pma_width" value="32" />
+ <parameter name="enh_pld_pcs_width" value="66" />
+ <parameter name="enh_rx_64b66b_enable" value="1" />
+ <parameter name="enh_rx_bitslip_enable" value="0" />
+ <parameter name="enh_rx_blksync_enable" value="1" />
+ <parameter name="enh_rx_crcchk_enable" value="0" />
+ <parameter name="enh_rx_descram_enable" value="1" />
+ <parameter name="enh_rx_dispchk_enable" value="0" />
+ <parameter name="enh_rx_frmsync_enable" value="0" />
+ <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
+ <parameter name="enh_rx_krfec_err_mark_enable" value="0" />
+ <parameter name="enh_rx_krfec_err_mark_type" value="10G" />
+ <parameter name="enh_rx_polinv_enable" value="0" />
+ <parameter name="enh_rxfifo_align_del" value="0" />
+ <parameter name="enh_rxfifo_control_del" value="0" />
+ <parameter name="enh_rxfifo_mode" value="10GBase-R" />
+ <parameter name="enh_rxfifo_pempty" value="2" />
+ <parameter name="enh_rxfifo_pfull" value="23" />
+ <parameter name="enh_rxtxfifo_double_width" value="0" />
+ <parameter name="enh_tx_64b66b_enable" value="1" />
+ <parameter name="enh_tx_bitslip_enable" value="0" />
+ <parameter name="enh_tx_crcerr_enable" value="0" />
+ <parameter name="enh_tx_crcgen_enable" value="0" />
+ <parameter name="enh_tx_dispgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_burst_enable" value="0" />
+ <parameter name="enh_tx_frmgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
+ <parameter name="enh_tx_krfec_burst_err_enable" value="0" />
+ <parameter name="enh_tx_krfec_burst_err_len" value="1" />
+ <parameter name="enh_tx_polinv_enable" value="0" />
+ <parameter name="enh_tx_randomdispbit_enable" value="0" />
+ <parameter name="enh_tx_scram_enable" value="1" />
+ <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_tx_sh_err" value="0" />
+ <parameter name="enh_txfifo_mode" value="Phase compensation" />
+ <parameter name="enh_txfifo_pempty" value="2" />
+ <parameter name="enh_txfifo_pfull" value="11" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="number_physical_bonding_clocks" value="1" />
+ <parameter name="pcie_rate_match" value="Bypass" />
+ <parameter name="pcs_direct_width" value="8" />
+ <parameter name="pll_select" value="0" />
+ <parameter name="plls" value="1" />
+ <parameter name="pma_mode" value="basic" />
+ <parameter name="protocol_mode" value="teng_baser_mode" />
+ <parameter name="rcfg_enable" value="1" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="1" />
+ <parameter name="rcfg_iface_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="1" />
+ <parameter name="rcfg_mif_file_enable" value="1" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_data0" value="" />
+ <parameter name="rcfg_profile_data1" value="" />
+ <parameter name="rcfg_profile_data2" value="" />
+ <parameter name="rcfg_profile_data3" value="" />
+ <parameter name="rcfg_profile_data4" value="" />
+ <parameter name="rcfg_profile_data5" value="" />
+ <parameter name="rcfg_profile_data6" value="" />
+ <parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_shared" value="1" />
+ <parameter name="rcfg_sv_file_enable" value="1" />
+ <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
+ <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
+ <parameter name="rx_pma_dfe_fixed_taps" value="3" />
+ <parameter name="rx_pma_div_clkout_divider" value="0" />
+ <parameter name="rx_ppm_detect_threshold" value="1000" />
+ <parameter name="set_capability_reg_enable" value="1" />
+ <parameter name="set_cdr_refclk_freq" value="644.531250" />
+ <parameter name="set_csr_soft_logic_enable" value="1" />
+ <parameter name="set_data_rate" value="10312.5" />
+ <parameter name="set_disconnect_analog_resets" value="0" />
+ <parameter name="set_embedded_debug_enable" value="0" />
+ <parameter name="set_enable_calibration" value="0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_odi_soft_logic_enable" value="0" />
+ <parameter name="set_pcs_bonding_master" value="Auto" />
+ <parameter name="set_prbs_soft_logic_enable" value="1" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="std_low_latency_bypass_enable" value="0" />
+ <parameter name="std_pcs_pma_width" value="10" />
+ <parameter name="std_rx_8b10b_enable" value="0" />
+ <parameter name="std_rx_bitrev_enable" value="0" />
+ <parameter name="std_rx_byte_deser_mode" value="Disabled" />
+ <parameter name="std_rx_byterev_enable" value="0" />
+ <parameter name="std_rx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_rx_polinv_enable" value="0" />
+ <parameter name="std_rx_rmfifo_mode" value="disabled" />
+ <parameter name="std_rx_rmfifo_pattern_n" value="0" />
+ <parameter name="std_rx_rmfifo_pattern_p" value="0" />
+ <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
+ <parameter name="std_rx_word_aligner_mode" value="bitslip" />
+ <parameter name="std_rx_word_aligner_pattern" value="0" />
+ <parameter name="std_rx_word_aligner_pattern_len" value="7" />
+ <parameter name="std_rx_word_aligner_renumber" value="3" />
+ <parameter name="std_rx_word_aligner_rgnumber" value="3" />
+ <parameter name="std_rx_word_aligner_rknumber" value="3" />
+ <parameter name="std_rx_word_aligner_rvnumber" value="0" />
+ <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
+ <parameter name="std_tx_8b10b_enable" value="0" />
+ <parameter name="std_tx_bitrev_enable" value="0" />
+ <parameter name="std_tx_bitslip_enable" value="0" />
+ <parameter name="std_tx_byte_ser_mode" value="Disabled" />
+ <parameter name="std_tx_byterev_enable" value="0" />
+ <parameter name="std_tx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="tx_pma_clk_div" value="1" />
+ <parameter name="tx_pma_div_clkout_divider" value="33" />
+ <parameter name="validation_rule_select" value="" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..445f2fed57c45685fc5e2a62706da6e6f271a308
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_phy_10gbase_r_4.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..680f6a38677c847b79186ea491ca3e52dae2df2b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_4
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_phy_10gbase_r_4.qip
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qsys b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..5f6c9b37ac1d2f5f92e34f0592d84490673dd785
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qsys
@@ -0,0 +1,619 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_phy_10gbase_r_4">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element xcvr_native_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="reconfig_avmm"
+ internal="xcvr_native_a10_0.reconfig_avmm"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_address" internal="reconfig_address" />
+ <port name="reconfig_read" internal="reconfig_read" />
+ <port name="reconfig_readdata" internal="reconfig_readdata" />
+ <port name="reconfig_waitrequest" internal="reconfig_waitrequest" />
+ <port name="reconfig_write" internal="reconfig_write" />
+ <port name="reconfig_writedata" internal="reconfig_writedata" />
+ </interface>
+ <interface
+ name="reconfig_clk"
+ internal="xcvr_native_a10_0.reconfig_clk"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_clk" internal="reconfig_clk" />
+ </interface>
+ <interface
+ name="reconfig_reset"
+ internal="xcvr_native_a10_0.reconfig_reset"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_reset" internal="reconfig_reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="xcvr_native_a10_0.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="xcvr_native_a10_0.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_cdr_refclk0"
+ internal="xcvr_native_a10_0.rx_cdr_refclk0"
+ type="conduit"
+ dir="end">
+ <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
+ </interface>
+ <interface
+ name="rx_clkout"
+ internal="xcvr_native_a10_0.rx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="rx_clkout" internal="rx_clkout" />
+ </interface>
+ <interface
+ name="rx_control"
+ internal="xcvr_native_a10_0.rx_control"
+ type="conduit"
+ dir="end">
+ <port name="rx_control" internal="rx_control" />
+ </interface>
+ <interface
+ name="rx_coreclkin"
+ internal="xcvr_native_a10_0.rx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="rx_coreclkin" internal="rx_coreclkin" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="xcvr_native_a10_0.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_enh_blk_lock"
+ internal="xcvr_native_a10_0.rx_enh_blk_lock"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
+ </interface>
+ <interface
+ name="rx_enh_data_valid"
+ internal="xcvr_native_a10_0.rx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_del"
+ internal="xcvr_native_a10_0.rx_enh_fifo_del"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_del" internal="rx_enh_fifo_del" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.rx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_empty" internal="rx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_full"
+ internal="xcvr_native_a10_0.rx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_full" internal="rx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_insert"
+ internal="xcvr_native_a10_0.rx_enh_fifo_insert"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_insert" internal="rx_enh_fifo_insert" />
+ </interface>
+ <interface
+ name="rx_enh_highber"
+ internal="xcvr_native_a10_0.rx_enh_highber"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_highber" internal="rx_enh_highber" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="xcvr_native_a10_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_is_lockedtoref"
+ internal="xcvr_native_a10_0.rx_is_lockedtoref"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtoref" internal="rx_is_lockedtoref" />
+ </interface>
+ <interface
+ name="rx_parallel_data"
+ internal="xcvr_native_a10_0.rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_parallel_data" internal="rx_parallel_data" />
+ </interface>
+ <interface
+ name="rx_prbs_done"
+ internal="xcvr_native_a10_0.rx_prbs_done"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_done" internal="rx_prbs_done" />
+ </interface>
+ <interface
+ name="rx_prbs_err"
+ internal="xcvr_native_a10_0.rx_prbs_err"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err" internal="rx_prbs_err" />
+ </interface>
+ <interface
+ name="rx_prbs_err_clr"
+ internal="xcvr_native_a10_0.rx_prbs_err_clr"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err_clr" internal="rx_prbs_err_clr" />
+ </interface>
+ <interface
+ name="rx_serial_data"
+ internal="xcvr_native_a10_0.rx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_serial_data" internal="rx_serial_data" />
+ </interface>
+ <interface
+ name="rx_seriallpbken"
+ internal="xcvr_native_a10_0.rx_seriallpbken"
+ type="conduit"
+ dir="end">
+ <port name="rx_seriallpbken" internal="rx_seriallpbken" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="xcvr_native_a10_0.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="xcvr_native_a10_0.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_clkout"
+ internal="xcvr_native_a10_0.tx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="tx_clkout" internal="tx_clkout" />
+ </interface>
+ <interface
+ name="tx_control"
+ internal="xcvr_native_a10_0.tx_control"
+ type="conduit"
+ dir="end">
+ <port name="tx_control" internal="tx_control" />
+ </interface>
+ <interface
+ name="tx_coreclkin"
+ internal="xcvr_native_a10_0.tx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="tx_coreclkin" internal="tx_coreclkin" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="xcvr_native_a10_0.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_enh_data_valid"
+ internal="xcvr_native_a10_0.tx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_empty" internal="tx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_full"
+ internal="xcvr_native_a10_0.tx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_full" internal="tx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pempty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pempty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pempty" internal="tx_enh_fifo_pempty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pfull"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pfull"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pfull" internal="tx_enh_fifo_pfull" />
+ </interface>
+ <interface
+ name="tx_err_ins"
+ internal="xcvr_native_a10_0.tx_err_ins"
+ type="conduit"
+ dir="end">
+ <port name="tx_err_ins" internal="tx_err_ins" />
+ </interface>
+ <interface
+ name="tx_parallel_data"
+ internal="xcvr_native_a10_0.tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_parallel_data" internal="tx_parallel_data" />
+ </interface>
+ <interface name="tx_pma_clkout" internal="xcvr_native_a10_0.tx_pma_clkout" />
+ <interface
+ name="tx_pma_div_clkout"
+ internal="xcvr_native_a10_0.tx_pma_div_clkout" />
+ <interface
+ name="tx_serial_clk0"
+ internal="xcvr_native_a10_0.tx_serial_clk0"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ </interface>
+ <interface
+ name="tx_serial_data"
+ internal="xcvr_native_a10_0.tx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_data" internal="tx_serial_data" />
+ </interface>
+ <interface
+ name="unused_rx_control"
+ internal="xcvr_native_a10_0.unused_rx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_control" internal="unused_rx_control" />
+ </interface>
+ <interface
+ name="unused_rx_parallel_data"
+ internal="xcvr_native_a10_0.unused_rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
+ </interface>
+ <interface
+ name="unused_tx_control"
+ internal="xcvr_native_a10_0.unused_tx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_control" internal="unused_tx_control" />
+ </interface>
+ <interface
+ name="unused_tx_parallel_data"
+ internal="xcvr_native_a10_0.unused_tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ </interface>
+ <module
+ name="xcvr_native_a10_0"
+ kind="altera_xcvr_native_a10"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="anlg_enable_rx_default_ovr" value="0" />
+ <parameter name="anlg_enable_tx_default_ovr" value="0" />
+ <parameter name="anlg_link" value="sr" />
+ <parameter name="anlg_rx_adp_ctle_acgain_4s">radp_ctle_acgain_4s_1</parameter>
+ <parameter name="anlg_rx_adp_ctle_eqz_1s_sel">radp_ctle_eqz_1s_sel_3</parameter>
+ <parameter name="anlg_rx_adp_dfe_fxtap1" value="radp_dfe_fxtap1_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap10" value="radp_dfe_fxtap10_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap11" value="radp_dfe_fxtap11_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap2" value="radp_dfe_fxtap2_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap3" value="radp_dfe_fxtap3_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap4" value="radp_dfe_fxtap4_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap5" value="radp_dfe_fxtap5_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap6" value="radp_dfe_fxtap6_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap7" value="radp_dfe_fxtap7_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap8" value="radp_dfe_fxtap8_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap9" value="radp_dfe_fxtap9_0" />
+ <parameter name="anlg_rx_adp_vga_sel" value="radp_vga_sel_2" />
+ <parameter name="anlg_rx_eq_dc_gain_trim" value="stg2_gain7" />
+ <parameter name="anlg_rx_one_stage_enable" value="s1_mode" />
+ <parameter name="anlg_rx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_analog_mode" value="user_custom" />
+ <parameter name="anlg_tx_compensation_en" value="enable" />
+ <parameter name="anlg_tx_pre_emp_sign_1st_post_tap" value="fir_post_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_2nd_post_tap" value="fir_post_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_1t" value="fir_pre_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_2t" value="fir_pre_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_1st_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_2nd_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_1t" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_2t" value="0" />
+ <parameter name="anlg_tx_slew_rate_ctrl" value="slew_r7" />
+ <parameter name="anlg_tx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_vod_output_swing_ctrl" value="0" />
+ <parameter name="anlg_voltage" value="1_1V" />
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="bonded_mode" value="not_bonded" />
+ <parameter name="cdr_refclk_cnt" value="1" />
+ <parameter name="cdr_refclk_select" value="0" />
+ <parameter name="channels" value="4" />
+ <parameter name="design_environment" value="NATIVE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="duplex_mode" value="duplex" />
+ <parameter name="enable_analog_settings" value="0" />
+ <parameter name="enable_hard_reset" value="0" />
+ <parameter name="enable_hip" value="0" />
+ <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
+ <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_port_rx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enable_port_rx_enh_blk_lock" value="1" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
+ <parameter name="enable_port_rx_enh_crc32_err" value="0" />
+ <parameter name="enable_port_rx_enh_data_valid" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_del" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_insert" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
+ <parameter name="enable_port_rx_enh_frame" value="0" />
+ <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_rx_enh_frame_lock" value="0" />
+ <parameter name="enable_port_rx_enh_highber" value="1" />
+ <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
+ <parameter name="enable_port_rx_is_lockedtodata" value="1" />
+ <parameter name="enable_port_rx_is_lockedtoref" value="1" />
+ <parameter name="enable_port_rx_pma_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_clkslip" value="0" />
+ <parameter name="enable_port_rx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_rx_polinv" value="0" />
+ <parameter name="enable_port_rx_seriallpbken" value="1" />
+ <parameter name="enable_port_rx_seriallpbken_tx" value="1" />
+ <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
+ <parameter name="enable_port_rx_std_bitslip" value="0" />
+ <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_rx_std_byterev_ena" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
+ <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_tx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_tx_enh_bitslip" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pempty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pfull" value="1" />
+ <parameter name="enable_port_tx_enh_frame" value="0" />
+ <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
+ <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_tx_pma_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_elecidle" value="0" />
+ <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_tx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_tx_pma_rxfound" value="0" />
+ <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
+ <parameter name="enable_port_tx_polinv" value="0" />
+ <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
+ <parameter name="enable_ports_adaptation" value="0" />
+ <parameter name="enable_ports_pipe_g3_analog" value="0" />
+ <parameter name="enable_ports_pipe_hclk" value="0" />
+ <parameter name="enable_ports_pipe_rx_elecidle" value="0" />
+ <parameter name="enable_ports_pipe_sw" value="0" />
+ <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
+ <parameter name="enable_ports_rx_manual_ppm" value="0" />
+ <parameter name="enable_ports_rx_prbs" value="1" />
+ <parameter name="enable_simple_interface" value="1" />
+ <parameter name="enable_skp_ports" value="0" />
+ <parameter name="enable_split_interface" value="0" />
+ <parameter name="enable_transparent_pcs" value="0" />
+ <parameter name="enh_low_latency_enable" value="0" />
+ <parameter name="enh_pcs_pma_width" value="32" />
+ <parameter name="enh_pld_pcs_width" value="66" />
+ <parameter name="enh_rx_64b66b_enable" value="1" />
+ <parameter name="enh_rx_bitslip_enable" value="0" />
+ <parameter name="enh_rx_blksync_enable" value="1" />
+ <parameter name="enh_rx_crcchk_enable" value="0" />
+ <parameter name="enh_rx_descram_enable" value="1" />
+ <parameter name="enh_rx_dispchk_enable" value="0" />
+ <parameter name="enh_rx_frmsync_enable" value="0" />
+ <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
+ <parameter name="enh_rx_krfec_err_mark_enable" value="0" />
+ <parameter name="enh_rx_krfec_err_mark_type" value="10G" />
+ <parameter name="enh_rx_polinv_enable" value="0" />
+ <parameter name="enh_rxfifo_align_del" value="0" />
+ <parameter name="enh_rxfifo_control_del" value="0" />
+ <parameter name="enh_rxfifo_mode" value="10GBase-R" />
+ <parameter name="enh_rxfifo_pempty" value="2" />
+ <parameter name="enh_rxfifo_pfull" value="23" />
+ <parameter name="enh_rxtxfifo_double_width" value="0" />
+ <parameter name="enh_tx_64b66b_enable" value="1" />
+ <parameter name="enh_tx_bitslip_enable" value="0" />
+ <parameter name="enh_tx_crcerr_enable" value="0" />
+ <parameter name="enh_tx_crcgen_enable" value="0" />
+ <parameter name="enh_tx_dispgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_burst_enable" value="0" />
+ <parameter name="enh_tx_frmgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
+ <parameter name="enh_tx_krfec_burst_err_enable" value="0" />
+ <parameter name="enh_tx_krfec_burst_err_len" value="1" />
+ <parameter name="enh_tx_polinv_enable" value="0" />
+ <parameter name="enh_tx_randomdispbit_enable" value="0" />
+ <parameter name="enh_tx_scram_enable" value="1" />
+ <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_tx_sh_err" value="0" />
+ <parameter name="enh_txfifo_mode" value="Phase compensation" />
+ <parameter name="enh_txfifo_pempty" value="2" />
+ <parameter name="enh_txfifo_pfull" value="11" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="number_physical_bonding_clocks" value="1" />
+ <parameter name="pcie_rate_match" value="Bypass" />
+ <parameter name="pcs_direct_width" value="8" />
+ <parameter name="pll_select" value="0" />
+ <parameter name="plls" value="1" />
+ <parameter name="pma_mode" value="basic" />
+ <parameter name="protocol_mode" value="teng_baser_mode" />
+ <parameter name="rcfg_enable" value="1" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="1" />
+ <parameter name="rcfg_iface_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="1" />
+ <parameter name="rcfg_mif_file_enable" value="1" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_data0" value="" />
+ <parameter name="rcfg_profile_data1" value="" />
+ <parameter name="rcfg_profile_data2" value="" />
+ <parameter name="rcfg_profile_data3" value="" />
+ <parameter name="rcfg_profile_data4" value="" />
+ <parameter name="rcfg_profile_data5" value="" />
+ <parameter name="rcfg_profile_data6" value="" />
+ <parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_shared" value="1" />
+ <parameter name="rcfg_sv_file_enable" value="1" />
+ <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
+ <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
+ <parameter name="rx_pma_dfe_fixed_taps" value="3" />
+ <parameter name="rx_pma_div_clkout_divider" value="0" />
+ <parameter name="rx_ppm_detect_threshold" value="1000" />
+ <parameter name="set_capability_reg_enable" value="1" />
+ <parameter name="set_cdr_refclk_freq" value="644.531250" />
+ <parameter name="set_csr_soft_logic_enable" value="1" />
+ <parameter name="set_data_rate" value="10312.5" />
+ <parameter name="set_disconnect_analog_resets" value="0" />
+ <parameter name="set_embedded_debug_enable" value="0" />
+ <parameter name="set_enable_calibration" value="0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_odi_soft_logic_enable" value="0" />
+ <parameter name="set_pcs_bonding_master" value="Auto" />
+ <parameter name="set_prbs_soft_logic_enable" value="1" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="std_low_latency_bypass_enable" value="0" />
+ <parameter name="std_pcs_pma_width" value="10" />
+ <parameter name="std_rx_8b10b_enable" value="0" />
+ <parameter name="std_rx_bitrev_enable" value="0" />
+ <parameter name="std_rx_byte_deser_mode" value="Disabled" />
+ <parameter name="std_rx_byterev_enable" value="0" />
+ <parameter name="std_rx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_rx_polinv_enable" value="0" />
+ <parameter name="std_rx_rmfifo_mode" value="disabled" />
+ <parameter name="std_rx_rmfifo_pattern_n" value="0" />
+ <parameter name="std_rx_rmfifo_pattern_p" value="0" />
+ <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
+ <parameter name="std_rx_word_aligner_mode" value="bitslip" />
+ <parameter name="std_rx_word_aligner_pattern" value="0" />
+ <parameter name="std_rx_word_aligner_pattern_len" value="7" />
+ <parameter name="std_rx_word_aligner_renumber" value="3" />
+ <parameter name="std_rx_word_aligner_rgnumber" value="3" />
+ <parameter name="std_rx_word_aligner_rknumber" value="3" />
+ <parameter name="std_rx_word_aligner_rvnumber" value="0" />
+ <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
+ <parameter name="std_tx_8b10b_enable" value="0" />
+ <parameter name="std_tx_bitrev_enable" value="0" />
+ <parameter name="std_tx_bitslip_enable" value="0" />
+ <parameter name="std_tx_byte_ser_mode" value="Disabled" />
+ <parameter name="std_tx_byterev_enable" value="0" />
+ <parameter name="std_tx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="tx_pma_clk_div" value="1" />
+ <parameter name="tx_pma_div_clkout_divider" value="33" />
+ <parameter name="validation_rule_select" value="" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..552a7a512e3009ede312770acde9f9377922acc8
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_phy_10gbase_r_48.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..977dbcf2d24e4b9ed0a38b3de63db4e4b5dad870
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_phy_10gbase_r_48
+hdl_library_clause_name = ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_phy_10gbase_r_48.qip
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qsys b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..ed9e10a5f6e0148138519f1777f2b28acd6ee6b6
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qsys
@@ -0,0 +1,619 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_phy_10gbase_r_48">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element xcvr_native_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="reconfig_avmm"
+ internal="xcvr_native_a10_0.reconfig_avmm"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_address" internal="reconfig_address" />
+ <port name="reconfig_read" internal="reconfig_read" />
+ <port name="reconfig_readdata" internal="reconfig_readdata" />
+ <port name="reconfig_waitrequest" internal="reconfig_waitrequest" />
+ <port name="reconfig_write" internal="reconfig_write" />
+ <port name="reconfig_writedata" internal="reconfig_writedata" />
+ </interface>
+ <interface
+ name="reconfig_clk"
+ internal="xcvr_native_a10_0.reconfig_clk"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_clk" internal="reconfig_clk" />
+ </interface>
+ <interface
+ name="reconfig_reset"
+ internal="xcvr_native_a10_0.reconfig_reset"
+ type="conduit"
+ dir="end">
+ <port name="reconfig_reset" internal="reconfig_reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="xcvr_native_a10_0.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="xcvr_native_a10_0.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_cdr_refclk0"
+ internal="xcvr_native_a10_0.rx_cdr_refclk0"
+ type="conduit"
+ dir="end">
+ <port name="rx_cdr_refclk0" internal="rx_cdr_refclk0" />
+ </interface>
+ <interface
+ name="rx_clkout"
+ internal="xcvr_native_a10_0.rx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="rx_clkout" internal="rx_clkout" />
+ </interface>
+ <interface
+ name="rx_control"
+ internal="xcvr_native_a10_0.rx_control"
+ type="conduit"
+ dir="end">
+ <port name="rx_control" internal="rx_control" />
+ </interface>
+ <interface
+ name="rx_coreclkin"
+ internal="xcvr_native_a10_0.rx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="rx_coreclkin" internal="rx_coreclkin" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="xcvr_native_a10_0.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_enh_blk_lock"
+ internal="xcvr_native_a10_0.rx_enh_blk_lock"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_blk_lock" internal="rx_enh_blk_lock" />
+ </interface>
+ <interface
+ name="rx_enh_data_valid"
+ internal="xcvr_native_a10_0.rx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_data_valid" internal="rx_enh_data_valid" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_del"
+ internal="xcvr_native_a10_0.rx_enh_fifo_del"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_del" internal="rx_enh_fifo_del" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.rx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_empty" internal="rx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_full"
+ internal="xcvr_native_a10_0.rx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_full" internal="rx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="rx_enh_fifo_insert"
+ internal="xcvr_native_a10_0.rx_enh_fifo_insert"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_fifo_insert" internal="rx_enh_fifo_insert" />
+ </interface>
+ <interface
+ name="rx_enh_highber"
+ internal="xcvr_native_a10_0.rx_enh_highber"
+ type="conduit"
+ dir="end">
+ <port name="rx_enh_highber" internal="rx_enh_highber" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="xcvr_native_a10_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_is_lockedtoref"
+ internal="xcvr_native_a10_0.rx_is_lockedtoref"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtoref" internal="rx_is_lockedtoref" />
+ </interface>
+ <interface
+ name="rx_parallel_data"
+ internal="xcvr_native_a10_0.rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_parallel_data" internal="rx_parallel_data" />
+ </interface>
+ <interface
+ name="rx_prbs_done"
+ internal="xcvr_native_a10_0.rx_prbs_done"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_done" internal="rx_prbs_done" />
+ </interface>
+ <interface
+ name="rx_prbs_err"
+ internal="xcvr_native_a10_0.rx_prbs_err"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err" internal="rx_prbs_err" />
+ </interface>
+ <interface
+ name="rx_prbs_err_clr"
+ internal="xcvr_native_a10_0.rx_prbs_err_clr"
+ type="conduit"
+ dir="end">
+ <port name="rx_prbs_err_clr" internal="rx_prbs_err_clr" />
+ </interface>
+ <interface
+ name="rx_serial_data"
+ internal="xcvr_native_a10_0.rx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="rx_serial_data" internal="rx_serial_data" />
+ </interface>
+ <interface
+ name="rx_seriallpbken"
+ internal="xcvr_native_a10_0.rx_seriallpbken"
+ type="conduit"
+ dir="end">
+ <port name="rx_seriallpbken" internal="rx_seriallpbken" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="xcvr_native_a10_0.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="xcvr_native_a10_0.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_clkout"
+ internal="xcvr_native_a10_0.tx_clkout"
+ type="conduit"
+ dir="end">
+ <port name="tx_clkout" internal="tx_clkout" />
+ </interface>
+ <interface
+ name="tx_control"
+ internal="xcvr_native_a10_0.tx_control"
+ type="conduit"
+ dir="end">
+ <port name="tx_control" internal="tx_control" />
+ </interface>
+ <interface
+ name="tx_coreclkin"
+ internal="xcvr_native_a10_0.tx_coreclkin"
+ type="conduit"
+ dir="end">
+ <port name="tx_coreclkin" internal="tx_coreclkin" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="xcvr_native_a10_0.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_enh_data_valid"
+ internal="xcvr_native_a10_0.tx_enh_data_valid"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_data_valid" internal="tx_enh_data_valid" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_empty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_empty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_empty" internal="tx_enh_fifo_empty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_full"
+ internal="xcvr_native_a10_0.tx_enh_fifo_full"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_full" internal="tx_enh_fifo_full" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pempty"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pempty"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pempty" internal="tx_enh_fifo_pempty" />
+ </interface>
+ <interface
+ name="tx_enh_fifo_pfull"
+ internal="xcvr_native_a10_0.tx_enh_fifo_pfull"
+ type="conduit"
+ dir="end">
+ <port name="tx_enh_fifo_pfull" internal="tx_enh_fifo_pfull" />
+ </interface>
+ <interface
+ name="tx_err_ins"
+ internal="xcvr_native_a10_0.tx_err_ins"
+ type="conduit"
+ dir="end">
+ <port name="tx_err_ins" internal="tx_err_ins" />
+ </interface>
+ <interface
+ name="tx_parallel_data"
+ internal="xcvr_native_a10_0.tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_parallel_data" internal="tx_parallel_data" />
+ </interface>
+ <interface name="tx_pma_clkout" internal="xcvr_native_a10_0.tx_pma_clkout" />
+ <interface
+ name="tx_pma_div_clkout"
+ internal="xcvr_native_a10_0.tx_pma_div_clkout" />
+ <interface
+ name="tx_serial_clk0"
+ internal="xcvr_native_a10_0.tx_serial_clk0"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_clk0" internal="tx_serial_clk0" />
+ </interface>
+ <interface
+ name="tx_serial_data"
+ internal="xcvr_native_a10_0.tx_serial_data"
+ type="conduit"
+ dir="end">
+ <port name="tx_serial_data" internal="tx_serial_data" />
+ </interface>
+ <interface
+ name="unused_rx_control"
+ internal="xcvr_native_a10_0.unused_rx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_control" internal="unused_rx_control" />
+ </interface>
+ <interface
+ name="unused_rx_parallel_data"
+ internal="xcvr_native_a10_0.unused_rx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_rx_parallel_data" internal="unused_rx_parallel_data" />
+ </interface>
+ <interface
+ name="unused_tx_control"
+ internal="xcvr_native_a10_0.unused_tx_control"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_control" internal="unused_tx_control" />
+ </interface>
+ <interface
+ name="unused_tx_parallel_data"
+ internal="xcvr_native_a10_0.unused_tx_parallel_data"
+ type="conduit"
+ dir="end">
+ <port name="unused_tx_parallel_data" internal="unused_tx_parallel_data" />
+ </interface>
+ <module
+ name="xcvr_native_a10_0"
+ kind="altera_xcvr_native_a10"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="anlg_enable_rx_default_ovr" value="0" />
+ <parameter name="anlg_enable_tx_default_ovr" value="0" />
+ <parameter name="anlg_link" value="sr" />
+ <parameter name="anlg_rx_adp_ctle_acgain_4s">radp_ctle_acgain_4s_1</parameter>
+ <parameter name="anlg_rx_adp_ctle_eqz_1s_sel">radp_ctle_eqz_1s_sel_3</parameter>
+ <parameter name="anlg_rx_adp_dfe_fxtap1" value="radp_dfe_fxtap1_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap10" value="radp_dfe_fxtap10_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap11" value="radp_dfe_fxtap11_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap2" value="radp_dfe_fxtap2_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap3" value="radp_dfe_fxtap3_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap4" value="radp_dfe_fxtap4_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap5" value="radp_dfe_fxtap5_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap6" value="radp_dfe_fxtap6_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap7" value="radp_dfe_fxtap7_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap8" value="radp_dfe_fxtap8_0" />
+ <parameter name="anlg_rx_adp_dfe_fxtap9" value="radp_dfe_fxtap9_0" />
+ <parameter name="anlg_rx_adp_vga_sel" value="radp_vga_sel_2" />
+ <parameter name="anlg_rx_eq_dc_gain_trim" value="stg2_gain7" />
+ <parameter name="anlg_rx_one_stage_enable" value="s1_mode" />
+ <parameter name="anlg_rx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_analog_mode" value="user_custom" />
+ <parameter name="anlg_tx_compensation_en" value="enable" />
+ <parameter name="anlg_tx_pre_emp_sign_1st_post_tap" value="fir_post_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_2nd_post_tap" value="fir_post_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_1t" value="fir_pre_1t_neg" />
+ <parameter name="anlg_tx_pre_emp_sign_pre_tap_2t" value="fir_pre_2t_neg" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_1st_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_2nd_post_tap" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_1t" value="0" />
+ <parameter name="anlg_tx_pre_emp_switching_ctrl_pre_tap_2t" value="0" />
+ <parameter name="anlg_tx_slew_rate_ctrl" value="slew_r7" />
+ <parameter name="anlg_tx_term_sel" value="r_r1" />
+ <parameter name="anlg_tx_vod_output_swing_ctrl" value="0" />
+ <parameter name="anlg_voltage" value="1_1V" />
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="bonded_mode" value="not_bonded" />
+ <parameter name="cdr_refclk_cnt" value="1" />
+ <parameter name="cdr_refclk_select" value="0" />
+ <parameter name="channels" value="48" />
+ <parameter name="design_environment" value="NATIVE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="duplex_mode" value="duplex" />
+ <parameter name="enable_analog_settings" value="0" />
+ <parameter name="enable_hard_reset" value="0" />
+ <parameter name="enable_hip" value="0" />
+ <parameter name="enable_parallel_loopback" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame" value="0" />
+ <parameter name="enable_port_krfec_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_krfec_tx_enh_frame" value="0" />
+ <parameter name="enable_port_pipe_rx_polarity" value="0" />
+ <parameter name="enable_port_rx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_rx_enh_bitslip" value="0" />
+ <parameter name="enable_port_rx_enh_blk_lock" value="1" />
+ <parameter name="enable_port_rx_enh_clr_errblk_count" value="0" />
+ <parameter name="enable_port_rx_enh_crc32_err" value="0" />
+ <parameter name="enable_port_rx_enh_data_valid" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_align_clr" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_align_val" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_del" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_insert" value="1" />
+ <parameter name="enable_port_rx_enh_fifo_pempty" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_pfull" value="0" />
+ <parameter name="enable_port_rx_enh_fifo_rd_en" value="0" />
+ <parameter name="enable_port_rx_enh_frame" value="0" />
+ <parameter name="enable_port_rx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_rx_enh_frame_lock" value="0" />
+ <parameter name="enable_port_rx_enh_highber" value="1" />
+ <parameter name="enable_port_rx_enh_highber_clr_cnt" value="0" />
+ <parameter name="enable_port_rx_is_lockedtodata" value="1" />
+ <parameter name="enable_port_rx_is_lockedtoref" value="1" />
+ <parameter name="enable_port_rx_pma_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_clkslip" value="0" />
+ <parameter name="enable_port_rx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_rx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_rx_polinv" value="0" />
+ <parameter name="enable_port_rx_seriallpbken" value="1" />
+ <parameter name="enable_port_rx_seriallpbken_tx" value="1" />
+ <parameter name="enable_port_rx_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_bitrev_ena" value="0" />
+ <parameter name="enable_port_rx_std_bitslip" value="0" />
+ <parameter name="enable_port_rx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_rx_std_byterev_ena" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_pcfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_empty" value="0" />
+ <parameter name="enable_port_rx_std_rmfifo_full" value="0" />
+ <parameter name="enable_port_rx_std_signaldetect" value="0" />
+ <parameter name="enable_port_rx_std_wa_a1a2size" value="0" />
+ <parameter name="enable_port_rx_std_wa_patternalign" value="0" />
+ <parameter name="enable_port_tx_analog_reset_ack" value="0" />
+ <parameter name="enable_port_tx_enh_bitslip" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_cnt" value="0" />
+ <parameter name="enable_port_tx_enh_fifo_empty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_full" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pempty" value="1" />
+ <parameter name="enable_port_tx_enh_fifo_pfull" value="1" />
+ <parameter name="enable_port_tx_enh_frame" value="0" />
+ <parameter name="enable_port_tx_enh_frame_burst_en" value="0" />
+ <parameter name="enable_port_tx_enh_frame_diag_status" value="0" />
+ <parameter name="enable_port_tx_pma_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_div_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_elecidle" value="0" />
+ <parameter name="enable_port_tx_pma_iqtxrx_clkout" value="0" />
+ <parameter name="enable_port_tx_pma_qpipulldn" value="0" />
+ <parameter name="enable_port_tx_pma_qpipullup" value="0" />
+ <parameter name="enable_port_tx_pma_rxfound" value="0" />
+ <parameter name="enable_port_tx_pma_txdetectrx" value="0" />
+ <parameter name="enable_port_tx_polinv" value="0" />
+ <parameter name="enable_port_tx_std_bitslipboundarysel" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_empty" value="0" />
+ <parameter name="enable_port_tx_std_pcfifo_full" value="0" />
+ <parameter name="enable_ports_adaptation" value="0" />
+ <parameter name="enable_ports_pipe_g3_analog" value="0" />
+ <parameter name="enable_ports_pipe_hclk" value="0" />
+ <parameter name="enable_ports_pipe_rx_elecidle" value="0" />
+ <parameter name="enable_ports_pipe_sw" value="0" />
+ <parameter name="enable_ports_rx_manual_cdr_mode" value="0" />
+ <parameter name="enable_ports_rx_manual_ppm" value="0" />
+ <parameter name="enable_ports_rx_prbs" value="1" />
+ <parameter name="enable_simple_interface" value="1" />
+ <parameter name="enable_skp_ports" value="0" />
+ <parameter name="enable_split_interface" value="0" />
+ <parameter name="enable_transparent_pcs" value="0" />
+ <parameter name="enh_low_latency_enable" value="0" />
+ <parameter name="enh_pcs_pma_width" value="32" />
+ <parameter name="enh_pld_pcs_width" value="66" />
+ <parameter name="enh_rx_64b66b_enable" value="1" />
+ <parameter name="enh_rx_bitslip_enable" value="0" />
+ <parameter name="enh_rx_blksync_enable" value="1" />
+ <parameter name="enh_rx_crcchk_enable" value="0" />
+ <parameter name="enh_rx_descram_enable" value="1" />
+ <parameter name="enh_rx_dispchk_enable" value="0" />
+ <parameter name="enh_rx_frmsync_enable" value="0" />
+ <parameter name="enh_rx_frmsync_mfrm_length" value="2048" />
+ <parameter name="enh_rx_krfec_err_mark_enable" value="0" />
+ <parameter name="enh_rx_krfec_err_mark_type" value="10G" />
+ <parameter name="enh_rx_polinv_enable" value="0" />
+ <parameter name="enh_rxfifo_align_del" value="0" />
+ <parameter name="enh_rxfifo_control_del" value="0" />
+ <parameter name="enh_rxfifo_mode" value="10GBase-R" />
+ <parameter name="enh_rxfifo_pempty" value="2" />
+ <parameter name="enh_rxfifo_pfull" value="23" />
+ <parameter name="enh_rxtxfifo_double_width" value="0" />
+ <parameter name="enh_tx_64b66b_enable" value="1" />
+ <parameter name="enh_tx_bitslip_enable" value="0" />
+ <parameter name="enh_tx_crcerr_enable" value="0" />
+ <parameter name="enh_tx_crcgen_enable" value="0" />
+ <parameter name="enh_tx_dispgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_burst_enable" value="0" />
+ <parameter name="enh_tx_frmgen_enable" value="0" />
+ <parameter name="enh_tx_frmgen_mfrm_length" value="2048" />
+ <parameter name="enh_tx_krfec_burst_err_enable" value="0" />
+ <parameter name="enh_tx_krfec_burst_err_len" value="1" />
+ <parameter name="enh_tx_polinv_enable" value="0" />
+ <parameter name="enh_tx_randomdispbit_enable" value="0" />
+ <parameter name="enh_tx_scram_enable" value="1" />
+ <parameter name="enh_tx_scram_seed" value="288230376151711743" />
+ <parameter name="enh_tx_sh_err" value="0" />
+ <parameter name="enh_txfifo_mode" value="Phase compensation" />
+ <parameter name="enh_txfifo_pempty" value="2" />
+ <parameter name="enh_txfifo_pfull" value="11" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="number_physical_bonding_clocks" value="1" />
+ <parameter name="pcie_rate_match" value="Bypass" />
+ <parameter name="pcs_direct_width" value="8" />
+ <parameter name="pll_select" value="0" />
+ <parameter name="plls" value="1" />
+ <parameter name="pma_mode" value="basic" />
+ <parameter name="protocol_mode" value="teng_baser_mode" />
+ <parameter name="rcfg_enable" value="1" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_native_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="1" />
+ <parameter name="rcfg_iface_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="1" />
+ <parameter name="rcfg_mif_file_enable" value="1" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_data0" value="" />
+ <parameter name="rcfg_profile_data1" value="" />
+ <parameter name="rcfg_profile_data2" value="" />
+ <parameter name="rcfg_profile_data3" value="" />
+ <parameter name="rcfg_profile_data4" value="" />
+ <parameter name="rcfg_profile_data5" value="" />
+ <parameter name="rcfg_profile_data6" value="" />
+ <parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_shared" value="1" />
+ <parameter name="rcfg_sv_file_enable" value="1" />
+ <parameter name="rx_pma_ctle_adaptation_mode" value="manual" />
+ <parameter name="rx_pma_dfe_adaptation_mode" value="disabled" />
+ <parameter name="rx_pma_dfe_fixed_taps" value="3" />
+ <parameter name="rx_pma_div_clkout_divider" value="0" />
+ <parameter name="rx_ppm_detect_threshold" value="1000" />
+ <parameter name="set_capability_reg_enable" value="1" />
+ <parameter name="set_cdr_refclk_freq" value="644.531250" />
+ <parameter name="set_csr_soft_logic_enable" value="1" />
+ <parameter name="set_data_rate" value="10312.5" />
+ <parameter name="set_disconnect_analog_resets" value="0" />
+ <parameter name="set_embedded_debug_enable" value="0" />
+ <parameter name="set_enable_calibration" value="0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_odi_soft_logic_enable" value="0" />
+ <parameter name="set_pcs_bonding_master" value="Auto" />
+ <parameter name="set_prbs_soft_logic_enable" value="1" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="std_low_latency_bypass_enable" value="0" />
+ <parameter name="std_pcs_pma_width" value="10" />
+ <parameter name="std_rx_8b10b_enable" value="0" />
+ <parameter name="std_rx_bitrev_enable" value="0" />
+ <parameter name="std_rx_byte_deser_mode" value="Disabled" />
+ <parameter name="std_rx_byterev_enable" value="0" />
+ <parameter name="std_rx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_rx_polinv_enable" value="0" />
+ <parameter name="std_rx_rmfifo_mode" value="disabled" />
+ <parameter name="std_rx_rmfifo_pattern_n" value="0" />
+ <parameter name="std_rx_rmfifo_pattern_p" value="0" />
+ <parameter name="std_rx_word_aligner_fast_sync_status_enable" value="0" />
+ <parameter name="std_rx_word_aligner_mode" value="bitslip" />
+ <parameter name="std_rx_word_aligner_pattern" value="0" />
+ <parameter name="std_rx_word_aligner_pattern_len" value="7" />
+ <parameter name="std_rx_word_aligner_renumber" value="3" />
+ <parameter name="std_rx_word_aligner_rgnumber" value="3" />
+ <parameter name="std_rx_word_aligner_rknumber" value="3" />
+ <parameter name="std_rx_word_aligner_rvnumber" value="0" />
+ <parameter name="std_tx_8b10b_disp_ctrl_enable" value="0" />
+ <parameter name="std_tx_8b10b_enable" value="0" />
+ <parameter name="std_tx_bitrev_enable" value="0" />
+ <parameter name="std_tx_bitslip_enable" value="0" />
+ <parameter name="std_tx_byte_ser_mode" value="Disabled" />
+ <parameter name="std_tx_byterev_enable" value="0" />
+ <parameter name="std_tx_pcfifo_mode" value="low_latency" />
+ <parameter name="std_tx_polinv_enable" value="0" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="tx_pma_clk_div" value="1" />
+ <parameter name="tx_pma_div_clkout_divider" value="33" />
+ <parameter name="validation_rule_select" value="" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..17e6673b38fc72cc8c74d22859e0d0d01adcdd88
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_pll_clk125.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..3b93d5e09ca59cc7b52c90ef4fb54899f1ebfdaf
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_pll_clk125
+hdl_library_clause_name = ip_arria10_e1sg_pll_clk125_altera_iopll_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_pll_clk125.qip
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/ip_arria10_e1sg_pll_clk125.qsys b/libraries/technology/ip_arria10_e1sg/pll_clk125/ip_arria10_e1sg_pll_clk125.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..2f229843aa464c338bffae2263dc97ed635a7498
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/ip_arria10_e1sg_pll_clk125.qsys
@@ -0,0 +1,398 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_pll_clk125">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element iopll_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>outclk0</key>
+ <value>
+ <connectionPointName>outclk0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>20000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk1</key>
+ <value>
+ <connectionPointName>outclk1</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>50000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk2</key>
+ <value>
+ <connectionPointName>outclk2</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk3</key>
+ <value>
+ <connectionPointName>outclk3</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="locked" internal="iopll_0.locked" type="conduit" dir="end">
+ <port name="locked" internal="locked" />
+ </interface>
+ <interface name="outclk0" internal="iopll_0.outclk0" type="clock" dir="start">
+ <port name="outclk_0" internal="outclk_0" />
+ </interface>
+ <interface name="outclk1" internal="iopll_0.outclk1" type="clock" dir="start">
+ <port name="outclk_1" internal="outclk_1" />
+ </interface>
+ <interface name="outclk2" internal="iopll_0.outclk2" type="clock" dir="start">
+ <port name="outclk_2" internal="outclk_2" />
+ </interface>
+ <interface name="outclk3" internal="iopll_0.outclk3" type="clock" dir="start">
+ <port name="outclk_3" internal="outclk_3" />
+ </interface>
+ <interface name="refclk" internal="iopll_0.refclk" type="clock" dir="end">
+ <port name="refclk" internal="refclk" />
+ </interface>
+ <interface name="reset" internal="iopll_0.reset" type="reset" dir="end">
+ <port name="rst" internal="rst" />
+ </interface>
+ <module
+ name="iopll_0"
+ kind="altera_iopll"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="gui_active_clk" value="false" />
+ <parameter name="gui_actual_duty_cycle0" value="50.0" />
+ <parameter name="gui_actual_duty_cycle1" value="50.0" />
+ <parameter name="gui_actual_duty_cycle10" value="50.0" />
+ <parameter name="gui_actual_duty_cycle11" value="50.0" />
+ <parameter name="gui_actual_duty_cycle12" value="50.0" />
+ <parameter name="gui_actual_duty_cycle13" value="50.0" />
+ <parameter name="gui_actual_duty_cycle14" value="50.0" />
+ <parameter name="gui_actual_duty_cycle15" value="50.0" />
+ <parameter name="gui_actual_duty_cycle16" value="50.0" />
+ <parameter name="gui_actual_duty_cycle17" value="50.0" />
+ <parameter name="gui_actual_duty_cycle2" value="50.0" />
+ <parameter name="gui_actual_duty_cycle3" value="50.0" />
+ <parameter name="gui_actual_duty_cycle4" value="50.0" />
+ <parameter name="gui_actual_duty_cycle5" value="50.0" />
+ <parameter name="gui_actual_duty_cycle6" value="50.0" />
+ <parameter name="gui_actual_duty_cycle7" value="50.0" />
+ <parameter name="gui_actual_duty_cycle8" value="50.0" />
+ <parameter name="gui_actual_duty_cycle9" value="50.0" />
+ <parameter name="gui_actual_output_clock_frequency0" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency1" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency10" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency11" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency12" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency13" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency14" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency15" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency16" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency17" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency2" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency3" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency4" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency5" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency6" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency7" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency8" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency9" value="100.0" />
+ <parameter name="gui_actual_phase_shift0" value="0.0" />
+ <parameter name="gui_actual_phase_shift1" value="0.0" />
+ <parameter name="gui_actual_phase_shift10" value="0.0" />
+ <parameter name="gui_actual_phase_shift11" value="0.0" />
+ <parameter name="gui_actual_phase_shift12" value="0.0" />
+ <parameter name="gui_actual_phase_shift13" value="0.0" />
+ <parameter name="gui_actual_phase_shift14" value="0.0" />
+ <parameter name="gui_actual_phase_shift15" value="0.0" />
+ <parameter name="gui_actual_phase_shift16" value="0.0" />
+ <parameter name="gui_actual_phase_shift17" value="0.0" />
+ <parameter name="gui_actual_phase_shift2" value="0.0" />
+ <parameter name="gui_actual_phase_shift3" value="0.0" />
+ <parameter name="gui_actual_phase_shift4" value="0.0" />
+ <parameter name="gui_actual_phase_shift5" value="0.0" />
+ <parameter name="gui_actual_phase_shift6" value="0.0" />
+ <parameter name="gui_actual_phase_shift7" value="0.0" />
+ <parameter name="gui_actual_phase_shift8" value="0.0" />
+ <parameter name="gui_actual_phase_shift9" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg0" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg1" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg10" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg11" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg12" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg13" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg14" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg15" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg16" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg17" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg2" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg3" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg4" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg5" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg6" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg7" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg8" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg9" value="0.0" />
+ <parameter name="gui_cascade_counter0" value="false" />
+ <parameter name="gui_cascade_counter1" value="false" />
+ <parameter name="gui_cascade_counter10" value="false" />
+ <parameter name="gui_cascade_counter11" value="false" />
+ <parameter name="gui_cascade_counter12" value="false" />
+ <parameter name="gui_cascade_counter13" value="false" />
+ <parameter name="gui_cascade_counter14" value="false" />
+ <parameter name="gui_cascade_counter15" value="false" />
+ <parameter name="gui_cascade_counter16" value="false" />
+ <parameter name="gui_cascade_counter17" value="false" />
+ <parameter name="gui_cascade_counter2" value="false" />
+ <parameter name="gui_cascade_counter3" value="false" />
+ <parameter name="gui_cascade_counter4" value="false" />
+ <parameter name="gui_cascade_counter5" value="false" />
+ <parameter name="gui_cascade_counter6" value="false" />
+ <parameter name="gui_cascade_counter7" value="false" />
+ <parameter name="gui_cascade_counter8" value="false" />
+ <parameter name="gui_cascade_counter9" value="false" />
+ <parameter name="gui_cascade_outclk_index" value="0" />
+ <parameter name="gui_clk_bad" value="false" />
+ <parameter name="gui_clock_name_global" value="false" />
+ <parameter name="gui_clock_name_string0" value="pll_clk20" />
+ <parameter name="gui_clock_name_string1" value="pll_clk50" />
+ <parameter name="gui_clock_name_string10" value="outclk10" />
+ <parameter name="gui_clock_name_string11" value="outclk11" />
+ <parameter name="gui_clock_name_string12" value="outclk12" />
+ <parameter name="gui_clock_name_string13" value="outclk13" />
+ <parameter name="gui_clock_name_string14" value="outclk14" />
+ <parameter name="gui_clock_name_string15" value="outclk15" />
+ <parameter name="gui_clock_name_string16" value="outclk16" />
+ <parameter name="gui_clock_name_string17" value="outclk17" />
+ <parameter name="gui_clock_name_string2" value="pll_clk100" />
+ <parameter name="gui_clock_name_string3" value="pll_clk125" />
+ <parameter name="gui_clock_name_string4" value="outclk4" />
+ <parameter name="gui_clock_name_string5" value="outclk5" />
+ <parameter name="gui_clock_name_string6" value="outclk6" />
+ <parameter name="gui_clock_name_string7" value="outclk7" />
+ <parameter name="gui_clock_name_string8" value="outclk8" />
+ <parameter name="gui_clock_name_string9" value="outclk9" />
+ <parameter name="gui_clock_to_compensate" value="0" />
+ <parameter name="gui_device_speed_grade" value="1" />
+ <parameter name="gui_divide_factor_c0" value="6" />
+ <parameter name="gui_divide_factor_c1" value="6" />
+ <parameter name="gui_divide_factor_c10" value="6" />
+ <parameter name="gui_divide_factor_c11" value="6" />
+ <parameter name="gui_divide_factor_c12" value="6" />
+ <parameter name="gui_divide_factor_c13" value="6" />
+ <parameter name="gui_divide_factor_c14" value="6" />
+ <parameter name="gui_divide_factor_c15" value="6" />
+ <parameter name="gui_divide_factor_c16" value="6" />
+ <parameter name="gui_divide_factor_c17" value="6" />
+ <parameter name="gui_divide_factor_c2" value="6" />
+ <parameter name="gui_divide_factor_c3" value="6" />
+ <parameter name="gui_divide_factor_c4" value="6" />
+ <parameter name="gui_divide_factor_c5" value="6" />
+ <parameter name="gui_divide_factor_c6" value="6" />
+ <parameter name="gui_divide_factor_c7" value="6" />
+ <parameter name="gui_divide_factor_c8" value="6" />
+ <parameter name="gui_divide_factor_c9" value="6" />
+ <parameter name="gui_divide_factor_n" value="1" />
+ <parameter name="gui_dps_cntr" value="C0" />
+ <parameter name="gui_dps_dir" value="Positive" />
+ <parameter name="gui_dps_num" value="1" />
+ <parameter name="gui_dsm_out_sel" value="1st_order" />
+ <parameter name="gui_duty_cycle0" value="50.0" />
+ <parameter name="gui_duty_cycle1" value="50.0" />
+ <parameter name="gui_duty_cycle10" value="50.0" />
+ <parameter name="gui_duty_cycle11" value="50.0" />
+ <parameter name="gui_duty_cycle12" value="50.0" />
+ <parameter name="gui_duty_cycle13" value="50.0" />
+ <parameter name="gui_duty_cycle14" value="50.0" />
+ <parameter name="gui_duty_cycle15" value="50.0" />
+ <parameter name="gui_duty_cycle16" value="50.0" />
+ <parameter name="gui_duty_cycle17" value="50.0" />
+ <parameter name="gui_duty_cycle2" value="50.0" />
+ <parameter name="gui_duty_cycle3" value="50.0" />
+ <parameter name="gui_duty_cycle4" value="50.0" />
+ <parameter name="gui_duty_cycle5" value="50.0" />
+ <parameter name="gui_duty_cycle6" value="50.0" />
+ <parameter name="gui_duty_cycle7" value="50.0" />
+ <parameter name="gui_duty_cycle8" value="50.0" />
+ <parameter name="gui_duty_cycle9" value="50.0" />
+ <parameter name="gui_en_adv_params" value="false" />
+ <parameter name="gui_en_dps_ports" value="false" />
+ <parameter name="gui_en_extclkout_ports" value="false" />
+ <parameter name="gui_en_lvds_ports" value="Disabled" />
+ <parameter name="gui_en_phout_ports" value="false" />
+ <parameter name="gui_en_reconf" value="false" />
+ <parameter name="gui_enable_cascade_in" value="false" />
+ <parameter name="gui_enable_cascade_out" value="false" />
+ <parameter name="gui_enable_mif_dps" value="false" />
+ <parameter name="gui_enable_output_counter_cascading" value="false" />
+ <parameter name="gui_existing_mif_file_path" value="~/pll.mif" />
+ <parameter name="gui_extclkout_0_source" value="C0" />
+ <parameter name="gui_extclkout_1_source" value="C0" />
+ <parameter name="gui_feedback_clock" value="Global Clock" />
+ <parameter name="gui_fix_vco_frequency" value="false" />
+ <parameter name="gui_fixed_vco_frequency" value="600.0" />
+ <parameter name="gui_frac_multiply_factor" value="1" />
+ <parameter name="gui_fractional_cout" value="32" />
+ <parameter name="gui_lock_setting" value="Low Lock Time" />
+ <parameter name="gui_mif_config_name" value="unnamed" />
+ <parameter name="gui_mif_gen_options">Generate New MIF File</parameter>
+ <parameter name="gui_multiply_factor" value="6" />
+ <parameter name="gui_new_mif_file_path" value="~/pll.mif" />
+ <parameter name="gui_number_of_clocks" value="4" />
+ <parameter name="gui_operation_mode" value="direct" />
+ <parameter name="gui_output_clock_frequency0" value="20.0" />
+ <parameter name="gui_output_clock_frequency1" value="50.0" />
+ <parameter name="gui_output_clock_frequency10" value="100.0" />
+ <parameter name="gui_output_clock_frequency11" value="100.0" />
+ <parameter name="gui_output_clock_frequency12" value="100.0" />
+ <parameter name="gui_output_clock_frequency13" value="100.0" />
+ <parameter name="gui_output_clock_frequency14" value="100.0" />
+ <parameter name="gui_output_clock_frequency15" value="100.0" />
+ <parameter name="gui_output_clock_frequency16" value="100.0" />
+ <parameter name="gui_output_clock_frequency17" value="100.0" />
+ <parameter name="gui_output_clock_frequency2" value="100.0" />
+ <parameter name="gui_output_clock_frequency3" value="125.0" />
+ <parameter name="gui_output_clock_frequency4" value="100.0" />
+ <parameter name="gui_output_clock_frequency5" value="100.0" />
+ <parameter name="gui_output_clock_frequency6" value="100.0" />
+ <parameter name="gui_output_clock_frequency7" value="100.0" />
+ <parameter name="gui_output_clock_frequency8" value="100.0" />
+ <parameter name="gui_output_clock_frequency9" value="100.0" />
+ <parameter name="gui_phase_shift0" value="0.0" />
+ <parameter name="gui_phase_shift1" value="0.0" />
+ <parameter name="gui_phase_shift10" value="0.0" />
+ <parameter name="gui_phase_shift11" value="0.0" />
+ <parameter name="gui_phase_shift12" value="0.0" />
+ <parameter name="gui_phase_shift13" value="0.0" />
+ <parameter name="gui_phase_shift14" value="0.0" />
+ <parameter name="gui_phase_shift15" value="0.0" />
+ <parameter name="gui_phase_shift16" value="0.0" />
+ <parameter name="gui_phase_shift17" value="0.0" />
+ <parameter name="gui_phase_shift2" value="0.0" />
+ <parameter name="gui_phase_shift3" value="0.0" />
+ <parameter name="gui_phase_shift4" value="0.0" />
+ <parameter name="gui_phase_shift5" value="0.0" />
+ <parameter name="gui_phase_shift6" value="0.0" />
+ <parameter name="gui_phase_shift7" value="0.0" />
+ <parameter name="gui_phase_shift8" value="0.0" />
+ <parameter name="gui_phase_shift9" value="0.0" />
+ <parameter name="gui_phase_shift_deg0" value="0.0" />
+ <parameter name="gui_phase_shift_deg1" value="0.0" />
+ <parameter name="gui_phase_shift_deg10" value="0.0" />
+ <parameter name="gui_phase_shift_deg11" value="0.0" />
+ <parameter name="gui_phase_shift_deg12" value="0.0" />
+ <parameter name="gui_phase_shift_deg13" value="0.0" />
+ <parameter name="gui_phase_shift_deg14" value="0.0" />
+ <parameter name="gui_phase_shift_deg15" value="0.0" />
+ <parameter name="gui_phase_shift_deg16" value="0.0" />
+ <parameter name="gui_phase_shift_deg17" value="0.0" />
+ <parameter name="gui_phase_shift_deg2" value="0.0" />
+ <parameter name="gui_phase_shift_deg3" value="0.0" />
+ <parameter name="gui_phase_shift_deg4" value="0.0" />
+ <parameter name="gui_phase_shift_deg5" value="0.0" />
+ <parameter name="gui_phase_shift_deg6" value="0.0" />
+ <parameter name="gui_phase_shift_deg7" value="0.0" />
+ <parameter name="gui_phase_shift_deg8" value="0.0" />
+ <parameter name="gui_phase_shift_deg9" value="0.0" />
+ <parameter name="gui_phout_division" value="1" />
+ <parameter name="gui_pll_auto_reset" value="false" />
+ <parameter name="gui_pll_bandwidth_preset" value="Low" />
+ <parameter name="gui_pll_cascading_mode" value="adjpllin" />
+ <parameter name="gui_pll_mode" value="Integer-N PLL" />
+ <parameter name="gui_ps_units0" value="ps" />
+ <parameter name="gui_ps_units1" value="ps" />
+ <parameter name="gui_ps_units10" value="ps" />
+ <parameter name="gui_ps_units11" value="ps" />
+ <parameter name="gui_ps_units12" value="ps" />
+ <parameter name="gui_ps_units13" value="ps" />
+ <parameter name="gui_ps_units14" value="ps" />
+ <parameter name="gui_ps_units15" value="ps" />
+ <parameter name="gui_ps_units16" value="ps" />
+ <parameter name="gui_ps_units17" value="ps" />
+ <parameter name="gui_ps_units2" value="ps" />
+ <parameter name="gui_ps_units3" value="ps" />
+ <parameter name="gui_ps_units4" value="ps" />
+ <parameter name="gui_ps_units5" value="ps" />
+ <parameter name="gui_ps_units6" value="ps" />
+ <parameter name="gui_ps_units7" value="ps" />
+ <parameter name="gui_ps_units8" value="ps" />
+ <parameter name="gui_ps_units9" value="ps" />
+ <parameter name="gui_refclk1_frequency" value="100.0" />
+ <parameter name="gui_refclk_switch" value="false" />
+ <parameter name="gui_reference_clock_frequency" value="125.0" />
+ <parameter name="gui_switchover_delay" value="0" />
+ <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+ <parameter name="gui_use_NDFB_modes" value="false" />
+ <parameter name="gui_use_locked" value="true" />
+ <parameter name="gui_vco_frequency" value="600.0" />
+ <parameter name="system_info_device_component" value="10AX115S2F45E1SG" />
+ <parameter name="system_info_device_family" value="Arria 10" />
+ <parameter name="system_info_device_speed_grade" value="1" />
+ <parameter name="system_part_trait_speed_grade" value="1" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..33378d48f5938d5fdae540eb07aae6262bf7772c
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_pll_clk200.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..99e5895aceb644a201a288db39ab44216460dab7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_pll_clk200
+hdl_library_clause_name = ip_arria10_e1sg_pll_clk200_altera_iopll_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_pll_clk200.qip
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/ip_arria10_e1sg_pll_clk200.qsys b/libraries/technology/ip_arria10_e1sg/pll_clk200/ip_arria10_e1sg_pll_clk200.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..e872e6f7aaa0ba2bdd22c4fa75fba820cc935b4e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/ip_arria10_e1sg_pll_clk200.qsys
@@ -0,0 +1,382 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_pll_clk200">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element iopll_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>outclk0</key>
+ <value>
+ <connectionPointName>outclk0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>200000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk1</key>
+ <value>
+ <connectionPointName>outclk1</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>200000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk2</key>
+ <value>
+ <connectionPointName>outclk2</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>400000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="locked" internal="iopll_0.locked" type="conduit" dir="end">
+ <port name="locked" internal="locked" />
+ </interface>
+ <interface name="outclk0" internal="iopll_0.outclk0" type="clock" dir="start">
+ <port name="outclk_0" internal="outclk_0" />
+ </interface>
+ <interface name="outclk1" internal="iopll_0.outclk1" type="clock" dir="start">
+ <port name="outclk_1" internal="outclk_1" />
+ </interface>
+ <interface name="outclk2" internal="iopll_0.outclk2" type="clock" dir="start">
+ <port name="outclk_2" internal="outclk_2" />
+ </interface>
+ <interface name="refclk" internal="iopll_0.refclk" type="clock" dir="end">
+ <port name="refclk" internal="refclk" />
+ </interface>
+ <interface name="reset" internal="iopll_0.reset" type="reset" dir="end">
+ <port name="rst" internal="rst" />
+ </interface>
+ <module
+ name="iopll_0"
+ kind="altera_iopll"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="gui_active_clk" value="false" />
+ <parameter name="gui_actual_duty_cycle0" value="50.0" />
+ <parameter name="gui_actual_duty_cycle1" value="50.0" />
+ <parameter name="gui_actual_duty_cycle10" value="50.0" />
+ <parameter name="gui_actual_duty_cycle11" value="50.0" />
+ <parameter name="gui_actual_duty_cycle12" value="50.0" />
+ <parameter name="gui_actual_duty_cycle13" value="50.0" />
+ <parameter name="gui_actual_duty_cycle14" value="50.0" />
+ <parameter name="gui_actual_duty_cycle15" value="50.0" />
+ <parameter name="gui_actual_duty_cycle16" value="50.0" />
+ <parameter name="gui_actual_duty_cycle17" value="50.0" />
+ <parameter name="gui_actual_duty_cycle2" value="50.0" />
+ <parameter name="gui_actual_duty_cycle3" value="50.0" />
+ <parameter name="gui_actual_duty_cycle4" value="50.0" />
+ <parameter name="gui_actual_duty_cycle5" value="50.0" />
+ <parameter name="gui_actual_duty_cycle6" value="50.0" />
+ <parameter name="gui_actual_duty_cycle7" value="50.0" />
+ <parameter name="gui_actual_duty_cycle8" value="50.0" />
+ <parameter name="gui_actual_duty_cycle9" value="50.0" />
+ <parameter name="gui_actual_output_clock_frequency0" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency1" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency10" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency11" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency12" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency13" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency14" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency15" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency16" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency17" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency2" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency3" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency4" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency5" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency6" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency7" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency8" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency9" value="100.0" />
+ <parameter name="gui_actual_phase_shift0" value="0.0" />
+ <parameter name="gui_actual_phase_shift1" value="0.0" />
+ <parameter name="gui_actual_phase_shift10" value="0.0" />
+ <parameter name="gui_actual_phase_shift11" value="0.0" />
+ <parameter name="gui_actual_phase_shift12" value="0.0" />
+ <parameter name="gui_actual_phase_shift13" value="0.0" />
+ <parameter name="gui_actual_phase_shift14" value="0.0" />
+ <parameter name="gui_actual_phase_shift15" value="0.0" />
+ <parameter name="gui_actual_phase_shift16" value="0.0" />
+ <parameter name="gui_actual_phase_shift17" value="0.0" />
+ <parameter name="gui_actual_phase_shift2" value="0.0" />
+ <parameter name="gui_actual_phase_shift3" value="0.0" />
+ <parameter name="gui_actual_phase_shift4" value="0.0" />
+ <parameter name="gui_actual_phase_shift5" value="0.0" />
+ <parameter name="gui_actual_phase_shift6" value="0.0" />
+ <parameter name="gui_actual_phase_shift7" value="0.0" />
+ <parameter name="gui_actual_phase_shift8" value="0.0" />
+ <parameter name="gui_actual_phase_shift9" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg0" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg1" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg10" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg11" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg12" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg13" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg14" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg15" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg16" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg17" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg2" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg3" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg4" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg5" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg6" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg7" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg8" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg9" value="0.0" />
+ <parameter name="gui_cascade_counter0" value="false" />
+ <parameter name="gui_cascade_counter1" value="false" />
+ <parameter name="gui_cascade_counter10" value="false" />
+ <parameter name="gui_cascade_counter11" value="false" />
+ <parameter name="gui_cascade_counter12" value="false" />
+ <parameter name="gui_cascade_counter13" value="false" />
+ <parameter name="gui_cascade_counter14" value="false" />
+ <parameter name="gui_cascade_counter15" value="false" />
+ <parameter name="gui_cascade_counter16" value="false" />
+ <parameter name="gui_cascade_counter17" value="false" />
+ <parameter name="gui_cascade_counter2" value="false" />
+ <parameter name="gui_cascade_counter3" value="false" />
+ <parameter name="gui_cascade_counter4" value="false" />
+ <parameter name="gui_cascade_counter5" value="false" />
+ <parameter name="gui_cascade_counter6" value="false" />
+ <parameter name="gui_cascade_counter7" value="false" />
+ <parameter name="gui_cascade_counter8" value="false" />
+ <parameter name="gui_cascade_counter9" value="false" />
+ <parameter name="gui_cascade_outclk_index" value="0" />
+ <parameter name="gui_clk_bad" value="false" />
+ <parameter name="gui_clock_name_global" value="false" />
+ <parameter name="gui_clock_name_string0" value="pll_clk200" />
+ <parameter name="gui_clock_name_string1" value="pll_clk200p" />
+ <parameter name="gui_clock_name_string10" value="outclk10" />
+ <parameter name="gui_clock_name_string11" value="outclk11" />
+ <parameter name="gui_clock_name_string12" value="outclk12" />
+ <parameter name="gui_clock_name_string13" value="outclk13" />
+ <parameter name="gui_clock_name_string14" value="outclk14" />
+ <parameter name="gui_clock_name_string15" value="outclk15" />
+ <parameter name="gui_clock_name_string16" value="outclk16" />
+ <parameter name="gui_clock_name_string17" value="outclk17" />
+ <parameter name="gui_clock_name_string2" value="pll_clk400" />
+ <parameter name="gui_clock_name_string3" value="outclk3" />
+ <parameter name="gui_clock_name_string4" value="outclk4" />
+ <parameter name="gui_clock_name_string5" value="outclk5" />
+ <parameter name="gui_clock_name_string6" value="outclk6" />
+ <parameter name="gui_clock_name_string7" value="outclk7" />
+ <parameter name="gui_clock_name_string8" value="outclk8" />
+ <parameter name="gui_clock_name_string9" value="outclk9" />
+ <parameter name="gui_clock_to_compensate" value="0" />
+ <parameter name="gui_device_speed_grade" value="1" />
+ <parameter name="gui_divide_factor_c0" value="6" />
+ <parameter name="gui_divide_factor_c1" value="6" />
+ <parameter name="gui_divide_factor_c10" value="6" />
+ <parameter name="gui_divide_factor_c11" value="6" />
+ <parameter name="gui_divide_factor_c12" value="6" />
+ <parameter name="gui_divide_factor_c13" value="6" />
+ <parameter name="gui_divide_factor_c14" value="6" />
+ <parameter name="gui_divide_factor_c15" value="6" />
+ <parameter name="gui_divide_factor_c16" value="6" />
+ <parameter name="gui_divide_factor_c17" value="6" />
+ <parameter name="gui_divide_factor_c2" value="6" />
+ <parameter name="gui_divide_factor_c3" value="6" />
+ <parameter name="gui_divide_factor_c4" value="6" />
+ <parameter name="gui_divide_factor_c5" value="6" />
+ <parameter name="gui_divide_factor_c6" value="6" />
+ <parameter name="gui_divide_factor_c7" value="6" />
+ <parameter name="gui_divide_factor_c8" value="6" />
+ <parameter name="gui_divide_factor_c9" value="6" />
+ <parameter name="gui_divide_factor_n" value="1" />
+ <parameter name="gui_dps_cntr" value="C0" />
+ <parameter name="gui_dps_dir" value="Positive" />
+ <parameter name="gui_dps_num" value="1" />
+ <parameter name="gui_dsm_out_sel" value="1st_order" />
+ <parameter name="gui_duty_cycle0" value="50.0" />
+ <parameter name="gui_duty_cycle1" value="50.0" />
+ <parameter name="gui_duty_cycle10" value="50.0" />
+ <parameter name="gui_duty_cycle11" value="50.0" />
+ <parameter name="gui_duty_cycle12" value="50.0" />
+ <parameter name="gui_duty_cycle13" value="50.0" />
+ <parameter name="gui_duty_cycle14" value="50.0" />
+ <parameter name="gui_duty_cycle15" value="50.0" />
+ <parameter name="gui_duty_cycle16" value="50.0" />
+ <parameter name="gui_duty_cycle17" value="50.0" />
+ <parameter name="gui_duty_cycle2" value="50.0" />
+ <parameter name="gui_duty_cycle3" value="50.0" />
+ <parameter name="gui_duty_cycle4" value="50.0" />
+ <parameter name="gui_duty_cycle5" value="50.0" />
+ <parameter name="gui_duty_cycle6" value="50.0" />
+ <parameter name="gui_duty_cycle7" value="50.0" />
+ <parameter name="gui_duty_cycle8" value="50.0" />
+ <parameter name="gui_duty_cycle9" value="50.0" />
+ <parameter name="gui_en_adv_params" value="false" />
+ <parameter name="gui_en_dps_ports" value="false" />
+ <parameter name="gui_en_extclkout_ports" value="false" />
+ <parameter name="gui_en_lvds_ports" value="Disabled" />
+ <parameter name="gui_en_phout_ports" value="false" />
+ <parameter name="gui_en_reconf" value="false" />
+ <parameter name="gui_enable_cascade_in" value="false" />
+ <parameter name="gui_enable_cascade_out" value="false" />
+ <parameter name="gui_enable_mif_dps" value="false" />
+ <parameter name="gui_enable_output_counter_cascading" value="false" />
+ <parameter name="gui_existing_mif_file_path" value="~/pll.mif" />
+ <parameter name="gui_extclkout_0_source" value="C0" />
+ <parameter name="gui_extclkout_1_source" value="C0" />
+ <parameter name="gui_feedback_clock" value="Global Clock" />
+ <parameter name="gui_fix_vco_frequency" value="false" />
+ <parameter name="gui_fixed_vco_frequency" value="600.0" />
+ <parameter name="gui_frac_multiply_factor" value="1" />
+ <parameter name="gui_fractional_cout" value="32" />
+ <parameter name="gui_lock_setting" value="Low Lock Time" />
+ <parameter name="gui_mif_config_name" value="unnamed" />
+ <parameter name="gui_mif_gen_options">Generate New MIF File</parameter>
+ <parameter name="gui_multiply_factor" value="6" />
+ <parameter name="gui_new_mif_file_path" value="~/pll.mif" />
+ <parameter name="gui_number_of_clocks" value="3" />
+ <parameter name="gui_operation_mode" value="direct" />
+ <parameter name="gui_output_clock_frequency0" value="200.0" />
+ <parameter name="gui_output_clock_frequency1" value="200.0" />
+ <parameter name="gui_output_clock_frequency10" value="100.0" />
+ <parameter name="gui_output_clock_frequency11" value="100.0" />
+ <parameter name="gui_output_clock_frequency12" value="100.0" />
+ <parameter name="gui_output_clock_frequency13" value="100.0" />
+ <parameter name="gui_output_clock_frequency14" value="100.0" />
+ <parameter name="gui_output_clock_frequency15" value="100.0" />
+ <parameter name="gui_output_clock_frequency16" value="100.0" />
+ <parameter name="gui_output_clock_frequency17" value="100.0" />
+ <parameter name="gui_output_clock_frequency2" value="400.0" />
+ <parameter name="gui_output_clock_frequency3" value="100.0" />
+ <parameter name="gui_output_clock_frequency4" value="100.0" />
+ <parameter name="gui_output_clock_frequency5" value="100.0" />
+ <parameter name="gui_output_clock_frequency6" value="100.0" />
+ <parameter name="gui_output_clock_frequency7" value="100.0" />
+ <parameter name="gui_output_clock_frequency8" value="100.0" />
+ <parameter name="gui_output_clock_frequency9" value="100.0" />
+ <parameter name="gui_phase_shift0" value="0.0" />
+ <parameter name="gui_phase_shift1" value="0.0" />
+ <parameter name="gui_phase_shift10" value="0.0" />
+ <parameter name="gui_phase_shift11" value="0.0" />
+ <parameter name="gui_phase_shift12" value="0.0" />
+ <parameter name="gui_phase_shift13" value="0.0" />
+ <parameter name="gui_phase_shift14" value="0.0" />
+ <parameter name="gui_phase_shift15" value="0.0" />
+ <parameter name="gui_phase_shift16" value="0.0" />
+ <parameter name="gui_phase_shift17" value="0.0" />
+ <parameter name="gui_phase_shift2" value="0.0" />
+ <parameter name="gui_phase_shift3" value="0.0" />
+ <parameter name="gui_phase_shift4" value="0.0" />
+ <parameter name="gui_phase_shift5" value="0.0" />
+ <parameter name="gui_phase_shift6" value="0.0" />
+ <parameter name="gui_phase_shift7" value="0.0" />
+ <parameter name="gui_phase_shift8" value="0.0" />
+ <parameter name="gui_phase_shift9" value="0.0" />
+ <parameter name="gui_phase_shift_deg0" value="0.0" />
+ <parameter name="gui_phase_shift_deg1" value="0.0" />
+ <parameter name="gui_phase_shift_deg10" value="0.0" />
+ <parameter name="gui_phase_shift_deg11" value="0.0" />
+ <parameter name="gui_phase_shift_deg12" value="0.0" />
+ <parameter name="gui_phase_shift_deg13" value="0.0" />
+ <parameter name="gui_phase_shift_deg14" value="0.0" />
+ <parameter name="gui_phase_shift_deg15" value="0.0" />
+ <parameter name="gui_phase_shift_deg16" value="0.0" />
+ <parameter name="gui_phase_shift_deg17" value="0.0" />
+ <parameter name="gui_phase_shift_deg2" value="0.0" />
+ <parameter name="gui_phase_shift_deg3" value="0.0" />
+ <parameter name="gui_phase_shift_deg4" value="0.0" />
+ <parameter name="gui_phase_shift_deg5" value="0.0" />
+ <parameter name="gui_phase_shift_deg6" value="0.0" />
+ <parameter name="gui_phase_shift_deg7" value="0.0" />
+ <parameter name="gui_phase_shift_deg8" value="0.0" />
+ <parameter name="gui_phase_shift_deg9" value="0.0" />
+ <parameter name="gui_phout_division" value="1" />
+ <parameter name="gui_pll_auto_reset" value="false" />
+ <parameter name="gui_pll_bandwidth_preset" value="Low" />
+ <parameter name="gui_pll_cascading_mode" value="adjpllin" />
+ <parameter name="gui_pll_mode" value="Integer-N PLL" />
+ <parameter name="gui_ps_units0" value="ps" />
+ <parameter name="gui_ps_units1" value="ps" />
+ <parameter name="gui_ps_units10" value="ps" />
+ <parameter name="gui_ps_units11" value="ps" />
+ <parameter name="gui_ps_units12" value="ps" />
+ <parameter name="gui_ps_units13" value="ps" />
+ <parameter name="gui_ps_units14" value="ps" />
+ <parameter name="gui_ps_units15" value="ps" />
+ <parameter name="gui_ps_units16" value="ps" />
+ <parameter name="gui_ps_units17" value="ps" />
+ <parameter name="gui_ps_units2" value="ps" />
+ <parameter name="gui_ps_units3" value="ps" />
+ <parameter name="gui_ps_units4" value="ps" />
+ <parameter name="gui_ps_units5" value="ps" />
+ <parameter name="gui_ps_units6" value="ps" />
+ <parameter name="gui_ps_units7" value="ps" />
+ <parameter name="gui_ps_units8" value="ps" />
+ <parameter name="gui_ps_units9" value="ps" />
+ <parameter name="gui_refclk1_frequency" value="100.0" />
+ <parameter name="gui_refclk_switch" value="false" />
+ <parameter name="gui_reference_clock_frequency" value="200.0" />
+ <parameter name="gui_switchover_delay" value="0" />
+ <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+ <parameter name="gui_use_NDFB_modes" value="false" />
+ <parameter name="gui_use_locked" value="true" />
+ <parameter name="gui_vco_frequency" value="600.0" />
+ <parameter name="system_info_device_component" value="10AX115S2F45E1SG" />
+ <parameter name="system_info_device_family" value="Arria 10" />
+ <parameter name="system_info_device_speed_grade" value="1" />
+ <parameter name="system_part_trait_speed_grade" value="1" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..ef4a1a818453dc0c080036ebb3fa20c7e51f4a47
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_pll_clk25.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..63bd14dfd32eb1abe8838e751bcdc92eedf0a862
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_pll_clk25
+hdl_library_clause_name = ip_arria10_e1sg_pll_clk25_altera_iopll_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_pll_clk25.qip
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/ip_arria10_e1sg_pll_clk25.qsys b/libraries/technology/ip_arria10_e1sg/pll_clk25/ip_arria10_e1sg_pll_clk25.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..d699b3fd4cea92118584df566cc350eccd161d8a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/ip_arria10_e1sg_pll_clk25.qsys
@@ -0,0 +1,398 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_pll_clk25">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element iopll_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>outclk0</key>
+ <value>
+ <connectionPointName>outclk0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>20000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk1</key>
+ <value>
+ <connectionPointName>outclk1</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>50000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk2</key>
+ <value>
+ <connectionPointName>outclk2</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk3</key>
+ <value>
+ <connectionPointName>outclk3</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>125000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="locked" internal="iopll_0.locked" type="conduit" dir="end">
+ <port name="locked" internal="locked" />
+ </interface>
+ <interface name="outclk0" internal="iopll_0.outclk0" type="clock" dir="start">
+ <port name="outclk_0" internal="outclk_0" />
+ </interface>
+ <interface name="outclk1" internal="iopll_0.outclk1" type="clock" dir="start">
+ <port name="outclk_1" internal="outclk_1" />
+ </interface>
+ <interface name="outclk2" internal="iopll_0.outclk2" type="clock" dir="start">
+ <port name="outclk_2" internal="outclk_2" />
+ </interface>
+ <interface name="outclk3" internal="iopll_0.outclk3" type="clock" dir="start">
+ <port name="outclk_3" internal="outclk_3" />
+ </interface>
+ <interface name="refclk" internal="iopll_0.refclk" type="clock" dir="end">
+ <port name="refclk" internal="refclk" />
+ </interface>
+ <interface name="reset" internal="iopll_0.reset" type="reset" dir="end">
+ <port name="rst" internal="rst" />
+ </interface>
+ <module
+ name="iopll_0"
+ kind="altera_iopll"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="gui_active_clk" value="false" />
+ <parameter name="gui_actual_duty_cycle0" value="50.0" />
+ <parameter name="gui_actual_duty_cycle1" value="50.0" />
+ <parameter name="gui_actual_duty_cycle10" value="50.0" />
+ <parameter name="gui_actual_duty_cycle11" value="50.0" />
+ <parameter name="gui_actual_duty_cycle12" value="50.0" />
+ <parameter name="gui_actual_duty_cycle13" value="50.0" />
+ <parameter name="gui_actual_duty_cycle14" value="50.0" />
+ <parameter name="gui_actual_duty_cycle15" value="50.0" />
+ <parameter name="gui_actual_duty_cycle16" value="50.0" />
+ <parameter name="gui_actual_duty_cycle17" value="50.0" />
+ <parameter name="gui_actual_duty_cycle2" value="50.0" />
+ <parameter name="gui_actual_duty_cycle3" value="50.0" />
+ <parameter name="gui_actual_duty_cycle4" value="50.0" />
+ <parameter name="gui_actual_duty_cycle5" value="50.0" />
+ <parameter name="gui_actual_duty_cycle6" value="50.0" />
+ <parameter name="gui_actual_duty_cycle7" value="50.0" />
+ <parameter name="gui_actual_duty_cycle8" value="50.0" />
+ <parameter name="gui_actual_duty_cycle9" value="50.0" />
+ <parameter name="gui_actual_output_clock_frequency0" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency1" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency10" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency11" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency12" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency13" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency14" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency15" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency16" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency17" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency2" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency3" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency4" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency5" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency6" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency7" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency8" value="100.0" />
+ <parameter name="gui_actual_output_clock_frequency9" value="100.0" />
+ <parameter name="gui_actual_phase_shift0" value="0.0" />
+ <parameter name="gui_actual_phase_shift1" value="0.0" />
+ <parameter name="gui_actual_phase_shift10" value="0.0" />
+ <parameter name="gui_actual_phase_shift11" value="0.0" />
+ <parameter name="gui_actual_phase_shift12" value="0.0" />
+ <parameter name="gui_actual_phase_shift13" value="0.0" />
+ <parameter name="gui_actual_phase_shift14" value="0.0" />
+ <parameter name="gui_actual_phase_shift15" value="0.0" />
+ <parameter name="gui_actual_phase_shift16" value="0.0" />
+ <parameter name="gui_actual_phase_shift17" value="0.0" />
+ <parameter name="gui_actual_phase_shift2" value="0.0" />
+ <parameter name="gui_actual_phase_shift3" value="0.0" />
+ <parameter name="gui_actual_phase_shift4" value="0.0" />
+ <parameter name="gui_actual_phase_shift5" value="0.0" />
+ <parameter name="gui_actual_phase_shift6" value="0.0" />
+ <parameter name="gui_actual_phase_shift7" value="0.0" />
+ <parameter name="gui_actual_phase_shift8" value="0.0" />
+ <parameter name="gui_actual_phase_shift9" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg0" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg1" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg10" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg11" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg12" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg13" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg14" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg15" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg16" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg17" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg2" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg3" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg4" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg5" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg6" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg7" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg8" value="0.0" />
+ <parameter name="gui_actual_phase_shift_deg9" value="0.0" />
+ <parameter name="gui_cascade_counter0" value="false" />
+ <parameter name="gui_cascade_counter1" value="false" />
+ <parameter name="gui_cascade_counter10" value="false" />
+ <parameter name="gui_cascade_counter11" value="false" />
+ <parameter name="gui_cascade_counter12" value="false" />
+ <parameter name="gui_cascade_counter13" value="false" />
+ <parameter name="gui_cascade_counter14" value="false" />
+ <parameter name="gui_cascade_counter15" value="false" />
+ <parameter name="gui_cascade_counter16" value="false" />
+ <parameter name="gui_cascade_counter17" value="false" />
+ <parameter name="gui_cascade_counter2" value="false" />
+ <parameter name="gui_cascade_counter3" value="false" />
+ <parameter name="gui_cascade_counter4" value="false" />
+ <parameter name="gui_cascade_counter5" value="false" />
+ <parameter name="gui_cascade_counter6" value="false" />
+ <parameter name="gui_cascade_counter7" value="false" />
+ <parameter name="gui_cascade_counter8" value="false" />
+ <parameter name="gui_cascade_counter9" value="false" />
+ <parameter name="gui_cascade_outclk_index" value="0" />
+ <parameter name="gui_clk_bad" value="false" />
+ <parameter name="gui_clock_name_global" value="false" />
+ <parameter name="gui_clock_name_string0" value="pll_clk20" />
+ <parameter name="gui_clock_name_string1" value="pll_clk50" />
+ <parameter name="gui_clock_name_string10" value="outclk10" />
+ <parameter name="gui_clock_name_string11" value="outclk11" />
+ <parameter name="gui_clock_name_string12" value="outclk12" />
+ <parameter name="gui_clock_name_string13" value="outclk13" />
+ <parameter name="gui_clock_name_string14" value="outclk14" />
+ <parameter name="gui_clock_name_string15" value="outclk15" />
+ <parameter name="gui_clock_name_string16" value="outclk16" />
+ <parameter name="gui_clock_name_string17" value="outclk17" />
+ <parameter name="gui_clock_name_string2" value="pll_clk100" />
+ <parameter name="gui_clock_name_string3" value="pll_clk125" />
+ <parameter name="gui_clock_name_string4" value="outclk4" />
+ <parameter name="gui_clock_name_string5" value="outclk5" />
+ <parameter name="gui_clock_name_string6" value="outclk6" />
+ <parameter name="gui_clock_name_string7" value="outclk7" />
+ <parameter name="gui_clock_name_string8" value="outclk8" />
+ <parameter name="gui_clock_name_string9" value="outclk9" />
+ <parameter name="gui_clock_to_compensate" value="0" />
+ <parameter name="gui_device_speed_grade" value="1" />
+ <parameter name="gui_divide_factor_c0" value="6" />
+ <parameter name="gui_divide_factor_c1" value="6" />
+ <parameter name="gui_divide_factor_c10" value="6" />
+ <parameter name="gui_divide_factor_c11" value="6" />
+ <parameter name="gui_divide_factor_c12" value="6" />
+ <parameter name="gui_divide_factor_c13" value="6" />
+ <parameter name="gui_divide_factor_c14" value="6" />
+ <parameter name="gui_divide_factor_c15" value="6" />
+ <parameter name="gui_divide_factor_c16" value="6" />
+ <parameter name="gui_divide_factor_c17" value="6" />
+ <parameter name="gui_divide_factor_c2" value="6" />
+ <parameter name="gui_divide_factor_c3" value="6" />
+ <parameter name="gui_divide_factor_c4" value="6" />
+ <parameter name="gui_divide_factor_c5" value="6" />
+ <parameter name="gui_divide_factor_c6" value="6" />
+ <parameter name="gui_divide_factor_c7" value="6" />
+ <parameter name="gui_divide_factor_c8" value="6" />
+ <parameter name="gui_divide_factor_c9" value="6" />
+ <parameter name="gui_divide_factor_n" value="1" />
+ <parameter name="gui_dps_cntr" value="C0" />
+ <parameter name="gui_dps_dir" value="Positive" />
+ <parameter name="gui_dps_num" value="1" />
+ <parameter name="gui_dsm_out_sel" value="1st_order" />
+ <parameter name="gui_duty_cycle0" value="50.0" />
+ <parameter name="gui_duty_cycle1" value="50.0" />
+ <parameter name="gui_duty_cycle10" value="50.0" />
+ <parameter name="gui_duty_cycle11" value="50.0" />
+ <parameter name="gui_duty_cycle12" value="50.0" />
+ <parameter name="gui_duty_cycle13" value="50.0" />
+ <parameter name="gui_duty_cycle14" value="50.0" />
+ <parameter name="gui_duty_cycle15" value="50.0" />
+ <parameter name="gui_duty_cycle16" value="50.0" />
+ <parameter name="gui_duty_cycle17" value="50.0" />
+ <parameter name="gui_duty_cycle2" value="50.0" />
+ <parameter name="gui_duty_cycle3" value="50.0" />
+ <parameter name="gui_duty_cycle4" value="50.0" />
+ <parameter name="gui_duty_cycle5" value="50.0" />
+ <parameter name="gui_duty_cycle6" value="50.0" />
+ <parameter name="gui_duty_cycle7" value="50.0" />
+ <parameter name="gui_duty_cycle8" value="50.0" />
+ <parameter name="gui_duty_cycle9" value="50.0" />
+ <parameter name="gui_en_adv_params" value="false" />
+ <parameter name="gui_en_dps_ports" value="false" />
+ <parameter name="gui_en_extclkout_ports" value="false" />
+ <parameter name="gui_en_lvds_ports" value="Disabled" />
+ <parameter name="gui_en_phout_ports" value="false" />
+ <parameter name="gui_en_reconf" value="false" />
+ <parameter name="gui_enable_cascade_in" value="false" />
+ <parameter name="gui_enable_cascade_out" value="false" />
+ <parameter name="gui_enable_mif_dps" value="false" />
+ <parameter name="gui_enable_output_counter_cascading" value="false" />
+ <parameter name="gui_existing_mif_file_path" value="~/pll.mif" />
+ <parameter name="gui_extclkout_0_source" value="C0" />
+ <parameter name="gui_extclkout_1_source" value="C0" />
+ <parameter name="gui_feedback_clock" value="Global Clock" />
+ <parameter name="gui_fix_vco_frequency" value="false" />
+ <parameter name="gui_fixed_vco_frequency" value="600.0" />
+ <parameter name="gui_frac_multiply_factor" value="1" />
+ <parameter name="gui_fractional_cout" value="32" />
+ <parameter name="gui_lock_setting" value="Low Lock Time" />
+ <parameter name="gui_mif_config_name" value="unnamed" />
+ <parameter name="gui_mif_gen_options">Generate New MIF File</parameter>
+ <parameter name="gui_multiply_factor" value="6" />
+ <parameter name="gui_new_mif_file_path" value="~/pll.mif" />
+ <parameter name="gui_number_of_clocks" value="4" />
+ <parameter name="gui_operation_mode" value="direct" />
+ <parameter name="gui_output_clock_frequency0" value="20.0" />
+ <parameter name="gui_output_clock_frequency1" value="50.0" />
+ <parameter name="gui_output_clock_frequency10" value="100.0" />
+ <parameter name="gui_output_clock_frequency11" value="100.0" />
+ <parameter name="gui_output_clock_frequency12" value="100.0" />
+ <parameter name="gui_output_clock_frequency13" value="100.0" />
+ <parameter name="gui_output_clock_frequency14" value="100.0" />
+ <parameter name="gui_output_clock_frequency15" value="100.0" />
+ <parameter name="gui_output_clock_frequency16" value="100.0" />
+ <parameter name="gui_output_clock_frequency17" value="100.0" />
+ <parameter name="gui_output_clock_frequency2" value="100.0" />
+ <parameter name="gui_output_clock_frequency3" value="125.0" />
+ <parameter name="gui_output_clock_frequency4" value="100.0" />
+ <parameter name="gui_output_clock_frequency5" value="100.0" />
+ <parameter name="gui_output_clock_frequency6" value="100.0" />
+ <parameter name="gui_output_clock_frequency7" value="100.0" />
+ <parameter name="gui_output_clock_frequency8" value="100.0" />
+ <parameter name="gui_output_clock_frequency9" value="100.0" />
+ <parameter name="gui_phase_shift0" value="0.0" />
+ <parameter name="gui_phase_shift1" value="0.0" />
+ <parameter name="gui_phase_shift10" value="0.0" />
+ <parameter name="gui_phase_shift11" value="0.0" />
+ <parameter name="gui_phase_shift12" value="0.0" />
+ <parameter name="gui_phase_shift13" value="0.0" />
+ <parameter name="gui_phase_shift14" value="0.0" />
+ <parameter name="gui_phase_shift15" value="0.0" />
+ <parameter name="gui_phase_shift16" value="0.0" />
+ <parameter name="gui_phase_shift17" value="0.0" />
+ <parameter name="gui_phase_shift2" value="0.0" />
+ <parameter name="gui_phase_shift3" value="0.0" />
+ <parameter name="gui_phase_shift4" value="0.0" />
+ <parameter name="gui_phase_shift5" value="0.0" />
+ <parameter name="gui_phase_shift6" value="0.0" />
+ <parameter name="gui_phase_shift7" value="0.0" />
+ <parameter name="gui_phase_shift8" value="0.0" />
+ <parameter name="gui_phase_shift9" value="0.0" />
+ <parameter name="gui_phase_shift_deg0" value="0.0" />
+ <parameter name="gui_phase_shift_deg1" value="0.0" />
+ <parameter name="gui_phase_shift_deg10" value="0.0" />
+ <parameter name="gui_phase_shift_deg11" value="0.0" />
+ <parameter name="gui_phase_shift_deg12" value="0.0" />
+ <parameter name="gui_phase_shift_deg13" value="0.0" />
+ <parameter name="gui_phase_shift_deg14" value="0.0" />
+ <parameter name="gui_phase_shift_deg15" value="0.0" />
+ <parameter name="gui_phase_shift_deg16" value="0.0" />
+ <parameter name="gui_phase_shift_deg17" value="0.0" />
+ <parameter name="gui_phase_shift_deg2" value="0.0" />
+ <parameter name="gui_phase_shift_deg3" value="0.0" />
+ <parameter name="gui_phase_shift_deg4" value="0.0" />
+ <parameter name="gui_phase_shift_deg5" value="0.0" />
+ <parameter name="gui_phase_shift_deg6" value="0.0" />
+ <parameter name="gui_phase_shift_deg7" value="0.0" />
+ <parameter name="gui_phase_shift_deg8" value="0.0" />
+ <parameter name="gui_phase_shift_deg9" value="0.0" />
+ <parameter name="gui_phout_division" value="1" />
+ <parameter name="gui_pll_auto_reset" value="false" />
+ <parameter name="gui_pll_bandwidth_preset" value="Low" />
+ <parameter name="gui_pll_cascading_mode" value="adjpllin" />
+ <parameter name="gui_pll_mode" value="Integer-N PLL" />
+ <parameter name="gui_ps_units0" value="ps" />
+ <parameter name="gui_ps_units1" value="ps" />
+ <parameter name="gui_ps_units10" value="ps" />
+ <parameter name="gui_ps_units11" value="ps" />
+ <parameter name="gui_ps_units12" value="ps" />
+ <parameter name="gui_ps_units13" value="ps" />
+ <parameter name="gui_ps_units14" value="ps" />
+ <parameter name="gui_ps_units15" value="ps" />
+ <parameter name="gui_ps_units16" value="ps" />
+ <parameter name="gui_ps_units17" value="ps" />
+ <parameter name="gui_ps_units2" value="ps" />
+ <parameter name="gui_ps_units3" value="ps" />
+ <parameter name="gui_ps_units4" value="ps" />
+ <parameter name="gui_ps_units5" value="ps" />
+ <parameter name="gui_ps_units6" value="ps" />
+ <parameter name="gui_ps_units7" value="ps" />
+ <parameter name="gui_ps_units8" value="ps" />
+ <parameter name="gui_ps_units9" value="ps" />
+ <parameter name="gui_refclk1_frequency" value="100.0" />
+ <parameter name="gui_refclk_switch" value="false" />
+ <parameter name="gui_reference_clock_frequency" value="25.0" />
+ <parameter name="gui_switchover_delay" value="0" />
+ <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+ <parameter name="gui_use_NDFB_modes" value="false" />
+ <parameter name="gui_use_locked" value="true" />
+ <parameter name="gui_vco_frequency" value="600.0" />
+ <parameter name="system_info_device_component" value="10AX115S2F45E1SG" />
+ <parameter name="system_info_device_family" value="Arria 10" />
+ <parameter name="system_info_device_speed_grade" value="1" />
+ <parameter name="system_part_trait_speed_grade" value="1" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..77f31d835c09eb748bbf8d85c9d4b808bdd3cdfa
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_pll_xgmii_mac_clocks.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..3e585d95929ab27cb38a4413369274ceab9a16fe
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_pll_xgmii_mac_clocks
+hdl_library_clause_name = ip_arria10_e1sg_pll_xgmii_mac_clocks_altera_xcvr_fpll_a10_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qsys b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..0a7e0ca642c3677c155034e955147397d65d6670
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qsys
@@ -0,0 +1,235 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_pll_xgmii_mac_clocks">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element xcvr_fpll_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>outclk0</key>
+ <value>
+ <connectionPointName>outclk0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>outclk1</key>
+ <value>
+ <connectionPointName>outclk1</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>100000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="outclk0"
+ internal="xcvr_fpll_a10_0.outclk0"
+ type="clock"
+ dir="start">
+ <port name="outclk0" internal="outclk0" />
+ </interface>
+ <interface
+ name="outclk1"
+ internal="xcvr_fpll_a10_0.outclk1"
+ type="clock"
+ dir="start">
+ <port name="outclk1" internal="outclk1" />
+ </interface>
+ <interface
+ name="pll_cal_busy"
+ internal="xcvr_fpll_a10_0.pll_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="pll_cal_busy" internal="pll_cal_busy" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="xcvr_fpll_a10_0.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="xcvr_fpll_a10_0.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_refclk0"
+ internal="xcvr_fpll_a10_0.pll_refclk0"
+ type="clock"
+ dir="end">
+ <port name="pll_refclk0" internal="pll_refclk0" />
+ </interface>
+ <module
+ name="xcvr_fpll_a10_0"
+ kind="altera_xcvr_fpll_a10"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="enable_analog_resets" value="0" />
+ <parameter name="enable_bonding_clks" value="0" />
+ <parameter name="enable_ext_lockdetect_ports" value="0" />
+ <parameter name="enable_fb_comp_bonding" value="0" />
+ <parameter name="enable_hfreq_clk" value="0" />
+ <parameter name="enable_mcgb" value="0" />
+ <parameter name="enable_mcgb_pcie_clksw" value="0" />
+ <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
+ <parameter name="enable_pll_reconfig" value="0" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="gui_actual_outclk0_frequency" value="100.0" />
+ <parameter name="gui_actual_outclk1_frequency" value="100.0" />
+ <parameter name="gui_actual_outclk2_frequency" value="100.0" />
+ <parameter name="gui_actual_outclk3_frequency" value="100.0" />
+ <parameter name="gui_actual_refclk_frequency" value="100.0" />
+ <parameter name="gui_bw_sel" value="low" />
+ <parameter name="gui_cascade_outclk_index" value="0" />
+ <parameter name="gui_desired_hssi_cascade_frequency" value="100.0" />
+ <parameter name="gui_desired_outclk0_frequency" value="156.25" />
+ <parameter name="gui_desired_outclk1_frequency" value="312.5" />
+ <parameter name="gui_desired_outclk2_frequency" value="100.0" />
+ <parameter name="gui_desired_outclk3_frequency" value="100.0" />
+ <parameter name="gui_desired_refclk_frequency" value="100.0" />
+ <parameter name="gui_enable_active_clk" value="false" />
+ <parameter name="gui_enable_cascade_out" value="false" />
+ <parameter name="gui_enable_clk_bad" value="false" />
+ <parameter name="gui_enable_dps" value="false" />
+ <parameter name="gui_enable_fractional" value="false" />
+ <parameter name="gui_enable_hip_cal_done_port" value="0" />
+ <parameter name="gui_enable_manual_config" value="false" />
+ <parameter name="gui_enable_manual_hssi_counters" value="false" />
+ <parameter name="gui_enable_phase_alignment" value="false" />
+ <parameter name="gui_enable_pld_cal_busy_port" value="1" />
+ <parameter name="gui_fpll_mode" value="0" />
+ <parameter name="gui_fractional_x" value="32" />
+ <parameter name="gui_hip_cal_en" value="0" />
+ <parameter name="gui_hssi_output_clock_frequency" value="1250.0" />
+ <parameter name="gui_hssi_prot_mode" value="0" />
+ <parameter name="gui_iqtxrxclk_outclk_index" value="0" />
+ <parameter name="gui_number_of_output_clocks" value="2" />
+ <parameter name="gui_operation_mode" value="0" />
+ <parameter name="gui_outclk0_actual_phase_shift" value="0.0" />
+ <parameter name="gui_outclk0_actual_phase_shift_deg" value="0.0" />
+ <parameter name="gui_outclk0_desired_phase_shift" value="0.0" />
+ <parameter name="gui_outclk0_phase_shift_unit" value="0" />
+ <parameter name="gui_outclk1_actual_phase_shift" value="0.0" />
+ <parameter name="gui_outclk1_actual_phase_shift_deg" value="0.0" />
+ <parameter name="gui_outclk1_desired_phase_shift" value="0" />
+ <parameter name="gui_outclk1_phase_shift_unit" value="0" />
+ <parameter name="gui_outclk2_actual_phase_shift" value="0 ps" />
+ <parameter name="gui_outclk2_actual_phase_shift_deg" value="0 deg" />
+ <parameter name="gui_outclk2_desired_phase_shift" value="0" />
+ <parameter name="gui_outclk2_phase_shift_unit" value="0" />
+ <parameter name="gui_outclk3_actual_phase_shift" value="0.0" />
+ <parameter name="gui_outclk3_actual_phase_shift_deg" value="0.0" />
+ <parameter name="gui_outclk3_desired_phase_shift" value="0" />
+ <parameter name="gui_outclk3_phase_shift_unit" value="0" />
+ <parameter name="gui_pll_c_counter_0" value="1" />
+ <parameter name="gui_pll_c_counter_1" value="1" />
+ <parameter name="gui_pll_c_counter_2" value="1" />
+ <parameter name="gui_pll_c_counter_3" value="1" />
+ <parameter name="gui_pll_dsm_fractional_division" value="1" />
+ <parameter name="gui_pll_m_counter" value="1" />
+ <parameter name="gui_pll_n_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_k_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_l_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_m_counter" value="1" />
+ <parameter name="gui_pll_set_hssi_n_counter" value="1" />
+ <parameter name="gui_refclk1_frequency" value="100.0" />
+ <parameter name="gui_refclk_cnt" value="1" />
+ <parameter name="gui_refclk_index" value="0" />
+ <parameter name="gui_refclk_switch" value="false" />
+ <parameter name="gui_reference_clock_frequency" value="644.53125" />
+ <parameter name="gui_self_reset_enabled" value="false" />
+ <parameter name="gui_switchover_delay" value="0" />
+ <parameter name="gui_switchover_mode">Automatic Switchover</parameter>
+ <parameter name="mcgb_aux_clkin_cnt" value="0" />
+ <parameter name="mcgb_div" value="1" />
+ <parameter name="phase_alignment_check_var" value="false" />
+ <parameter name="pma_width" value="64" />
+ <parameter name="rcfg_debug" value="0" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_fpll_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="0" />
+ <parameter name="rcfg_mif_file_enable" value="0" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_data0" value="" />
+ <parameter name="rcfg_profile_data1" value="" />
+ <parameter name="rcfg_profile_data2" value="" />
+ <parameter name="rcfg_profile_data3" value="" />
+ <parameter name="rcfg_profile_data4" value="" />
+ <parameter name="rcfg_profile_data5" value="" />
+ <parameter name="rcfg_profile_data6" value="" />
+ <parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_sv_file_enable" value="0" />
+ <parameter name="rcfg_txt_file_enable" value="0" />
+ <parameter name="set_altera_xcvr_fpll_a10_calibration_en" value="1" />
+ <parameter name="set_capability_reg_enable" value="0" />
+ <parameter name="set_csr_soft_logic_enable" value="0" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="silicon_rev" value="false" />
+ <parameter name="support_mode" value="user_mode" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/ram/README.txt b/libraries/technology/ip_arria10_e1sg/ram/README.txt
new file mode 100755
index 0000000000000000000000000000000000000000..334f704974a248b117cd90c5b6b1af9286c49322
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ram/README.txt
@@ -0,0 +1,97 @@
+README.txt for $RADIOHDL/libraries/technology/ip_arria10/ram
+
+Contents:
+
+1) RAM components
+2) ROM components
+3) Arria10 IP
+4) Inferred IP
+5) Memory initialisation file
+6) Implementation options (LUTs or block RAM)
+7) Synthesis trials
+
+
+1) RAM components:
+
+ ip_arria10_ram_crwk_crw = Two read/write ports each port with own port clock and with power of two ratio between port widths
+ ip_arria10_ram_crw_crw = Two read/write ports each port with own port clock and with same address and data width on both ports
+ ip_arria10_ram_cr_cw = One read port with clock and one write port with clock and with same address and data width on both ports
+ ip_arria10_ram_r_w = Single clock, one read port and one write port and with same address and data width on both ports
+
+
+2) ROM components:
+ ip_arria10_rom_r_w = Not available and not needed, because the ip_arria10_ram_r_w can be used for ROM IP by not connecting the
+ write port.
+
+
+3) Arria10 IP
+
+ The IP only needs to be generated with
+
+ ./generate_ip.sh
+
+ if it need to be modified, because the ip_arria10_ram_*.vhd directly instantiates the altera_syncram component.
+
+ The instantiation is copied manually from the generated/ip_arria10_ram_*/ram_2port_140/sim/ip_arria10_ram_*.vhd.
+
+ It appears that the altera_syncram component can be synthesized even though it comes from the altera_lnsim package,
+ that is a simulation package. However it resembles how it worked for Straix IV with altera_mf.
+
+
+4) Inferred IP
+
+ The inferred Altera code was obtained using template insert with Quartus 14.0a10.
+ The ram_crwk_crw can not be inferred.
+ For the other RAM the g_inferred generic is set to FALSE because the inferred instances do not yet support g_init_file.
+ It is possible to init the RAM using a function e.g.:
+
+ function init_ram
+ return memory_t is
+ variable tmp : memory_t := (others => (others => '0'));
+ begin
+ for addr_pos in 0 to 2**ADDR_WIDTH - 1 loop
+ -- Initialize each address with the address itself
+ tmp(addr_pos) := std_logic_vector(to_unsigned(addr_pos, DATA_WIDTH));
+ end loop;
+ return tmp;
+ end init_ram;
+
+ -- Declare the RAM signal and specify a default value. Quartus II
+ -- will create a memory initialization file (.mif) based on the
+ -- default value.
+ signal ram : memory_t := init_ram;
+
+5) Memory initialisation file
+
+ To support the g_init_file requires first reading the file in a certain format. For us an integer format or SLV format
+ with one value per line (line number = address) would be fine. Using SLV format is necessary if the RAM data is wider
+ than 32 bit, because VHDL integer range is only 2**32. The tb_common_pkg has functiosn to read such a file. Quartus
+ creates a mif file from this when it infers the RAM. However our current UniBoard1 designs provide a mif file that fits
+ the RAM IP. Therefore it is easier initially to also use the RAM IP for Arria10. In future for RadioHDL a generic
+ RAM init file format is preferrable though.
+
+
+6) Implementation options (LUTs or block RAM)
+
+ The IP and inferred RAM can be set to use LUTs (MLAB) or block RAM (M20K), however this is not supported yet.
+
+ . For IP RAM this would imply adding a generic to set the appropriate parameter in the altera_syncram
+ . For inferred RAM is would imply adding a generic to be used for the syntype attribute.
+ From http://www.alterawiki.com/wiki/Mapping_SRLs_to_registers,_MLABs,_or_Block_RAMs:
+
+ entity
+ g_ramstyle : STRING := "MLAB,no_rw_check"
+ architecture
+ attribute ramstyle : string;
+
+ signal ram : memory_t := init_ram;
+ attribute ramstyle of ram : signal is g_ramstyle;
+
+
+7) Synthesis trials
+
+ The quartus/ram.qpf Quartus project was used to verify that the inferred RAM and the block RAM IP actually synthesise
+ to the appropriate FPGA resources.
+ Use the Quartus GUI to manually select a top level component for synthesis e.g. by right clicking the entity vhd file
+ in the file tab of the Quartus project navigator window.
+ Then check the resource usage in the synthesis and fitter reports.
diff --git a/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..3349722ddf66df22d8b2b5b72bec6889fb9ad4f9
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ram/generate_ip.sh
@@ -0,0 +1,50 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Remark:
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+# The IP only needs to be generated if it need to be modified, because the ip_arria10_e1sg_ram_*.vhd directly instantiates
+# the altera_syncram component.
+# The instantiation is copied manually from the generated/ip_arria10_e1sg_ram_*/ram_2port_140/sim/ip_arria10_e1sg_ram_*.vhd.
+# It appears that the altera_syncram component can be synthesized even though it comes from the altera_lnsim package,
+# that is a simulation package. However it resembles how it worked for Straix IV with altera_mf.
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+qsys-generate ip_arria10_e1sg_ram_crwk_crw.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
+qsys-generate ip_arria10_e1sg_ram_crw_crw.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
+qsys-generate ip_arria10_e1sg_ram_cr_cw.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
+qsys-generate ip_arria10_e1sg_ram_r_w.qsys --synthesis=VHDL --simulation=VHDL --output-directory=generated
diff --git a/libraries/technology/ip_arria10_e1sg/ram/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ram/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..11a6f461518fbf997aadf12bf0b161adf4deaff5
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ram/hdllib.cfg
@@ -0,0 +1,24 @@
+hdl_lib_name = ip_arria10_e1sg_ram
+hdl_library_clause_name = ip_arria10_e1sg_ram_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+ ip_arria10_e1sg_true_dual_port_ram_dual_clock.vhd
+ ip_arria10_e1sg_simple_dual_port_ram_dual_clock.vhd
+ ip_arria10_e1sg_simple_dual_port_ram_single_clock.vhd
+
+ ip_arria10_e1sg_ram_crwk_crw.vhd
+ ip_arria10_e1sg_ram_crw_crw.vhd
+ ip_arria10_e1sg_ram_cr_cw.vhd
+ ip_arria10_e1sg_ram_r_w.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.qsys b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..490922f73ca288b657842512cdee16f80083c393
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.qsys
@@ -0,0 +1,131 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_ram_cr_cw">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element ram_2port_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="ram_input"
+ internal="ram_2port_0.ram_input"
+ type="conduit"
+ dir="end">
+ <port name="data" internal="data" />
+ <port name="rdaddress" internal="rdaddress" />
+ <port name="rdclock" internal="rdclock" />
+ <port name="wraddress" internal="wraddress" />
+ <port name="wrclock" internal="wrclock" />
+ <port name="wren" internal="wren" />
+ </interface>
+ <interface
+ name="ram_output"
+ internal="ram_2port_0.ram_output"
+ type="conduit"
+ dir="end">
+ <port name="q" internal="q" />
+ </interface>
+ <module
+ name="ram_2port_0"
+ kind="ram_2port"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_ACLR_READ_INPUT_RDADDRESS" value="false" />
+ <parameter name="GUI_ACLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_ACLR_READ_OUTPUT_QB" value="false" />
+ <parameter name="GUI_BLANK_MEMORY" value="1" />
+ <parameter name="GUI_BYTE_ENABLE_A" value="false" />
+ <parameter name="GUI_BYTE_ENABLE_B" value="false" />
+ <parameter name="GUI_BYTE_ENABLE_WIDTH" value="8" />
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_A" value="false" />
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_B" value="false" />
+ <parameter name="GUI_CLKEN_INPUT_REG_A" value="false" />
+ <parameter name="GUI_CLKEN_INPUT_REG_B" value="false" />
+ <parameter name="GUI_CLKEN_OUTPUT_REG_A" value="false" />
+ <parameter name="GUI_CLKEN_OUTPUT_REG_B" value="false" />
+ <parameter name="GUI_CLKEN_RDADDRESSSTALL" value="false" />
+ <parameter name="GUI_CLKEN_READ_INPUT_REG" value="false" />
+ <parameter name="GUI_CLKEN_READ_OUTPUT_REG" value="false" />
+ <parameter name="GUI_CLKEN_WRADDRESSSTALL" value="false" />
+ <parameter name="GUI_CLKEN_WRITE_INPUT_REG" value="false" />
+ <parameter name="GUI_CLOCK_TYPE" value="1" />
+ <parameter name="GUI_COHERENT_READ" value="false" />
+ <parameter name="GUI_CONSTRAINED_DONT_CARE" value="true" />
+ <parameter name="GUI_DATAA_WIDTH" value="8" />
+ <parameter name="GUI_DIFFERENT_CLKENS" value="false" />
+ <parameter name="GUI_ECCENCBYPASS" value="false" />
+ <parameter name="GUI_ECC_DOUBLE" value="false" />
+ <parameter name="GUI_ECC_PIPELINE" value="false" />
+ <parameter name="GUI_ECC_TRIPLE" value="false" />
+ <parameter name="GUI_FILE_REFERENCE" value="0" />
+ <parameter name="GUI_INIT_FILE_LAYOUT" value="PORT_B" />
+ <parameter name="GUI_INIT_SIM_TO_X" value="false" />
+ <parameter name="GUI_LC_IMPLEMENTION_OPTIONS" value="0" />
+ <parameter name="GUI_MAX_DEPTH" value="Auto" />
+ <parameter name="GUI_MEMSIZE_BITS" value="256" />
+ <parameter name="GUI_MEMSIZE_WORDS" value="32" />
+ <parameter name="GUI_MEM_IN_BITS" value="0" />
+ <parameter name="GUI_MIF_FILENAME" value="./ram_1024.hex" />
+ <parameter name="GUI_MODE" value="0" />
+ <parameter name="GUI_NBE_A" value="false" />
+ <parameter name="GUI_NBE_B" value="false" />
+ <parameter name="GUI_QA_WIDTH" value="8" />
+ <parameter name="GUI_QB_WIDTH" value="8" />
+ <parameter name="GUI_Q_PORT_MODE" value="2" />
+ <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
+ <parameter name="GUI_RDEN_DOUBLE" value="false" />
+ <parameter name="GUI_RDEN_SINGLE" value="false" />
+ <parameter name="GUI_RDW_A_MODE" value="New Data" />
+ <parameter name="GUI_RDW_B_MODE" value="New Data" />
+ <parameter name="GUI_READ_INPUT_RDADDRESS" value="true" />
+ <parameter name="GUI_READ_OUTPUT_QA" value="true" />
+ <parameter name="GUI_READ_OUTPUT_QB" value="true" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QB" value="false" />
+ <parameter name="GUI_TBENCH" value="false" />
+ <parameter name="GUI_VAR_WIDTH" value="false" />
+ <parameter name="GUI_WIDTH_ECCENCPARITY" value="8" />
+ <parameter name="GUI_WRITE_INPUT_PORTS" value="true" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3baa3a14e0b0a9ec4a20e5177b75c42d02d16d55
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
@@ -0,0 +1,160 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- RadioHDL wrapper
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE technology_lib.technology_pkg.all;
+
+LIBRARY altera_lnsim;
+USE altera_lnsim.altera_lnsim_components.all;
+
+ENTITY ip_arria10_e1sg_ram_cr_cw IS
+ GENERIC (
+ g_inferred : BOOLEAN := FALSE;
+ g_adr_w : NATURAL := 5;
+ g_dat_w : NATURAL := 8;
+ g_nof_words : NATURAL := 2**5;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT
+ (
+ data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ rdaddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ wraddress : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ wrclk : IN STD_LOGIC := '1';
+ wren : IN STD_LOGIC := '0';
+ q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+ );
+END ip_arria10_e1sg_ram_cr_cw;
+
+
+ARCHITECTURE SYN OF ip_arria10_e1sg_ram_cr_cw IS
+
+ CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
+
+ COMPONENT altera_syncram
+ GENERIC (
+ address_aclr_b : string;
+ address_reg_b : string;
+ clock_enable_input_a : string;
+ clock_enable_input_b : string;
+ clock_enable_output_b : string;
+ init_file : string;
+ intended_device_family : string;
+ lpm_type : string;
+ numwords_a : integer;
+ numwords_b : integer;
+ operation_mode : string;
+ outdata_aclr_b : string;
+ outdata_reg_b : string;
+ power_up_uninitialized : string;
+ widthad_a : integer;
+ widthad_b : integer;
+ width_a : integer;
+ width_b : integer;
+ width_byteena_a : integer
+ );
+ PORT (
+ address_a : in std_logic_vector(g_adr_w-1 downto 0);
+ address_b : in std_logic_vector(g_adr_w-1 downto 0);
+ clock0 : in std_logic;
+ clock1 : in std_logic;
+ data_a : in std_logic_vector(g_dat_w-1 downto 0);
+ wren_a : in std_logic;
+ q_b : out std_logic_vector(g_dat_w-1 downto 0)
+ );
+ END COMPONENT;
+
+ SIGNAL rdaddr : natural range 0 to g_nof_words - 1;
+ SIGNAL wraddr : natural range 0 to g_nof_words - 1;
+
+ SIGNAL out_q : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ SIGNAL reg_q : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+
+BEGIN
+
+ ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e1sg_ram_cr_cw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
+
+ gen_ip : IF g_inferred=FALSE GENERATE
+ -- Copied from generated/ip_arria10_e1sg_ram_cr_cw/ram_2port_140/sim/ip_arria10_e1sg_ram_cr_cw_ram_2port_140_72tpmcy.vhd
+ u_altera_syncram : altera_syncram
+ GENERIC MAP (
+ address_aclr_b => "NONE",
+ address_reg_b => "CLOCK1",
+ clock_enable_input_a => "BYPASS",
+ clock_enable_input_b => "BYPASS",
+ clock_enable_output_b => "BYPASS",
+ init_file => g_init_file,
+ intended_device_family => "Arria 10",
+ lpm_type => "altera_syncram",
+ numwords_a => g_nof_words,
+ numwords_b => g_nof_words,
+ operation_mode => "DUAL_PORT",
+ outdata_aclr_b => "NONE",
+ outdata_reg_b => c_outdata_reg_b,
+ power_up_uninitialized => "FALSE",
+ widthad_a => g_adr_w,
+ widthad_b => g_adr_w,
+ width_a => g_dat_w,
+ width_b => g_dat_w,
+ width_byteena_a => 1
+ )
+ PORT MAP (
+ address_a => wraddress,
+ address_b => rdaddress,
+ clock0 => wrclk,
+ clock1 => rdclk,
+ data_a => data,
+ wren_a => wren,
+ q_b => q
+ );
+ END GENERATE;
+
+ gen_inferred : IF g_inferred=TRUE GENERATE
+ rdaddr <= TO_INTEGER(UNSIGNED(rdaddress));
+ wraddr <= TO_INTEGER(UNSIGNED(wraddress));
+
+ u_mem : entity work.ip_arria10_e1sg_simple_dual_port_ram_dual_clock
+ generic map (
+ DATA_WIDTH => g_dat_w,
+ ADDR_WIDTH => g_adr_w
+ )
+ port map (
+ rclk => rdclk,
+ wclk => wrclk,
+ raddr => rdaddr,
+ waddr => wraddr,
+ data => data,
+ we => wren,
+ q => out_q
+ );
+
+ reg_q <= out_q WHEN rising_edge(rdclk);
+
+ q <= out_q WHEN g_rd_latency=1 ELSE reg_q;
+ END GENERATE;
+
+END SYN;
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.qsys b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..c78a9c1f663317c7f94beec2c1da3bc9c8646c69
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.qsys
@@ -0,0 +1,134 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_ram_crw_crw">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element ram_2port_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="ram_input"
+ internal="ram_2port_0.ram_input"
+ type="conduit"
+ dir="end">
+ <port name="address_a" internal="address_a" />
+ <port name="address_b" internal="address_b" />
+ <port name="clock_a" internal="clock_a" />
+ <port name="clock_b" internal="clock_b" />
+ <port name="data_a" internal="data_a" />
+ <port name="data_b" internal="data_b" />
+ <port name="wren_a" internal="wren_a" />
+ <port name="wren_b" internal="wren_b" />
+ </interface>
+ <interface
+ name="ram_output"
+ internal="ram_2port_0.ram_output"
+ type="conduit"
+ dir="end">
+ <port name="q_a" internal="q_a" />
+ <port name="q_b" internal="q_b" />
+ </interface>
+ <module
+ name="ram_2port_0"
+ kind="ram_2port"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_ACLR_READ_INPUT_RDADDRESS" value="false" />
+ <parameter name="GUI_ACLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_ACLR_READ_OUTPUT_QB" value="false" />
+ <parameter name="GUI_BLANK_MEMORY" value="1" />
+ <parameter name="GUI_BYTE_ENABLE_A" value="false" />
+ <parameter name="GUI_BYTE_ENABLE_B" value="false" />
+ <parameter name="GUI_BYTE_ENABLE_WIDTH" value="8" />
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_A" value="false" />
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_B" value="false" />
+ <parameter name="GUI_CLKEN_INPUT_REG_A" value="false" />
+ <parameter name="GUI_CLKEN_INPUT_REG_B" value="false" />
+ <parameter name="GUI_CLKEN_OUTPUT_REG_A" value="false" />
+ <parameter name="GUI_CLKEN_OUTPUT_REG_B" value="false" />
+ <parameter name="GUI_CLKEN_RDADDRESSSTALL" value="false" />
+ <parameter name="GUI_CLKEN_READ_INPUT_REG" value="false" />
+ <parameter name="GUI_CLKEN_READ_OUTPUT_REG" value="false" />
+ <parameter name="GUI_CLKEN_WRADDRESSSTALL" value="false" />
+ <parameter name="GUI_CLKEN_WRITE_INPUT_REG" value="false" />
+ <parameter name="GUI_CLOCK_TYPE" value="4" />
+ <parameter name="GUI_COHERENT_READ" value="false" />
+ <parameter name="GUI_CONSTRAINED_DONT_CARE" value="true" />
+ <parameter name="GUI_DATAA_WIDTH" value="8" />
+ <parameter name="GUI_DIFFERENT_CLKENS" value="false" />
+ <parameter name="GUI_ECCENCBYPASS" value="false" />
+ <parameter name="GUI_ECC_DOUBLE" value="false" />
+ <parameter name="GUI_ECC_PIPELINE" value="false" />
+ <parameter name="GUI_ECC_TRIPLE" value="false" />
+ <parameter name="GUI_FILE_REFERENCE" value="0" />
+ <parameter name="GUI_INIT_FILE_LAYOUT" value="PORT_B" />
+ <parameter name="GUI_INIT_SIM_TO_X" value="false" />
+ <parameter name="GUI_LC_IMPLEMENTION_OPTIONS" value="0" />
+ <parameter name="GUI_MAX_DEPTH" value="Auto" />
+ <parameter name="GUI_MEMSIZE_BITS" value="256" />
+ <parameter name="GUI_MEMSIZE_WORDS" value="32" />
+ <parameter name="GUI_MEM_IN_BITS" value="0" />
+ <parameter name="GUI_MIF_FILENAME" value="./ram_1024.hex" />
+ <parameter name="GUI_MODE" value="1" />
+ <parameter name="GUI_NBE_A" value="true" />
+ <parameter name="GUI_NBE_B" value="true" />
+ <parameter name="GUI_QA_WIDTH" value="8" />
+ <parameter name="GUI_QB_WIDTH" value="8" />
+ <parameter name="GUI_Q_PORT_MODE" value="2" />
+ <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
+ <parameter name="GUI_RDEN_DOUBLE" value="false" />
+ <parameter name="GUI_RDEN_SINGLE" value="false" />
+ <parameter name="GUI_RDW_A_MODE" value="New Data" />
+ <parameter name="GUI_RDW_B_MODE" value="New Data" />
+ <parameter name="GUI_READ_INPUT_RDADDRESS" value="true" />
+ <parameter name="GUI_READ_OUTPUT_QA" value="true" />
+ <parameter name="GUI_READ_OUTPUT_QB" value="true" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QB" value="false" />
+ <parameter name="GUI_TBENCH" value="false" />
+ <parameter name="GUI_VAR_WIDTH" value="false" />
+ <parameter name="GUI_WIDTH_ECCENCPARITY" value="8" />
+ <parameter name="GUI_WRITE_INPUT_PORTS" value="true" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bd96396a6d3af597ad880231cf532864d444cb54
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
@@ -0,0 +1,190 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- RadioHDL wrapper
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE technology_lib.technology_pkg.all;
+
+LIBRARY altera_lnsim;
+USE altera_lnsim.altera_lnsim_components.all;
+
+ENTITY ip_arria10_e1sg_ram_crw_crw IS
+ GENERIC (
+ g_inferred : BOOLEAN := FALSE;
+ g_adr_w : NATURAL := 5;
+ g_dat_w : NATURAL := 8;
+ g_nof_words : NATURAL := 2**5;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT
+ (
+ address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
+ clk_a : IN STD_LOGIC := '1';
+ clk_b : IN STD_LOGIC ;
+ data_a : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ data_b : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ wren_a : IN STD_LOGIC := '0';
+ wren_b : IN STD_LOGIC := '0';
+ q_a : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ q_b : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
+ );
+END ip_arria10_e1sg_ram_crw_crw;
+
+
+ARCHITECTURE SYN OF ip_arria10_e1sg_ram_crw_crw IS
+
+ CONSTANT c_outdata_reg_a : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK0");
+ CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
+
+ COMPONENT altera_syncram
+ GENERIC (
+ address_reg_b : string;
+ clock_enable_input_a : string;
+ clock_enable_input_b : string;
+ clock_enable_output_a : string;
+ clock_enable_output_b : string;
+ indata_reg_b : string;
+ init_file : string;
+ intended_device_family : string;
+ lpm_type : string;
+ numwords_a : integer;
+ numwords_b : integer;
+ operation_mode : string;
+ outdata_aclr_a : string;
+ outdata_aclr_b : string;
+ outdata_reg_a : string;
+ outdata_reg_b : string;
+ power_up_uninitialized : string;
+ read_during_write_mode_port_a : string;
+ read_during_write_mode_port_b : string;
+ widthad_a : integer;
+ widthad_b : integer;
+ width_a : integer;
+ width_b : integer;
+ width_byteena_a : integer;
+ width_byteena_b : integer
+ );
+ PORT (
+ address_a : in std_logic_vector(g_adr_w-1 downto 0);
+ address_b : in std_logic_vector(g_adr_w-1 downto 0);
+ clock0 : in std_logic;
+ clock1 : in std_logic;
+ data_a : in std_logic_vector(g_dat_w-1 downto 0);
+ data_b : in std_logic_vector(g_dat_w-1 downto 0);
+ wren_a : in std_logic;
+ wren_b : in std_logic;
+ q_a : out std_logic_vector(g_dat_w - 1 downto 0);
+ q_b : out std_logic_vector(g_dat_w - 1 downto 0)
+ );
+ END COMPONENT;
+
+ SIGNAL addr_a : natural range 0 to g_nof_words - 1;
+ SIGNAL addr_b : natural range 0 to g_nof_words - 1;
+
+ SIGNAL out_a : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ SIGNAL out_b : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+
+ SIGNAL reg_a : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ SIGNAL reg_b : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+
+BEGIN
+
+ ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e1sg_ram_crw_crw : read latency must be 1 (default) or 2" SEVERITY FAILURE;
+
+ gen_ip : IF g_inferred=FALSE GENERATE
+ -- Copied from generated/ip_arria10_e1sg_ram_crw_crw/ram_2port_140/sim/ip_arria10_e1sg_ram_crw_crw_ram_2port_140_ehaf5aa.vhd
+ u_altera_syncram : altera_syncram
+ GENERIC MAP (
+ address_reg_b => "CLOCK1",
+ clock_enable_input_a => "BYPASS",
+ clock_enable_input_b => "BYPASS",
+ clock_enable_output_a => "BYPASS",
+ clock_enable_output_b => "BYPASS",
+ indata_reg_b => "CLOCK1",
+ init_file => g_init_file,
+ intended_device_family => "Arria 10",
+ lpm_type => "altera_syncram",
+ numwords_a => g_nof_words,
+ numwords_b => g_nof_words,
+ operation_mode => "BIDIR_DUAL_PORT",
+ outdata_aclr_a => "NONE",
+ outdata_aclr_b => "NONE",
+ outdata_reg_a => c_outdata_reg_a,
+ outdata_reg_b => c_outdata_reg_b,
+ power_up_uninitialized => "FALSE",
+ read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+ read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+ widthad_a => g_adr_w,
+ widthad_b => g_adr_w,
+ width_a => g_dat_w,
+ width_b => g_dat_w,
+ width_byteena_a => 1,
+ width_byteena_b => 1
+ )
+ PORT MAP (
+ address_a => address_a,
+ address_b => address_b,
+ clock0 => clk_a,
+ clock1 => clk_b,
+ data_a => data_a,
+ data_b => data_b,
+ wren_a => wren_a,
+ wren_b => wren_b,
+ q_a => q_a,
+ q_b => q_b
+ );
+ END GENERATE;
+
+ gen_inferred : IF g_inferred=TRUE GENERATE
+ addr_a <= TO_INTEGER(UNSIGNED(address_a));
+ addr_b <= TO_INTEGER(UNSIGNED(address_b));
+
+ u_mem : entity work.ip_arria10_e1sg_true_dual_port_ram_dual_clock
+ generic map (
+ DATA_WIDTH => g_dat_w,
+ ADDR_WIDTH => g_adr_w
+ )
+ port map (
+ clk_a => clk_a,
+ clk_b => clk_b,
+ addr_a => addr_a,
+ addr_b => addr_b,
+ data_a => data_a,
+ data_b => data_b,
+ we_a => wren_a,
+ we_b => wren_b,
+ q_a => out_a,
+ q_b => out_b
+ );
+
+ reg_a <= out_a WHEN rising_edge(clk_a);
+ reg_b <= out_b WHEN rising_edge(clk_b);
+
+ q_a <= out_a WHEN g_rd_latency=1 ELSE reg_a;
+ q_b <= out_b WHEN g_rd_latency=1 ELSE reg_b;
+ END GENERATE;
+
+END SYN;
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.qsys b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..54ed5d17e9070789382b2d1c9105a8aeae1b2b3f
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.qsys
@@ -0,0 +1,136 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_ram_crwk_crw">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags=""
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element ip_arria10_ram_crwk_crw
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="false" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="ram_input"
+ internal="ip_arria10_ram_crwk_crw.ram_input"
+ type="conduit"
+ dir="end">
+ <port name="address_a" internal="address_a" />
+ <port name="address_b" internal="address_b" />
+ <port name="clock_a" internal="clock_a" />
+ <port name="clock_b" internal="clock_b" />
+ <port name="data_a" internal="data_a" />
+ <port name="data_b" internal="data_b" />
+ <port name="rden_a" internal="rden_a" />
+ <port name="rden_b" internal="rden_b" />
+ <port name="wren_a" internal="wren_a" />
+ <port name="wren_b" internal="wren_b" />
+ </interface>
+ <interface
+ name="ram_output"
+ internal="ip_arria10_ram_crwk_crw.ram_output"
+ type="conduit"
+ dir="end">
+ <port name="q_a" internal="q_a" />
+ <port name="q_b" internal="q_b" />
+ </interface>
+ <module
+ name="ip_arria10_ram_crwk_crw"
+ kind="ram_2port"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_ACLR_READ_INPUT_RDADDRESS" value="false" />
+ <parameter name="GUI_ACLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_ACLR_READ_OUTPUT_QB" value="false" />
+ <parameter name="GUI_BLANK_MEMORY" value="1" />
+ <parameter name="GUI_BYTE_ENABLE_A" value="false" />
+ <parameter name="GUI_BYTE_ENABLE_B" value="false" />
+ <parameter name="GUI_BYTE_ENABLE_WIDTH" value="8" />
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_A" value="false" />
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_B" value="false" />
+ <parameter name="GUI_CLKEN_INPUT_REG_A" value="false" />
+ <parameter name="GUI_CLKEN_INPUT_REG_B" value="false" />
+ <parameter name="GUI_CLKEN_OUTPUT_REG_A" value="false" />
+ <parameter name="GUI_CLKEN_OUTPUT_REG_B" value="false" />
+ <parameter name="GUI_CLKEN_RDADDRESSSTALL" value="false" />
+ <parameter name="GUI_CLKEN_READ_INPUT_REG" value="true" />
+ <parameter name="GUI_CLKEN_READ_OUTPUT_REG" value="true" />
+ <parameter name="GUI_CLKEN_WRADDRESSSTALL" value="false" />
+ <parameter name="GUI_CLKEN_WRITE_INPUT_REG" value="true" />
+ <parameter name="GUI_CLOCK_TYPE" value="4" />
+ <parameter name="GUI_COHERENT_READ" value="false" />
+ <parameter name="GUI_CONSTRAINED_DONT_CARE" value="true" />
+ <parameter name="GUI_DATAA_WIDTH" value="32" />
+ <parameter name="GUI_DIFFERENT_CLKENS" value="false" />
+ <parameter name="GUI_ECCENCBYPASS" value="false" />
+ <parameter name="GUI_ECC_DOUBLE" value="false" />
+ <parameter name="GUI_ECC_PIPELINE" value="false" />
+ <parameter name="GUI_ECC_TRIPLE" value="false" />
+ <parameter name="GUI_FILE_REFERENCE" value="0" />
+ <parameter name="GUI_INIT_FILE_LAYOUT" value="PORT_B" />
+ <parameter name="GUI_INIT_SIM_TO_X" value="false" />
+ <parameter name="GUI_LC_IMPLEMENTION_OPTIONS" value="0" />
+ <parameter name="GUI_MAX_DEPTH" value="Auto" />
+ <parameter name="GUI_MEMSIZE_BITS" value="256" />
+ <parameter name="GUI_MEMSIZE_WORDS" value="256" />
+ <parameter name="GUI_MEM_IN_BITS" value="0" />
+ <parameter name="GUI_MIF_FILENAME" value="./ram_1024.hex" />
+ <parameter name="GUI_MODE" value="1" />
+ <parameter name="GUI_NBE_A" value="true" />
+ <parameter name="GUI_NBE_B" value="true" />
+ <parameter name="GUI_QA_WIDTH" value="32" />
+ <parameter name="GUI_QB_WIDTH" value="8" />
+ <parameter name="GUI_Q_PORT_MODE" value="2" />
+ <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
+ <parameter name="GUI_RDEN_DOUBLE" value="true" />
+ <parameter name="GUI_RDEN_SINGLE" value="true" />
+ <parameter name="GUI_RDW_A_MODE" value="New Data" />
+ <parameter name="GUI_RDW_B_MODE" value="New Data" />
+ <parameter name="GUI_READ_INPUT_RDADDRESS" value="true" />
+ <parameter name="GUI_READ_OUTPUT_QA" value="true" />
+ <parameter name="GUI_READ_OUTPUT_QB" value="true" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QB" value="false" />
+ <parameter name="GUI_TBENCH" value="false" />
+ <parameter name="GUI_VAR_WIDTH" value="true" />
+ <parameter name="GUI_WIDTH_ECCENCPARITY" value="8" />
+ <parameter name="GUI_WRITE_INPUT_PORTS" value="true" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..be1ddf85cda316dfac5056ad845597a954dea5e8
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
@@ -0,0 +1,142 @@
+-- (C) 2001-2014 Altera Corporation. All rights reserved.
+-- Your use of Altera Corporation's design tools, logic functions and other
+-- software and tools, and its AMPP partner logic functions, and any output
+-- files any of the foregoing (including device programming or simulation
+-- files), and any associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License Subscription
+-- Agreement, Altera MegaCore Function License Agreement, or other applicable
+-- license agreement, including, without limitation, that your use is for the
+-- sole purpose of programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the applicable
+-- agreement for further details.
+
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE technology_lib.technology_pkg.all;
+
+LIBRARY altera_lnsim;
+USE altera_lnsim.altera_lnsim_components.all;
+
+ENTITY ip_arria10_e1sg_ram_crwk_crw IS
+ GENERIC (
+ g_adr_a_w : NATURAL := 5;
+ g_dat_a_w : NATURAL := 32;
+ g_adr_b_w : NATURAL := 4;
+ g_dat_b_w : NATURAL := 64;
+ g_nof_words_a : NATURAL := 2**5;
+ g_nof_words_b : NATURAL := 2**4;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT
+ (
+ address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
+ address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
+ clk_a : IN STD_LOGIC := '1';
+ clk_b : IN STD_LOGIC ;
+ data_a : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+ data_b : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
+ wren_a : IN STD_LOGIC := '0';
+ wren_b : IN STD_LOGIC := '0';
+ q_a : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
+ q_b : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
+ );
+END ip_arria10_e1sg_ram_crwk_crw;
+
+
+ARCHITECTURE SYN OF ip_arria10_e1sg_ram_crwk_crw IS
+
+ CONSTANT c_outdata_reg_a : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK0");
+ CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
+
+ COMPONENT altera_syncram
+ GENERIC (
+ address_reg_b : string;
+ clock_enable_input_a : string;
+ clock_enable_input_b : string;
+ clock_enable_output_a : string;
+ clock_enable_output_b : string;
+ indata_reg_b : string;
+ init_file : string;
+ init_file_layout : string;
+ intended_device_family : string;
+ lpm_type : string;
+ numwords_a : integer;
+ numwords_b : integer;
+ operation_mode : string;
+ outdata_aclr_a : string;
+ outdata_aclr_b : string;
+ outdata_reg_a : string;
+ outdata_reg_b : string;
+ power_up_uninitialized : string;
+ read_during_write_mode_port_a : string;
+ read_during_write_mode_port_b : string;
+ widthad_a : integer;
+ widthad_b : integer;
+ width_a : integer;
+ width_b : integer;
+ width_byteena_a : integer;
+ width_byteena_b : integer
+ );
+ PORT (
+ address_a : in std_logic_vector(g_adr_a_w-1 downto 0);
+ address_b : in std_logic_vector(g_adr_b_w-1 downto 0);
+ clock0 : in std_logic;
+ clock1 : in std_logic;
+ data_a : in std_logic_vector(g_dat_a_w-1 downto 0);
+ data_b : in std_logic_vector(g_dat_b_w-1 downto 0);
+ wren_a : in std_logic;
+ wren_b : in std_logic;
+ q_a : out std_logic_vector(g_dat_a_w - 1 downto 0);
+ q_b : out std_logic_vector(g_dat_b_w - 1 downto 0)
+ );
+ END COMPONENT;
+
+BEGIN
+
+ -- Copied from generated/ip_arria10_e1sg_ram_crwk_crw/ram_2port_140/sim/ip_arria10_e1sg_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
+ u_altera_syncram : altera_syncram
+ GENERIC MAP (
+ address_reg_b => "CLOCK1",
+ clock_enable_input_a => "BYPASS",
+ clock_enable_input_b => "BYPASS",
+ clock_enable_output_a => "BYPASS",
+ clock_enable_output_b => "BYPASS",
+ indata_reg_b => "CLOCK1",
+ init_file => g_init_file,
+ init_file_layout => "PORT_B",
+ intended_device_family => "Arria 10",
+ lpm_type => "altera_syncram",
+ numwords_a => g_nof_words_a,
+ numwords_b => g_nof_words_b,
+ operation_mode => "BIDIR_DUAL_PORT",
+ outdata_aclr_a => "NONE",
+ outdata_aclr_b => "NONE",
+ outdata_reg_a => c_outdata_reg_a,
+ outdata_reg_b => c_outdata_reg_b,
+ power_up_uninitialized => "FALSE",
+ read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+ read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+ widthad_a => g_adr_a_w,
+ widthad_b => g_adr_b_w,
+ width_a => g_dat_a_w,
+ width_b => g_dat_b_w,
+ width_byteena_a => 1,
+ width_byteena_b => 1
+ )
+ PORT MAP (
+ address_a => address_a,
+ address_b => address_b,
+ clock0 => clk_a,
+ clock1 => clk_b,
+ data_a => data_a,
+ data_b => data_b,
+ wren_a => wren_a,
+ wren_b => wren_b,
+ q_a => q_a,
+ q_b => q_b
+ );
+
+END SYN;
+
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.qsys b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..e477cfa2ae1e853e97a59bb0086d5c038e49f6e8
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.qsys
@@ -0,0 +1,130 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e3sge3_ram_r_w">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element ram_2port_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115U4F45E3SGE3" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="3" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="ram_input"
+ internal="ram_2port_0.ram_input"
+ type="conduit"
+ dir="end">
+ <port name="clock" internal="clock" />
+ <port name="data" internal="data" />
+ <port name="rdaddress" internal="rdaddress" />
+ <port name="wraddress" internal="wraddress" />
+ <port name="wren" internal="wren" />
+ </interface>
+ <interface
+ name="ram_output"
+ internal="ram_2port_0.ram_output"
+ type="conduit"
+ dir="end">
+ <port name="q" internal="q" />
+ </interface>
+ <module
+ name="ram_2port_0"
+ kind="ram_2port"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="GUI_ACLR_READ_INPUT_RDADDRESS" value="false" />
+ <parameter name="GUI_ACLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_ACLR_READ_OUTPUT_QB" value="false" />
+ <parameter name="GUI_BLANK_MEMORY" value="1" />
+ <parameter name="GUI_BYTE_ENABLE_A" value="false" />
+ <parameter name="GUI_BYTE_ENABLE_B" value="false" />
+ <parameter name="GUI_BYTE_ENABLE_WIDTH" value="8" />
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_A" value="false" />
+ <parameter name="GUI_CLKEN_ADDRESS_STALL_B" value="false" />
+ <parameter name="GUI_CLKEN_INPUT_REG_A" value="false" />
+ <parameter name="GUI_CLKEN_INPUT_REG_B" value="false" />
+ <parameter name="GUI_CLKEN_OUTPUT_REG_A" value="false" />
+ <parameter name="GUI_CLKEN_OUTPUT_REG_B" value="false" />
+ <parameter name="GUI_CLKEN_RDADDRESSSTALL" value="false" />
+ <parameter name="GUI_CLKEN_READ_INPUT_REG" value="false" />
+ <parameter name="GUI_CLKEN_READ_OUTPUT_REG" value="false" />
+ <parameter name="GUI_CLKEN_WRADDRESSSTALL" value="false" />
+ <parameter name="GUI_CLKEN_WRITE_INPUT_REG" value="false" />
+ <parameter name="GUI_CLOCK_TYPE" value="0" />
+ <parameter name="GUI_COHERENT_READ" value="false" />
+ <parameter name="GUI_CONSTRAINED_DONT_CARE" value="true" />
+ <parameter name="GUI_DATAA_WIDTH" value="8" />
+ <parameter name="GUI_DIFFERENT_CLKENS" value="false" />
+ <parameter name="GUI_ECCENCBYPASS" value="false" />
+ <parameter name="GUI_ECC_DOUBLE" value="false" />
+ <parameter name="GUI_ECC_PIPELINE" value="false" />
+ <parameter name="GUI_ECC_TRIPLE" value="false" />
+ <parameter name="GUI_FILE_REFERENCE" value="0" />
+ <parameter name="GUI_INIT_FILE_LAYOUT" value="PORT_B" />
+ <parameter name="GUI_INIT_SIM_TO_X" value="false" />
+ <parameter name="GUI_LC_IMPLEMENTION_OPTIONS" value="0" />
+ <parameter name="GUI_MAX_DEPTH" value="Auto" />
+ <parameter name="GUI_MEMSIZE_BITS" value="256" />
+ <parameter name="GUI_MEMSIZE_WORDS" value="32" />
+ <parameter name="GUI_MEM_IN_BITS" value="0" />
+ <parameter name="GUI_MIF_FILENAME" value="./ram_1024.hex" />
+ <parameter name="GUI_MODE" value="0" />
+ <parameter name="GUI_NBE_A" value="false" />
+ <parameter name="GUI_NBE_B" value="false" />
+ <parameter name="GUI_QA_WIDTH" value="8" />
+ <parameter name="GUI_QB_WIDTH" value="8" />
+ <parameter name="GUI_Q_PORT_MODE" value="2" />
+ <parameter name="GUI_RAM_BLOCK_TYPE" value="Auto" />
+ <parameter name="GUI_RDEN_DOUBLE" value="false" />
+ <parameter name="GUI_RDEN_SINGLE" value="false" />
+ <parameter name="GUI_RDW_A_MODE" value="New Data" />
+ <parameter name="GUI_RDW_B_MODE" value="New Data" />
+ <parameter name="GUI_READ_INPUT_RDADDRESS" value="true" />
+ <parameter name="GUI_READ_OUTPUT_QA" value="true" />
+ <parameter name="GUI_READ_OUTPUT_QB" value="true" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QA" value="false" />
+ <parameter name="GUI_SCLR_READ_OUTPUT_QB" value="false" />
+ <parameter name="GUI_TBENCH" value="false" />
+ <parameter name="GUI_VAR_WIDTH" value="false" />
+ <parameter name="GUI_WIDTH_ECCENCPARITY" value="8" />
+ <parameter name="GUI_WRITE_INPUT_PORTS" value="true" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3b9707e7e5c29ef5d09d4063871b49e9d3213633
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd
@@ -0,0 +1,155 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- RadioHDL wrapper
+
+LIBRARY ieee, technology_lib;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE technology_lib.technology_pkg.all;
+
+LIBRARY altera_lnsim;
+USE altera_lnsim.altera_lnsim_components.all;
+
+ENTITY ip_arria10_e1sg_ram_r_w IS
+ GENERIC (
+ g_inferred : BOOLEAN := FALSE;
+ g_adr_w : NATURAL := 5;
+ g_dat_w : NATURAL := 8;
+ g_nof_words : NATURAL := 2**5;
+ g_rd_latency : NATURAL := 1; -- choose 1 or 2
+ g_init_file : STRING := "UNUSED"
+ );
+ PORT (
+ clk : IN STD_LOGIC := '1';
+ data : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+ rdaddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
+ wraddress : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
+ wren : IN STD_LOGIC := '0';
+ q : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
+ );
+END ip_arria10_e1sg_ram_r_w;
+
+
+ARCHITECTURE SYN OF ip_arria10_e1sg_ram_r_w IS
+
+ CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");
+
+ COMPONENT altera_syncram
+ GENERIC (
+ address_aclr_b : string;
+ address_reg_b : string;
+ clock_enable_input_a : string;
+ clock_enable_input_b : string;
+ clock_enable_output_b : string;
+ init_file : string;
+ intended_device_family : string;
+ lpm_type : string;
+ numwords_a : integer;
+ numwords_b : integer;
+ operation_mode : string;
+ outdata_aclr_b : string;
+ outdata_reg_b : string;
+ power_up_uninitialized : string;
+ widthad_a : integer;
+ widthad_b : integer;
+ width_a : integer;
+ width_b : integer;
+ width_byteena_a : integer
+ );
+ PORT (
+ address_a : in std_logic_vector(g_adr_w-1 downto 0);
+ address_b : in std_logic_vector(g_adr_w-1 downto 0);
+ clock0 : in std_logic;
+ data_a : in std_logic_vector(g_dat_w-1 downto 0);
+ wren_a : in std_logic;
+ q_b : out std_logic_vector(g_dat_w-1 downto 0)
+ );
+ END COMPONENT;
+
+ SIGNAL rdaddr : natural range 0 to g_nof_words - 1;
+ SIGNAL wraddr : natural range 0 to g_nof_words - 1;
+
+ SIGNAL out_q : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+ SIGNAL reg_q : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
+
+BEGIN
+
+ ASSERT g_rd_latency=1 OR g_rd_latency=2 REPORT "ip_arria10_e1sg_ram_r_w : read latency must be 1 (default) or 2" SEVERITY FAILURE;
+
+ gen_ip : IF g_inferred=FALSE GENERATE
+ -- Copied from generated/ip_arria10_e1sg_ram_r_w/ram_2port_140/sim/ip_arria10_e1sg_ram_r_w_ram_2port_140_hukd7xi.vhd
+ u_altera_syncram : altera_syncram
+ GENERIC MAP (
+ address_aclr_b => "NONE",
+ address_reg_b => "CLOCK0",
+ clock_enable_input_a => "BYPASS",
+ clock_enable_input_b => "BYPASS",
+ clock_enable_output_b => "BYPASS",
+ init_file => g_init_file,
+ intended_device_family => "Arria 10",
+ lpm_type => "altera_syncram",
+ numwords_a => g_nof_words,
+ numwords_b => g_nof_words,
+ operation_mode => "DUAL_PORT",
+ outdata_aclr_b => "NONE",
+ outdata_reg_b => c_outdata_reg_b,
+ power_up_uninitialized => "FALSE",
+ widthad_a => g_adr_w,
+ widthad_b => g_adr_w,
+ width_a => g_dat_w,
+ width_b => g_dat_w,
+ width_byteena_a => 1
+ )
+ PORT MAP (
+ address_a => wraddress,
+ address_b => rdaddress,
+ clock0 => clk,
+ data_a => data,
+ wren_a => wren,
+ q_b => q
+ );
+ END GENERATE;
+
+ gen_inferred : IF g_inferred=TRUE GENERATE
+ rdaddr <= TO_INTEGER(UNSIGNED(rdaddress));
+ wraddr <= TO_INTEGER(UNSIGNED(wraddress));
+
+ u_mem : entity work.ip_arria10_e1sg_simple_dual_port_ram_single_clock
+ generic map (
+ DATA_WIDTH => g_dat_w,
+ ADDR_WIDTH => g_adr_w
+ )
+ port map (
+ clk => clk,
+ raddr => rdaddr,
+ waddr => wraddr,
+ data => data,
+ we => wren,
+ q => out_q
+ );
+
+ reg_q <= out_q WHEN rising_edge(clk);
+
+ q <= out_q WHEN g_rd_latency=1 ELSE reg_q;
+ END GENERATE;
+
+END SYN;
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_dual_clock.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_dual_clock.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7574066a9943245fb10bcf64c63ee04cfa6271ac
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_dual_clock.vhd
@@ -0,0 +1,80 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- The inferred Altera code was obtained using template insert with Quartus 14.0a10.
+
+-- Quartus II VHDL Template
+-- Simple Dual-Port RAM with different read/write addresses and
+-- different read/write clock
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_arria10_e1sg_simple_dual_port_ram_dual_clock is
+
+ generic
+ (
+ DATA_WIDTH : natural := 8;
+ ADDR_WIDTH : natural := 6
+ );
+
+ port
+ (
+ rclk : in std_logic;
+ wclk : in std_logic;
+ raddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+ waddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+ data : in std_logic_vector((DATA_WIDTH-1) downto 0);
+ we : in std_logic := '1';
+ q : out std_logic_vector((DATA_WIDTH -1) downto 0)
+ );
+
+end ip_arria10_e1sg_simple_dual_port_ram_dual_clock;
+
+architecture rtl of ip_arria10_e1sg_simple_dual_port_ram_dual_clock is
+
+ -- Build a 2-D array type for the RAM
+ subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
+ type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
+
+ -- Declare the RAM signal.
+ signal ram : memory_t;
+
+begin
+
+ process(wclk)
+ begin
+ if(rising_edge(wclk)) then
+ if(we = '1') then
+ ram(waddr) <= data;
+ end if;
+ end if;
+ end process;
+
+ process(rclk)
+ begin
+ if(rising_edge(rclk)) then
+ q <= ram(raddr);
+ end if;
+ end process;
+
+end rtl;
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_single_clock.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_single_clock.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5cb7d9caeaeb74a92338fb79d0914ab1ec5d4196
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_single_clock.vhd
@@ -0,0 +1,76 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- The inferred Altera code was obtained using template insert with Quartus 14.0a10.
+-- Quartus II VHDL Template
+-- Simple Dual-Port RAM with different read/write addresses but
+-- single read/write clock
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_arria10_e1sg_simple_dual_port_ram_single_clock is
+
+ generic
+ (
+ DATA_WIDTH : natural := 8;
+ ADDR_WIDTH : natural := 6
+ );
+
+ port
+ (
+ clk : in std_logic;
+ raddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+ waddr : in natural range 0 to 2**ADDR_WIDTH - 1;
+ data : in std_logic_vector((DATA_WIDTH-1) downto 0);
+ we : in std_logic := '1';
+ q : out std_logic_vector((DATA_WIDTH -1) downto 0)
+ );
+
+end ip_arria10_e1sg_simple_dual_port_ram_single_clock;
+
+architecture rtl of ip_arria10_e1sg_simple_dual_port_ram_single_clock is
+
+ -- Build a 2-D array type for the RAM
+ subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
+ type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
+
+ -- Declare the RAM signal.
+ signal ram : memory_t;
+
+begin
+
+ process(clk)
+ begin
+ if(rising_edge(clk)) then
+ if(we = '1') then
+ ram(waddr) <= data;
+ end if;
+
+ -- On a read during a write to the same address, the read will
+ -- return the OLD data at the address
+ q <= ram(raddr);
+ end if;
+ end process;
+
+end rtl;
+
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_true_dual_port_ram_dual_clock.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_true_dual_port_ram_dual_clock.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b45b979935d7efb8594f53928c42a7a37f1bfaab
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_true_dual_port_ram_dual_clock.vhd
@@ -0,0 +1,92 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- The inferred Altera code was obtained using template insert with Quartus 14.0a10.
+
+-- Quartus II VHDL Template
+-- True Dual-Port RAM with dual clock
+--
+-- Read-during-write on port A or B returns newly written data
+--
+-- Read-during-write on port A and B returns unknown data.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ip_arria10_e1sg_true_dual_port_ram_dual_clock is
+
+ generic
+ (
+ DATA_WIDTH : natural := 8;
+ ADDR_WIDTH : natural := 6
+ );
+
+ port
+ (
+ clk_a : in std_logic;
+ clk_b : in std_logic;
+ addr_a : in natural range 0 to 2**ADDR_WIDTH - 1;
+ addr_b : in natural range 0 to 2**ADDR_WIDTH - 1;
+ data_a : in std_logic_vector((DATA_WIDTH-1) downto 0);
+ data_b : in std_logic_vector((DATA_WIDTH-1) downto 0);
+ we_a : in std_logic := '1';
+ we_b : in std_logic := '1';
+ q_a : out std_logic_vector((DATA_WIDTH -1) downto 0);
+ q_b : out std_logic_vector((DATA_WIDTH -1) downto 0)
+ );
+
+end ip_arria10_e1sg_true_dual_port_ram_dual_clock;
+
+architecture rtl of ip_arria10_e1sg_true_dual_port_ram_dual_clock is
+
+ -- Build a 2-D array type for the RAM
+ subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
+ type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
+
+ -- Declare the RAM
+ shared variable ram : memory_t;
+
+begin
+
+ -- Port A
+ process(clk_a)
+ begin
+ if(rising_edge(clk_a)) then
+ if(we_a = '1') then
+ ram(addr_a) := data_a;
+ end if;
+ q_a <= ram(addr_a);
+ end if;
+ end process;
+
+ -- Port B
+ process(clk_b)
+ begin
+ if(rising_edge(clk_b)) then
+ if(we_b = '1') then
+ ram(addr_b) := data_b;
+ end if;
+ q_b <= ram(addr_b);
+ end if;
+ end process;
+
+end rtl;
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/README.patch b/libraries/technology/ip_arria10_e1sg/temp_sense/README.patch
new file mode 100644
index 0000000000000000000000000000000000000000..5d049715990215f956082a0c913d1a6816a1758f
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/README.patch
@@ -0,0 +1,4 @@
+The patch is generated with:
+
+diff -cB ip_arria10_e3sge3_temp_sense/altera_temp_sense_151/synth/altera_temp_sense.sdc generated/altera_temp_sense_151/synth/altera_temp_sense.sdc >altera_temp_sense.sdc.patch
+
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/altera_temp_sense.sdc.patch b/libraries/technology/ip_arria10_e1sg/temp_sense/altera_temp_sense.sdc.patch
new file mode 100644
index 0000000000000000000000000000000000000000..443cbc214f44448ef772f2e3fbc18771491088f4
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/altera_temp_sense.sdc.patch
@@ -0,0 +1,19 @@
+*** ip_arria10_e3sge3_temp_sense/altera_temp_sense_151/synth/altera_temp_sense.sdc 2016-01-29 09:56:26.683213797 +0100
+--- generated/altera_temp_sense_151/synth/altera_temp_sense.sdc 2016-01-29 09:58:08.553558667 +0100
+***************
+*** 11,15 ****
+ # agreement for further details.
+
+
+! # Create clock for temperature sensor internal clock
+! create_clock -period 1000 -name altera_ts_clk [get_nodes {*altera_temp_sense:temp_sense_0|sd1~sn_adc_ts_clk}]
+\ No newline at end of file
+--- 11,18 ----
+ # agreement for further details.
+
+
+! # Create clock for temperature sensor internal clock
+! create_clock -period 1000 -name altera_ts_clk [get_nodes {*altera_temp_sense:temp_sense_0|sd1~sn_adc_ts_clk}]
+! # extra virtual clock:
+! create_clock -period 1000 -name altera_ts_clk.reg [get_nodes {*altera_temp_sense:temp_sense_0|sd1~sn_adc_ts_clk.reg}]
+!
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..ab8fbc6a740fbfb1b4f48a70f96ec45a4b5d0006
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_temp_sense.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..26d451acdfc1cc2b4ef2c68165db2f5c6b6457d3
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
@@ -0,0 +1,18 @@
+hdl_lib_name = ip_arria10_e1sg_temp_sense
+hdl_library_clause_name = ip_arria10_e1sg_temp_sense_altera_temp_sense_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+#modelsim_compile_ip_files =
+# $RADIOHDL/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files = generated/ip_arria10_e1sg_temp_sense.qip
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/ip_arria10_e1sg_temp_sense.qsys b/libraries/technology/ip_arria10_e1sg/temp_sense/ip_arria10_e1sg_temp_sense.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..33fbc1f1ea6b2abbea1f33c195e678fdc0948e46
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/ip_arria10_e1sg_temp_sense.qsys
@@ -0,0 +1,89 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_temp_sense">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element temp_sense_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="clk" internal="temp_sense_0.clk" />
+ <interface
+ name="corectl"
+ internal="temp_sense_0.corectl"
+ type="conduit"
+ dir="end">
+ <port name="corectl" internal="corectl" />
+ </interface>
+ <interface name="eoc" internal="temp_sense_0.eoc" type="conduit" dir="end">
+ <port name="eoc" internal="eoc" />
+ </interface>
+ <interface name="reset" internal="temp_sense_0.reset" type="conduit" dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="tempout"
+ internal="temp_sense_0.tempout"
+ type="conduit"
+ dir="end">
+ <port name="tempout" internal="tempout" />
+ </interface>
+ <interface name="tsdcaldone" internal="temp_sense_0.tsdcaldone" />
+ <interface name="tsdcalo" internal="temp_sense_0.tsdcalo" />
+ <module
+ name="temp_sense_0"
+ kind="altera_temp_sense"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CBX_AUTO_BLACKBOX" value="ALL" />
+ <parameter name="CE_CHECK" value="false" />
+ <parameter name="CLK_FREQUENCY" value="1.0" />
+ <parameter name="CLOCK_DIVIDER_VALUE" value="40" />
+ <parameter name="CLR_CHECK" value="false" />
+ <parameter name="DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="NUMBER_OF_SAMPLES" value="128" />
+ <parameter name="POI_CAL_TEMPERATURE" value="85" />
+ <parameter name="SIM_TSDCALO" value="0" />
+ <parameter name="USER_OFFSET_ENABLE" value="off" />
+ <parameter name="USE_WYS" value="on" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/run_patch.sh b/libraries/technology/ip_arria10_e1sg/temp_sense/run_patch.sh
new file mode 100755
index 0000000000000000000000000000000000000000..c03ae5de5d6f063efe85dc30b77bf10aa55c4dc2
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/run_patch.sh
@@ -0,0 +1,10 @@
+#!/bin/bash
+
+patchfile='altera_temp_sense.sdc.patch'
+
+echo -e "Applying patch: $patchfile\n"
+
+cd generated/altera_temp_sense_151/synth/
+patch <../../../${patchfile}
+
+echo "done."
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..12de447a123ef957c2f267135432bb1c783a31c9
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_transceiver_pll_10g.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..f89384011679be01f6822d6fc3e350023dfe6c81
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_transceiver_pll_10g
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_transceiver_pll_10g.qip
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..e2553800078f8a5fb8f0d417f8b7f602a9bee352
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qsys
@@ -0,0 +1,223 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_transceiver_pll_10g">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element xcvr_atx_pll_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>reconfig_avmm0</key>
+ <value>
+ <connectionPointName>reconfig_avmm0</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='reconfig_avmm0' start='0x0' end='0x1000' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>12</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="mcgb_rst"
+ internal="xcvr_atx_pll_a10_0.mcgb_rst"
+ type="conduit"
+ dir="end">
+ <port name="mcgb_rst" internal="mcgb_rst" />
+ </interface>
+ <interface
+ name="mcgb_serial_clk"
+ internal="xcvr_atx_pll_a10_0.mcgb_serial_clk"
+ type="hssi_serial_clock"
+ dir="start">
+ <port name="mcgb_serial_clk" internal="mcgb_serial_clk" />
+ </interface>
+ <interface
+ name="pll_cal_busy"
+ internal="xcvr_atx_pll_a10_0.pll_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="pll_cal_busy" internal="pll_cal_busy" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="xcvr_atx_pll_a10_0.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="xcvr_atx_pll_a10_0.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_refclk0"
+ internal="xcvr_atx_pll_a10_0.pll_refclk0"
+ type="clock"
+ dir="end">
+ <port name="pll_refclk0" internal="pll_refclk0" />
+ </interface>
+ <interface
+ name="reconfig_avmm0"
+ internal="xcvr_atx_pll_a10_0.reconfig_avmm0"
+ type="avalon"
+ dir="end">
+ <port name="reconfig_address0" internal="reconfig_address0" />
+ <port name="reconfig_read0" internal="reconfig_read0" />
+ <port name="reconfig_readdata0" internal="reconfig_readdata0" />
+ <port name="reconfig_waitrequest0" internal="reconfig_waitrequest0" />
+ <port name="reconfig_write0" internal="reconfig_write0" />
+ <port name="reconfig_writedata0" internal="reconfig_writedata0" />
+ </interface>
+ <interface
+ name="reconfig_clk0"
+ internal="xcvr_atx_pll_a10_0.reconfig_clk0"
+ type="clock"
+ dir="end">
+ <port name="reconfig_clk0" internal="reconfig_clk0" />
+ </interface>
+ <interface
+ name="reconfig_reset0"
+ internal="xcvr_atx_pll_a10_0.reconfig_reset0"
+ type="reset"
+ dir="end">
+ <port name="reconfig_reset0" internal="reconfig_reset0" />
+ </interface>
+ <interface
+ name="tx_serial_clk"
+ internal="xcvr_atx_pll_a10_0.tx_serial_clk"
+ type="hssi_serial_clock"
+ dir="start">
+ <port name="tx_serial_clk" internal="tx_serial_clk" />
+ </interface>
+ <module
+ name="xcvr_atx_pll_a10_0"
+ kind="altera_xcvr_atx_pll_a10"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="base_device" value="NIGHTFURY5" />
+ <parameter name="bw_sel" value="low" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="enable_16G_path" value="0" />
+ <parameter name="enable_8G_path" value="1" />
+ <parameter name="enable_analog_resets" value="0" />
+ <parameter name="enable_bonding_clks" value="0" />
+ <parameter name="enable_cascade_out" value="0" />
+ <parameter name="enable_debug_ports_parameters" value="0" />
+ <parameter name="enable_ext_lockdetect_ports" value="0" />
+ <parameter name="enable_fb_comp_bonding" value="0" />
+ <parameter name="enable_hfreq_clk" value="1" />
+ <parameter name="enable_hip_cal_done_port" value="0" />
+ <parameter name="enable_manual_configuration" value="1" />
+ <parameter name="enable_mcgb" value="1" />
+ <parameter name="enable_mcgb_pcie_clksw" value="0" />
+ <parameter name="enable_pcie_clk" value="0" />
+ <parameter name="enable_pld_atx_cal_busy_port" value="1" />
+ <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
+ <parameter name="enable_pll_reconfig" value="1" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="mcgb_aux_clkin_cnt" value="0" />
+ <parameter name="mcgb_div" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="pma_width" value="64" />
+ <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
+ <parameter name="prot_mode" value="Basic" />
+ <parameter name="rcfg_debug" value="0" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="1" />
+ <parameter name="rcfg_jtag_enable" value="1" />
+ <parameter name="rcfg_mif_file_enable" value="1" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_data0" value="" />
+ <parameter name="rcfg_profile_data1" value="" />
+ <parameter name="rcfg_profile_data2" value="" />
+ <parameter name="rcfg_profile_data3" value="" />
+ <parameter name="rcfg_profile_data4" value="" />
+ <parameter name="rcfg_profile_data5" value="" />
+ <parameter name="rcfg_profile_data6" value="" />
+ <parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_sv_file_enable" value="1" />
+ <parameter name="rcfg_txt_file_enable" value="0" />
+ <parameter name="refclk_cnt" value="1" />
+ <parameter name="refclk_index" value="0" />
+ <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
+ <parameter name="set_auto_reference_clock_frequency" value="644.53125" />
+ <parameter name="set_capability_reg_enable" value="1" />
+ <parameter name="set_csr_soft_logic_enable" value="1" />
+ <parameter name="set_fref_clock_frequency" value="100.0" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_k_counter" value="1" />
+ <parameter name="set_l_cascade_counter" value="4" />
+ <parameter name="set_l_cascade_predivider" value="1" />
+ <parameter name="set_l_counter" value="2" />
+ <parameter name="set_m_counter" value="1" />
+ <parameter name="set_manual_reference_clock_frequency" value="100.0" />
+ <parameter name="set_output_clock_frequency" value="5156.25" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
+ <parameter name="set_ref_clk_div" value="1" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="silicon_rev" value="false" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="test_mode" value="0" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..17e84e3a490d62221312a8fcd6301aa6a4c23561
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_transceiver_reset_controller_1.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..130feaaeb93c92d94b9c808796d2f5eaa81fb19a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_1
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_1_altera_xcvr_reset_control_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_transceiver_reset_controller_1.qip
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..50d06a0630205badae265bff1e0b2b6c38ecf4ef
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qsys
@@ -0,0 +1,175 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_transceiver_reset_controller_1">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element xcvr_reset_control_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="clock"
+ internal="xcvr_reset_control_0.clock"
+ type="clock"
+ dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="xcvr_reset_control_0.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="xcvr_reset_control_0.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_select"
+ internal="xcvr_reset_control_0.pll_select"
+ type="conduit"
+ dir="end">
+ <port name="pll_select" internal="pll_select" />
+ </interface>
+ <interface
+ name="reset"
+ internal="xcvr_reset_control_0.reset"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="xcvr_reset_control_0.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="xcvr_reset_control_0.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="xcvr_reset_control_0.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="xcvr_reset_control_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_ready"
+ internal="xcvr_reset_control_0.rx_ready"
+ type="conduit"
+ dir="end">
+ <port name="rx_ready" internal="rx_ready" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="xcvr_reset_control_0.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="xcvr_reset_control_0.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="xcvr_reset_control_0.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_ready"
+ internal="xcvr_reset_control_0.tx_ready"
+ type="conduit"
+ dir="end">
+ <port name="tx_ready" internal="tx_ready" />
+ </interface>
+ <module
+ name="xcvr_reset_control_0"
+ kind="altera_xcvr_reset_control"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CHANNELS" value="1" />
+ <parameter name="PLLS" value="1" />
+ <parameter name="REDUCED_SIM_TIME" value="1" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="1" />
+ <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="156" />
+ <parameter name="TX_ENABLE" value="1" />
+ <parameter name="TX_PER_CHANNEL" value="0" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
+ <parameter name="T_PLL_LOCK_HYST" value="60" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="T_RX_ANALOGRESET" value="70000" />
+ <parameter name="T_RX_DIGITALRESET" value="4000" />
+ <parameter name="T_TX_ANALOGRESET" value="70000" />
+ <parameter name="T_TX_DIGITALRESET" value="70000" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="0" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..db50fda3d1c23b1fba99b29b706585e04f519493
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_transceiver_reset_controller_12.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..fa572fc2d5df2f8bcf9b50f552206f617a899343
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_12
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_12_altera_xcvr_reset_control_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_transceiver_reset_controller_12.qip
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..7d673d7121e7467544e5cc695b4f0b47415e5b2e
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qsys
@@ -0,0 +1,175 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_transceiver_reset_controller_12">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element transceiver_reset_controller_inst
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="clock"
+ internal="transceiver_reset_controller_inst.clock"
+ type="clock"
+ dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="transceiver_reset_controller_inst.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="transceiver_reset_controller_inst.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_select"
+ internal="transceiver_reset_controller_inst.pll_select"
+ type="conduit"
+ dir="end">
+ <port name="pll_select" internal="pll_select" />
+ </interface>
+ <interface
+ name="reset"
+ internal="transceiver_reset_controller_inst.reset"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="transceiver_reset_controller_inst.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="transceiver_reset_controller_inst.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="transceiver_reset_controller_inst.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_ready"
+ internal="transceiver_reset_controller_inst.rx_ready"
+ type="conduit"
+ dir="end">
+ <port name="rx_ready" internal="rx_ready" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="transceiver_reset_controller_inst.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="transceiver_reset_controller_inst.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="transceiver_reset_controller_inst.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_ready"
+ internal="transceiver_reset_controller_inst.tx_ready"
+ type="conduit"
+ dir="end">
+ <port name="tx_ready" internal="tx_ready" />
+ </interface>
+ <module
+ name="transceiver_reset_controller_inst"
+ kind="altera_xcvr_reset_control"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CHANNELS" value="12" />
+ <parameter name="PLLS" value="1" />
+ <parameter name="REDUCED_SIM_TIME" value="1" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="1" />
+ <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="156" />
+ <parameter name="TX_ENABLE" value="1" />
+ <parameter name="TX_PER_CHANNEL" value="0" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
+ <parameter name="T_PLL_LOCK_HYST" value="60" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="T_RX_ANALOGRESET" value="70000" />
+ <parameter name="T_RX_DIGITALRESET" value="4000" />
+ <parameter name="T_TX_ANALOGRESET" value="70000" />
+ <parameter name="T_TX_DIGITALRESET" value="70000" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="0" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..761d94c86955a2bfa768b6d837eb61929e4c33eb
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_transceiver_reset_controller_24.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..47c738e840d9f34735654480297ad0f19cdb0f2c
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_24
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_24_altera_xcvr_reset_control_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_transceiver_reset_controller_24.qip
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..37333b36887e110ddf3d87ec63036e8618a5a569
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qsys
@@ -0,0 +1,175 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_transceiver_reset_controller_24">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element transceiver_reset_controller_inst
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="clock"
+ internal="transceiver_reset_controller_inst.clock"
+ type="clock"
+ dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="transceiver_reset_controller_inst.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="transceiver_reset_controller_inst.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_select"
+ internal="transceiver_reset_controller_inst.pll_select"
+ type="conduit"
+ dir="end">
+ <port name="pll_select" internal="pll_select" />
+ </interface>
+ <interface
+ name="reset"
+ internal="transceiver_reset_controller_inst.reset"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="transceiver_reset_controller_inst.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="transceiver_reset_controller_inst.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="transceiver_reset_controller_inst.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_ready"
+ internal="transceiver_reset_controller_inst.rx_ready"
+ type="conduit"
+ dir="end">
+ <port name="rx_ready" internal="rx_ready" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="transceiver_reset_controller_inst.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="transceiver_reset_controller_inst.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="transceiver_reset_controller_inst.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_ready"
+ internal="transceiver_reset_controller_inst.tx_ready"
+ type="conduit"
+ dir="end">
+ <port name="tx_ready" internal="tx_ready" />
+ </interface>
+ <module
+ name="transceiver_reset_controller_inst"
+ kind="altera_xcvr_reset_control"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CHANNELS" value="24" />
+ <parameter name="PLLS" value="1" />
+ <parameter name="REDUCED_SIM_TIME" value="1" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="1" />
+ <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="156" />
+ <parameter name="TX_ENABLE" value="1" />
+ <parameter name="TX_PER_CHANNEL" value="0" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
+ <parameter name="T_PLL_LOCK_HYST" value="60" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="T_RX_ANALOGRESET" value="70000" />
+ <parameter name="T_RX_DIGITALRESET" value="4000" />
+ <parameter name="T_TX_ANALOGRESET" value="70000" />
+ <parameter name="T_TX_DIGITALRESET" value="70000" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="0" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..ad1d84d8d18b04d91936446ff8dfbdf90c3448eb
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_transceiver_reset_controller_4.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..e1a30e6660020843261a2525ab540cd34a6060f0
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_4
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_4_altera_xcvr_reset_control_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_transceiver_reset_controller_4.qip
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..d61ebe600396461303507a2a74bd6225b56fc020
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qsys
@@ -0,0 +1,175 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_transceiver_reset_controller_4">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element transceiver_reset_controller_inst
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="clock"
+ internal="transceiver_reset_controller_inst.clock"
+ type="clock"
+ dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="transceiver_reset_controller_inst.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="transceiver_reset_controller_inst.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_select"
+ internal="transceiver_reset_controller_inst.pll_select"
+ type="conduit"
+ dir="end">
+ <port name="pll_select" internal="pll_select" />
+ </interface>
+ <interface
+ name="reset"
+ internal="transceiver_reset_controller_inst.reset"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="transceiver_reset_controller_inst.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="transceiver_reset_controller_inst.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="transceiver_reset_controller_inst.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_ready"
+ internal="transceiver_reset_controller_inst.rx_ready"
+ type="conduit"
+ dir="end">
+ <port name="rx_ready" internal="rx_ready" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="transceiver_reset_controller_inst.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="transceiver_reset_controller_inst.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="transceiver_reset_controller_inst.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_ready"
+ internal="transceiver_reset_controller_inst.tx_ready"
+ type="conduit"
+ dir="end">
+ <port name="tx_ready" internal="tx_ready" />
+ </interface>
+ <module
+ name="transceiver_reset_controller_inst"
+ kind="altera_xcvr_reset_control"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CHANNELS" value="4" />
+ <parameter name="PLLS" value="1" />
+ <parameter name="REDUCED_SIM_TIME" value="1" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="1" />
+ <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="156" />
+ <parameter name="TX_ENABLE" value="1" />
+ <parameter name="TX_PER_CHANNEL" value="0" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
+ <parameter name="T_PLL_LOCK_HYST" value="60" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="T_RX_ANALOGRESET" value="70000" />
+ <parameter name="T_RX_DIGITALRESET" value="4000" />
+ <parameter name="T_TX_ANALOGRESET" value="70000" />
+ <parameter name="T_TX_DIGITALRESET" value="70000" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="0" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..81f461f352dfdcb41c9d6b086edea7f1b2c374b7
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_transceiver_reset_controller_48.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..ded13eeaff2b64887a39364b97e3c113c8736360
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_transceiver_reset_controller_48
+hdl_library_clause_name = ip_arria10_e1sg_transceiver_reset_controller_48_altera_xcvr_reset_control_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_transceiver_reset_controller_48.qip
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qsys b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..c30c9521e612e211d4d17e037bc69446c281feb8
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qsys
@@ -0,0 +1,175 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_transceiver_reset_controller_48">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element transceiver_reset_controller_inst
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="clock"
+ internal="transceiver_reset_controller_inst.clock"
+ type="clock"
+ dir="end">
+ <port name="clock" internal="clock" />
+ </interface>
+ <interface
+ name="pll_locked"
+ internal="transceiver_reset_controller_inst.pll_locked"
+ type="conduit"
+ dir="end">
+ <port name="pll_locked" internal="pll_locked" />
+ </interface>
+ <interface
+ name="pll_powerdown"
+ internal="transceiver_reset_controller_inst.pll_powerdown"
+ type="conduit"
+ dir="end">
+ <port name="pll_powerdown" internal="pll_powerdown" />
+ </interface>
+ <interface
+ name="pll_select"
+ internal="transceiver_reset_controller_inst.pll_select"
+ type="conduit"
+ dir="end">
+ <port name="pll_select" internal="pll_select" />
+ </interface>
+ <interface
+ name="reset"
+ internal="transceiver_reset_controller_inst.reset"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="transceiver_reset_controller_inst.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="transceiver_reset_controller_inst.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="transceiver_reset_controller_inst.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="transceiver_reset_controller_inst.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_ready"
+ internal="transceiver_reset_controller_inst.rx_ready"
+ type="conduit"
+ dir="end">
+ <port name="rx_ready" internal="rx_ready" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="transceiver_reset_controller_inst.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="transceiver_reset_controller_inst.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="transceiver_reset_controller_inst.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_ready"
+ internal="transceiver_reset_controller_inst.tx_ready"
+ type="conduit"
+ dir="end">
+ <port name="tx_ready" internal="tx_ready" />
+ </interface>
+ <module
+ name="transceiver_reset_controller_inst"
+ kind="altera_xcvr_reset_control"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="CHANNELS" value="48" />
+ <parameter name="PLLS" value="1" />
+ <parameter name="REDUCED_SIM_TIME" value="1" />
+ <parameter name="RX_ENABLE" value="1" />
+ <parameter name="RX_PER_CHANNEL" value="1" />
+ <parameter name="SYNCHRONIZE_PLL_RESET" value="0" />
+ <parameter name="SYNCHRONIZE_RESET" value="1" />
+ <parameter name="SYS_CLK_IN_MHZ" value="156" />
+ <parameter name="TX_ENABLE" value="1" />
+ <parameter name="TX_PER_CHANNEL" value="0" />
+ <parameter name="TX_PLL_ENABLE" value="1" />
+ <parameter name="T_PLL_LOCK_HYST" value="60" />
+ <parameter name="T_PLL_POWERDOWN" value="1000" />
+ <parameter name="T_RX_ANALOGRESET" value="70000" />
+ <parameter name="T_RX_DIGITALRESET" value="4000" />
+ <parameter name="T_TX_ANALOGRESET" value="70000" />
+ <parameter name="T_TX_DIGITALRESET" value="70000" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="gui_pll_cal_busy" value="0" />
+ <parameter name="gui_rx_auto_reset" value="0" />
+ <parameter name="gui_split_interfaces" value="0" />
+ <parameter name="gui_tx_auto_reset" value="0" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt
new file mode 100755
index 0000000000000000000000000000000000000000..846e784f55181cb84a27903a7e897ac3d01fa383
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt
@@ -0,0 +1,8 @@
+README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_gx
+
+The ip_arria10_tse_sgmii_gx IP was ported to Quartus 14.0a10 for Arria10 by creating it in Qsys using the same parameter settings as the ip_arria10_tse_sgmii_lvds, but with GX IO.
+
+The tb_ip_arria10_tse_sgmii_gx.vhd verifies the DUT and simulates OK.
+
+For more information see: $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..91152f6cd89e4dad4f848dd56816f60f2499bb8d
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generate_ip.sh
@@ -0,0 +1,54 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_tse_sgmii_gx.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
+
+# Also generate the testbench IP
+#qsys-generate ip_arria10_e1sg_tse_sgmii_gx.qsys \
+# --synthesis=VHDL \
+# --simulation=VHDL \
+# --testbench=STANDARD \
+# --testbench-simulation=VHDL \
+# --output-directory=generated \
+# --allow-mixed-language-simulation \
+# --allow-mixed-language-testbench-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..b1b572504b80e2690b82c6c3ce4534c00ed15faf
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
@@ -0,0 +1,20 @@
+hdl_lib_name = ip_arria10_e1sg_tse_sgmii_gx
+hdl_library_clause_name = ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_151
+hdl_lib_uses_synth = common
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+ tb_ip_arria10_e1sg_tse_sgmii_gx.vhd
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_tse_sgmii_gx.qip
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qsys b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..4f66e6da726faaa2c41d6372262b78df1bc8d6bb
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qsys
@@ -0,0 +1,329 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_tse_sgmii_gx">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element eth_tse_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>control_port</key>
+ <value>
+ <connectionPointName>control_port</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='control_port' start='0x0' end='0x400' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>10</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="control_port"
+ internal="eth_tse_0.control_port"
+ type="avalon"
+ dir="end">
+ <port name="reg_addr" internal="reg_addr" />
+ <port name="reg_busy" internal="reg_busy" />
+ <port name="reg_data_in" internal="reg_data_in" />
+ <port name="reg_data_out" internal="reg_data_out" />
+ <port name="reg_rd" internal="reg_rd" />
+ <port name="reg_wr" internal="reg_wr" />
+ </interface>
+ <interface
+ name="control_port_clock_connection"
+ internal="eth_tse_0.control_port_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="clk" internal="clk" />
+ </interface>
+ <interface name="mac_gmii_connection" internal="eth_tse_0.mac_gmii_connection" />
+ <interface name="mac_mii_connection" internal="eth_tse_0.mac_mii_connection" />
+ <interface
+ name="mac_misc_connection"
+ internal="eth_tse_0.mac_misc_connection"
+ type="conduit"
+ dir="end">
+ <port name="ff_rx_a_empty" internal="ff_rx_a_empty" />
+ <port name="ff_rx_a_full" internal="ff_rx_a_full" />
+ <port name="ff_rx_dsav" internal="ff_rx_dsav" />
+ <port name="ff_tx_a_empty" internal="ff_tx_a_empty" />
+ <port name="ff_tx_a_full" internal="ff_tx_a_full" />
+ <port name="ff_tx_crc_fwd" internal="ff_tx_crc_fwd" />
+ <port name="ff_tx_septy" internal="ff_tx_septy" />
+ <port name="rx_err_stat" internal="rx_err_stat" />
+ <port name="rx_frm_type" internal="rx_frm_type" />
+ <port name="tx_ff_uflow" internal="tx_ff_uflow" />
+ </interface>
+ <interface
+ name="mac_status_connection"
+ internal="eth_tse_0.mac_status_connection" />
+ <interface
+ name="pcs_mac_rx_clock_connection"
+ internal="eth_tse_0.pcs_mac_rx_clock_connection" />
+ <interface
+ name="pcs_mac_tx_clock_connection"
+ internal="eth_tse_0.pcs_mac_tx_clock_connection" />
+ <interface
+ name="pcs_ref_clk_clock_connection"
+ internal="eth_tse_0.pcs_ref_clk_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="ref_clk" internal="ref_clk" />
+ </interface>
+ <interface
+ name="receive"
+ internal="eth_tse_0.receive"
+ type="avalon_streaming"
+ dir="start">
+ <port name="ff_rx_data" internal="ff_rx_data" />
+ <port name="ff_rx_dval" internal="ff_rx_dval" />
+ <port name="ff_rx_eop" internal="ff_rx_eop" />
+ <port name="ff_rx_mod" internal="ff_rx_mod" />
+ <port name="ff_rx_rdy" internal="ff_rx_rdy" />
+ <port name="ff_rx_sop" internal="ff_rx_sop" />
+ <port name="rx_err" internal="rx_err" />
+ </interface>
+ <interface
+ name="receive_clock_connection"
+ internal="eth_tse_0.receive_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="ff_rx_clk" internal="ff_rx_clk" />
+ </interface>
+ <interface
+ name="reset_connection"
+ internal="eth_tse_0.reset_connection"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="rx_analogreset"
+ internal="eth_tse_0.rx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_analogreset" internal="rx_analogreset" />
+ </interface>
+ <interface
+ name="rx_cal_busy"
+ internal="eth_tse_0.rx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="rx_cal_busy" internal="rx_cal_busy" />
+ </interface>
+ <interface
+ name="rx_cdr_refclk"
+ internal="eth_tse_0.rx_cdr_refclk"
+ type="clock"
+ dir="end">
+ <port name="rx_cdr_refclk" internal="rx_cdr_refclk" />
+ </interface>
+ <interface
+ name="rx_digitalreset"
+ internal="eth_tse_0.rx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="rx_digitalreset" internal="rx_digitalreset" />
+ </interface>
+ <interface
+ name="rx_is_lockedtodata"
+ internal="eth_tse_0.rx_is_lockedtodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtodata" internal="rx_is_lockedtodata" />
+ </interface>
+ <interface
+ name="rx_is_lockedtoref"
+ internal="eth_tse_0.rx_is_lockedtoref"
+ type="conduit"
+ dir="end">
+ <port name="rx_is_lockedtoref" internal="rx_is_lockedtoref" />
+ </interface>
+ <interface
+ name="rx_set_locktodata"
+ internal="eth_tse_0.rx_set_locktodata"
+ type="conduit"
+ dir="end">
+ <port name="rx_set_locktodata" internal="rx_set_locktodata" />
+ </interface>
+ <interface
+ name="rx_set_locktoref"
+ internal="eth_tse_0.rx_set_locktoref"
+ type="conduit"
+ dir="end">
+ <port name="rx_set_locktoref" internal="rx_set_locktoref" />
+ </interface>
+ <interface
+ name="serdes_control_connection"
+ internal="eth_tse_0.serdes_control_connection"
+ type="conduit"
+ dir="end">
+ <port name="rx_recovclkout" internal="rx_recovclkout" />
+ </interface>
+ <interface
+ name="serial_connection"
+ internal="eth_tse_0.serial_connection"
+ type="conduit"
+ dir="end">
+ <port name="rxp" internal="rxp" />
+ <port name="txp" internal="txp" />
+ </interface>
+ <interface
+ name="status_led_connection"
+ internal="eth_tse_0.status_led_connection"
+ type="conduit"
+ dir="end">
+ <port name="led_an" internal="led_an" />
+ <port name="led_char_err" internal="led_char_err" />
+ <port name="led_col" internal="led_col" />
+ <port name="led_crs" internal="led_crs" />
+ <port name="led_disp_err" internal="led_disp_err" />
+ <port name="led_link" internal="led_link" />
+ <port name="led_panel_link" internal="led_panel_link" />
+ </interface>
+ <interface name="tbi_connection" internal="eth_tse_0.tbi_connection" />
+ <interface
+ name="transmit"
+ internal="eth_tse_0.transmit"
+ type="avalon_streaming"
+ dir="end">
+ <port name="ff_tx_data" internal="ff_tx_data" />
+ <port name="ff_tx_eop" internal="ff_tx_eop" />
+ <port name="ff_tx_err" internal="ff_tx_err" />
+ <port name="ff_tx_mod" internal="ff_tx_mod" />
+ <port name="ff_tx_rdy" internal="ff_tx_rdy" />
+ <port name="ff_tx_sop" internal="ff_tx_sop" />
+ <port name="ff_tx_wren" internal="ff_tx_wren" />
+ </interface>
+ <interface
+ name="transmit_clock_connection"
+ internal="eth_tse_0.transmit_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="ff_tx_clk" internal="ff_tx_clk" />
+ </interface>
+ <interface
+ name="tx_analogreset"
+ internal="eth_tse_0.tx_analogreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_analogreset" internal="tx_analogreset" />
+ </interface>
+ <interface
+ name="tx_cal_busy"
+ internal="eth_tse_0.tx_cal_busy"
+ type="conduit"
+ dir="end">
+ <port name="tx_cal_busy" internal="tx_cal_busy" />
+ </interface>
+ <interface
+ name="tx_digitalreset"
+ internal="eth_tse_0.tx_digitalreset"
+ type="conduit"
+ dir="end">
+ <port name="tx_digitalreset" internal="tx_digitalreset" />
+ </interface>
+ <interface
+ name="tx_serial_clk"
+ internal="eth_tse_0.tx_serial_clk"
+ type="hssi_serial_clock"
+ dir="end">
+ <port name="tx_serial_clk" internal="tx_serial_clk" />
+ </interface>
+ <module
+ name="eth_tse_0"
+ kind="altera_eth_tse"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="AUTO_DEVICE" value="10AX115S2F45E1SG" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
+ <parameter name="core_variation" value="MAC_PCS" />
+ <parameter name="deviceFamilyName" value="Arria 10" />
+ <parameter name="eg_addr" value="11" />
+ <parameter name="ena_hash" value="false" />
+ <parameter name="enable_alt_reconfig" value="false" />
+ <parameter name="enable_ecc" value="false" />
+ <parameter name="enable_ena" value="32" />
+ <parameter name="enable_gmii_loopback" value="false" />
+ <parameter name="enable_hd_logic" value="false" />
+ <parameter name="enable_mac_flow_ctrl" value="false" />
+ <parameter name="enable_mac_vlan" value="false" />
+ <parameter name="enable_magic_detect" value="false" />
+ <parameter name="enable_ptp_1step" value="false" />
+ <parameter name="enable_sgmii" value="false" />
+ <parameter name="enable_shift16" value="true" />
+ <parameter name="enable_sup_addr" value="false" />
+ <parameter name="enable_timestamping" value="false" />
+ <parameter name="enable_use_internal_fifo" value="true" />
+ <parameter name="export_pwrdn" value="false" />
+ <parameter name="ext_stat_cnt_ena" value="false" />
+ <parameter name="ifGMII" value="MII_GMII" />
+ <parameter name="ing_addr" value="11" />
+ <parameter name="max_channels" value="1" />
+ <parameter name="mdio_clk_div" value="40" />
+ <parameter name="nf_phyip_rcfg_enable" value="false" />
+ <parameter name="phy_identifier" value="0" />
+ <parameter name="phyip_en_synce_support" value="false" />
+ <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
+ <parameter name="phyip_pll_type" value="CMU" />
+ <parameter name="phyip_pma_bonding_mode" value="x1" />
+ <parameter name="starting_channel_number" value="0" />
+ <parameter name="stat_cnt_ena" value="false" />
+ <parameter name="transceiver_type" value="GXB" />
+ <parameter name="tstamp_fp_width" value="4" />
+ <parameter name="useMDIO" value="false" />
+ <parameter name="use_mac_clken" value="false" />
+ <parameter name="use_misc_ports" value="true" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/tb_ip_arria10_e1sg_tse_sgmii_gx.vhd b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/tb_ip_arria10_e1sg_tse_sgmii_gx.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..677d7991f95644b508162b5b4e57001509727801
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/tb_ip_arria10_e1sg_tse_sgmii_gx.vhd
@@ -0,0 +1,748 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Testbench for ip_arria10_e1sg_tse_sgmii_gx.
+-- Description:
+-- The tb is self checking based on that tx_pkt_cnt=rx_pkt_cnt must be true
+-- at the tb_end.
+-- Usage:
+-- > as 10
+-- > run -all
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+
+
+ENTITY tb_ip_arria10_e1sg_tse_sgmii_gx IS
+END tb_ip_arria10_e1sg_tse_sgmii_gx;
+
+
+ARCHITECTURE tb OF tb_ip_arria10_e1sg_tse_sgmii_gx IS
+
+ CONSTANT sys_clk_period : TIME := 10 ns; -- 100 MHz
+ CONSTANT eth_clk_period : TIME := 8 ns; -- 125 MHz
+ CONSTANT serial_clk_period : TIME := 800 ps; -- 1250 MHz ????
+ CONSTANT cdr_clk_period : TIME := 8000 ps; -- 125 MHz ????
+
+ CONSTANT c_tse_reg_addr_w : NATURAL := 8; -- = max 256 MAC registers
+ CONSTANT c_tse_byte_addr_w : NATURAL := c_tse_reg_addr_w + 2;
+ CONSTANT c_tse_byte_addr_pcs_offset : NATURAL := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
+ CONSTANT c_tse_data_w : NATURAL := c_word_w; -- = 32
+
+ CONSTANT c_tse_symbol_w : NATURAL := c_byte_w; -- = 8
+ CONSTANT c_tse_symbol_max : NATURAL := 2**c_tse_symbol_w-1; -- = 255
+ CONSTANT c_tse_symbols_per_beat : NATURAL := c_tse_data_w / c_tse_symbol_w; -- = 4
+
+ CONSTANT c_tse_pcs_reg_addr_w : NATURAL := 5; -- = max 32 PCS registers
+ CONSTANT c_tse_pcs_halfword_addr_w : NATURAL := c_tse_pcs_reg_addr_w + 1; -- table 4.17 in ug_ethernet.pdf
+ CONSTANT c_tse_pcs_byte_addr_w : NATURAL := c_tse_pcs_reg_addr_w + 2;
+ CONSTANT c_tse_pcs_data_w : NATURAL := c_halfword_w; -- = 16;
+
+ CONSTANT c_tse_empty_w : NATURAL := 2;
+ CONSTANT c_tse_tx_error_w : NATURAL := 1;
+ CONSTANT c_tse_rx_error_w : NATURAL := 6;
+ CONSTANT c_tse_error_w : NATURAL := largest(c_tse_tx_error_w, c_tse_rx_error_w);
+ CONSTANT c_tse_err_stat_w : NATURAL := 18;
+ CONSTANT c_tse_frm_type_w : NATURAL := 4;
+
+ CONSTANT c_tse_tx_fifo_depth : NATURAL := 256; -- nof words for Tx FIFO
+ CONSTANT c_tse_rx_fifo_depth : NATURAL := 256; -- nof words for Rx FIFO
+
+ CONSTANT c_tse_promis_en : BOOLEAN := FALSE;
+ --CONSTANT c_tse_promis_en : BOOLEAN := TRUE;
+
+ CONSTANT c_tx_data_type : NATURAL := 1; -- 0 = symbols, 1 = counter
+ CONSTANT c_tx_ready_latency : NATURAL := 0;
+ CONSTANT c_nof_tx_not_valid : NATURAL := 0; -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+
+ CONSTANT c_eth_dst_mac : STD_LOGIC_VECTOR(47 DOWNTO 0) := X"10FA01020300";
+ CONSTANT c_eth_src_mac : STD_LOGIC_VECTOR(47 DOWNTO 0) := X"123456789ABC"; -- = 12-34-56-78-9A-BC
+ CONSTANT c_eth_ethertype : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"10FA";
+
+ TYPE t_mm_bus IS RECORD
+ -- Master In Slave Out
+ waitreq : STD_LOGIC;
+ rddata : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ -- Master Out Slave In
+ address : STD_LOGIC_VECTOR(c_tse_byte_addr_w-1 DOWNTO 0);
+ wrdata : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ wr : STD_LOGIC;
+ rd : STD_LOGIC;
+ END RECORD;
+
+ PROCEDURE proc_dbg_mm_bus(SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : IN t_mm_bus;
+ SIGNAL dbg_mm : OUT t_mm_bus) IS
+ BEGIN
+ dbg_mm.waitreq <= mm_miso.waitreq;
+ dbg_mm.rddata <= mm_miso.rddata;
+ dbg_mm.address <= mm_mosi.address;
+ dbg_mm.wrdata <= mm_mosi.wrdata;
+ dbg_mm.wr <= mm_mosi.wr;
+ dbg_mm.rd <= mm_mosi.rd;
+ END proc_dbg_mm_bus;
+
+ -- Wait for MM access (either read or write) finished
+ PROCEDURE proc_mm_access(SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_waitreq : IN STD_LOGIC;
+ SIGNAL mm_access : OUT STD_LOGIC) IS
+ BEGIN
+ mm_access <= '1';
+ WAIT UNTIL rising_edge(mm_clk);
+ WHILE mm_waitreq='1' LOOP
+ WAIT UNTIL rising_edge(mm_clk);
+ END LOOP;
+ mm_access <= '0';
+ END proc_mm_access;
+
+ -- Use word addressing for MAC registers according to table 4.8, 4.9
+ PROCEDURE proc_wr_mac(CONSTANT mac_addr : IN NATURAL;
+ CONSTANT mac_data : IN NATURAL;
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : OUT t_mm_bus) IS
+ BEGIN
+ mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(mac_addr, c_tse_byte_addr_w));
+ mm_mosi.wrdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(mac_data, c_tse_data_w));
+ proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.wr);
+ END proc_wr_mac;
+
+ PROCEDURE proc_rd_mac(CONSTANT mac_addr : IN NATURAL;
+ SIGNAL mac_data : OUT NATURAL;
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : OUT t_mm_bus) IS
+ BEGIN
+ mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(mac_addr, c_tse_byte_addr_w));
+ proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.rd);
+ MAC_data <= TO_INTEGER(UNSIGNED(mm_miso.rddata));
+ END proc_rd_mac;
+
+ -- Use halfword addressing for PCS register to match table 4.17
+ PROCEDURE proc_wr_pcs(CONSTANT pcs_addr : IN NATURAL;
+ CONSTANT pcs_data : IN NATURAL;
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : OUT t_mm_bus) IS
+ BEGIN
+ mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(pcs_addr*2 + c_tse_byte_addr_pcs_offset, c_tse_byte_addr_w));
+ mm_mosi.wrdata <= (OTHERS=>'0');
+ mm_mosi.wrdata(c_tse_pcs_data_w-1 DOWNTO 0) <= STD_LOGIC_VECTOR(TO_UNSIGNED(pcs_data, c_tse_pcs_data_w));
+ proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.wr);
+ END proc_wr_pcs;
+
+ PROCEDURE proc_rd_pcs(CONSTANT pcs_addr : IN NATURAL;
+ SIGNAL pcs_data : OUT NATURAL;
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : OUT t_mm_bus) IS
+ BEGIN
+ mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(pcs_addr*2 + c_tse_byte_addr_pcs_offset, c_tse_byte_addr_w));
+ proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.rd);
+ pcs_data <= TO_INTEGER(UNSIGNED(mm_miso.rddata(c_tse_pcs_data_w-1 DOWNTO 0)));
+ END proc_rd_pcs;
+
+ TYPE t_tse_stream IS RECORD
+ -- Source In or Sink Out
+ ready : STD_LOGIC;
+ -- Source Out or Sink In
+ data : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ valid : STD_LOGIC;
+ sop : STD_LOGIC;
+ eop : STD_LOGIC;
+ empty : STD_LOGIC_VECTOR(c_tse_empty_w-1 DOWNTO 0);
+ err : STD_LOGIC_VECTOR(c_tse_error_w-1 DOWNTO 0);
+ END RECORD;
+
+ PROCEDURE proc_dbg_tse_stream_src(SIGNAL src_in : IN t_tse_stream;
+ SIGNAL src_out : IN t_tse_stream;
+ SIGNAL dbg_src : OUT t_tse_stream) IS
+ BEGIN
+ dbg_src.ready <= src_in.ready;
+ dbg_src.data <= src_out.data;
+ dbg_src.valid <= src_out.valid;
+ dbg_src.sop <= src_out.sop;
+ dbg_src.eop <= src_out.eop;
+ dbg_src.empty <= src_out.empty;
+ dbg_src.err <= src_out.err;
+ END proc_dbg_tse_stream_src;
+
+ PROCEDURE proc_dbg_tse_stream_snk(SIGNAL snk_in : IN t_tse_stream;
+ SIGNAL snk_out : IN t_tse_stream;
+ SIGNAL dbg_snk : OUT t_tse_stream) IS
+ BEGIN
+ dbg_snk.ready <= snk_out.ready;
+ dbg_snk.data <= snk_in.data;
+ dbg_snk.valid <= snk_in.valid;
+ dbg_snk.sop <= snk_in.sop;
+ dbg_snk.eop <= snk_in.eop;
+ dbg_snk.empty <= snk_in.empty;
+ dbg_snk.err <= snk_in.err;
+ END proc_dbg_tse_stream_snk;
+
+ -- Handle TX ready
+ -- Only support tx_ready_latency=0 or 1, corresponding to TX_ALMOST_FULL=3 or 4
+ -- Support for tx_ready_latency>1 requires keeping previous ready information
+ -- in a STD_LOGIC_VECTOR(tx_ready_latency-1 DOWNTO 0).
+ PROCEDURE proc_ready_latency(CONSTANT c_latency : IN NATURAL;
+ SIGNAL clk : IN STD_LOGIC;
+ SIGNAL ready : IN STD_LOGIC;
+ CONSTANT c_valid : IN STD_LOGIC;
+ CONSTANT c_sop : IN STD_LOGIC;
+ CONSTANT c_eop : IN STD_LOGIC;
+ SIGNAL out_valid : OUT STD_LOGIC;
+ SIGNAL out_sop : OUT STD_LOGIC;
+ SIGNAL out_eop : OUT STD_LOGIC) IS
+ BEGIN
+ IF c_latency=0 THEN
+ out_valid <= c_valid;
+ out_sop <= c_sop;
+ out_eop <= c_eop;
+ WAIT UNTIL rising_edge(clk);
+ WHILE ready /= '1' LOOP
+ WAIT UNTIL rising_edge(clk);
+ END LOOP;
+ END IF;
+ IF c_latency=1 THEN
+ WHILE ready /= '1' LOOP
+ out_valid <= '0';
+ out_sop <= '0';
+ out_eop <= '0';
+ WAIT UNTIL rising_edge(clk);
+ END LOOP;
+ out_valid <= c_valid;
+ out_sop <= c_sop;
+ out_eop <= c_eop;
+ WAIT UNTIL rising_edge(clk);
+ END IF;
+ END proc_ready_latency;
+
+ -- Transmit user packet
+ -- . Use word aligned payload data, so with half word inserted before the 14 byte header
+ -- . Packets can be send immediately after eachother so new sop directly after last eop
+ -- . The word rate is controlled by respecting ready from the MAC
+ PROCEDURE proc_tx_packet(CONSTANT dst_mac_addr : IN STD_LOGIC_VECTOR(c_eth_dst_mac'RANGE);
+ CONSTANT src_mac_addr : IN STD_LOGIC_VECTOR(c_eth_src_mac'RANGE);
+ CONSTANT ethertype : IN STD_LOGIC_VECTOR(c_eth_ethertype'RANGE);
+ CONSTANT data_len : IN NATURAL; -- in symbols = octets = bytes
+ SIGNAL dp_clk : IN STD_LOGIC;
+ SIGNAL dp_src_in : IN t_tse_stream;
+ SIGNAL dp_src_out : OUT t_tse_stream) IS
+ CONSTANT c_mod : NATURAL := data_len MOD c_tse_symbols_per_beat;
+ CONSTANT c_nof_data_beats : NATURAL := data_len / c_tse_symbols_per_beat + sel_a_b(c_mod, 1, 0);
+ CONSTANT c_empty : NATURAL := sel_a_b(c_mod, c_tse_symbols_per_beat - c_mod, 0);
+ VARIABLE v_sym : UNSIGNED(c_tse_symbol_w-1 DOWNTO 0) := (OTHERS=>'0');
+ VARIABLE v_num : UNSIGNED(c_tse_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ BEGIN
+ -- DST MAC
+ dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, c_tse_empty_w));
+ dp_src_out.data <= (OTHERS=>'0');
+ dp_src_out.data(15 DOWNTO 0) <= hton(dst_mac_addr(15 DOWNTO 0)); -- send to itself
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '1', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ dp_src_out.data <= hton(dst_mac_addr(47 DOWNTO 16));
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ -- SRC MAC
+ dp_src_out.data <= hton(src_mac_addr(31 DOWNTO 0));
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ -- SRC MAC & ETHERTYPE
+ dp_src_out.data <= hton(src_mac_addr(47 DOWNTO 32)) & hton(c_eth_ethertype);
+ -- DATA
+ FOR I IN 0 TO c_nof_data_beats-1 LOOP
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ IF c_tx_data_type=0 THEN
+ -- data : X"01020304", X"05060708", X"090A0B0C", etc
+ FOR J IN c_tse_symbols_per_beat-1 DOWNTO 0 LOOP
+ v_sym := v_sym + 1;
+ dp_src_out.data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) <= STD_LOGIC_VECTOR(v_sym);
+ END LOOP;
+ ELSE
+ -- data : X"00000001", X"00000002", X"00000003", etc
+ v_num := v_num + 1;
+ dp_src_out.data <= STD_LOGIC_VECTOR(v_num);
+ END IF;
+ -- tb : pull valid low for some time during the middle of the payload
+ IF c_nof_tx_not_valid > 0 AND I=c_nof_data_beats/2 THEN
+ dp_src_out.valid <= '0';
+ FOR I IN 0 TO c_nof_tx_not_valid LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+ dp_src_out.valid <= '1';
+ END IF;
+ END LOOP;
+ IF c_empty > 0 THEN
+ dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(c_empty, c_tse_empty_w));
+ FOR J IN c_empty-1 DOWNTO 0 LOOP
+ dp_src_out.data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) <= (OTHERS=>'0');
+ END LOOP;
+ END IF;
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '1', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ dp_src_out.data <= (OTHERS=>'0');
+ dp_src_out.valid <= '0';
+ dp_src_out.eop <= '0';
+ dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, c_tse_empty_w));
+ END proc_tx_packet;
+
+ PROCEDURE proc_valid_sop(SIGNAL clk : IN STD_LOGIC;
+ SIGNAL in_valid : IN STD_LOGIC;
+ SIGNAL in_sop : IN STD_LOGIC) IS
+ BEGIN
+ WAIT UNTIL rising_edge(clk);
+ WHILE in_valid /= '1' AND in_sop /= '1' LOOP
+ WAIT UNTIL rising_edge(clk);
+ END LOOP;
+ END proc_valid_sop;
+
+ PROCEDURE proc_valid(SIGNAL clk : IN STD_LOGIC;
+ SIGNAL in_valid : IN STD_LOGIC) IS
+ BEGIN
+ WAIT UNTIL rising_edge(clk);
+ WHILE in_valid /= '1' LOOP
+ WAIT UNTIL rising_edge(clk);
+ END LOOP;
+ END proc_valid;
+
+ -- Receive packet
+ -- . Use word aligned payload data, so with half word inserted before the 14 byte header
+ -- . Packets can be always be received, assume the user application is always ready
+ -- . The CRC32 is also passed on to the user at eop.
+ -- . Note that when empty/=0 then the CRC32 is not word aligned, so therefore use prev_data to be able
+ -- to handle part of last data word in case empty/=0 at eop
+ PROCEDURE proc_rx_packet(CONSTANT dst_mac_addr : IN STD_LOGIC_VECTOR(c_eth_dst_mac'RANGE);
+ CONSTANT src_mac_addr : IN STD_LOGIC_VECTOR(c_eth_src_mac'RANGE);
+ CONSTANT ethertype : IN STD_LOGIC_VECTOR(c_eth_ethertype'RANGE);
+ SIGNAL dp_clk : IN STD_LOGIC;
+ SIGNAL dp_snk_in : IN t_tse_stream;
+ SIGNAL dp_snk_out : OUT t_tse_stream) IS
+ VARIABLE v_sym : UNSIGNED(c_tse_symbol_w-1 DOWNTO 0) := (OTHERS=>'0');
+ VARIABLE v_num : UNSIGNED(c_tse_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ VARIABLE v_empty : NATURAL;
+ VARIABLE v_first : BOOLEAN := TRUE;
+ VARIABLE v_data : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ VARIABLE v_prev_data : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ BEGIN
+ -- Keep ff_rx_snk_out.ready='1' all the time
+ dp_snk_out.ready <= '1';
+ -- Verify DST MAC
+ proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop);
+ ASSERT dp_snk_in.data(31 DOWNTO 16) = X"0000" REPORT "RX: Alignment half word not zero" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(15 DOWNTO 0) = hton(dst_mac_addr(15 DOWNTO 0)) REPORT "RX: Wrong dst_mac_addr(15 DOWNTO 0)" SEVERITY ERROR;
+ proc_valid(dp_clk, dp_snk_in.valid);
+ ASSERT dp_snk_in.data(31 DOWNTO 0) = hton(dst_mac_addr(47 DOWNTO 16)) REPORT "RX: Wrong dst_mac_addr(47 DOWNTO 16)" SEVERITY ERROR;
+ -- Verify SRC MAC
+ proc_valid(dp_clk, dp_snk_in.valid);
+ ASSERT dp_snk_in.data(31 DOWNTO 0) = hton(src_mac_addr(31 DOWNTO 0)) REPORT "RX: Wrong src_mac_addr(31 DOWNTO 0)" SEVERITY ERROR;
+ -- Verify SRC MAC & ETHERTYPE
+ proc_valid(dp_clk, dp_snk_in.valid);
+ ASSERT dp_snk_in.data(31 DOWNTO 16) = hton(src_mac_addr(47 DOWNTO 32)) REPORT "RX: Wrong src_mac_addr(47 DOWNTO 32)" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(15 DOWNTO 0) = hton(c_eth_ethertype) REPORT "RX: Wrong ethertype" SEVERITY ERROR;
+ -- Verify DATA
+ v_first := TRUE;
+ proc_valid(dp_clk, dp_snk_in.valid);
+ WHILE dp_snk_in.eop /= '1' LOOP
+ v_prev_data := v_data;
+ v_data := dp_snk_in.data;
+ IF v_first = FALSE THEN
+ IF c_tx_data_type=0 THEN
+ -- data : X"01020304", X"05060708", X"090A0B0C", etc
+ FOR J IN c_tse_symbols_per_beat-1 DOWNTO 0 LOOP
+ v_sym := v_sym + 1;
+ ASSERT UNSIGNED(v_prev_data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w)) = v_sym REPORT "RX: Wrong data symbol" SEVERITY ERROR;
+ END LOOP;
+ ELSE
+ -- data : X"00000001", X"00000002", X"00000003", etc
+ v_num := v_num + 1;
+ ASSERT UNSIGNED(v_prev_data) = v_num REPORT "RX: Wrong data word" SEVERITY ERROR;
+ END IF;
+ END IF;
+ v_first := FALSE;
+ proc_valid(dp_clk, dp_snk_in.valid);
+ END LOOP;
+ -- Verify last DATA and CRC32 if empty /=0 else the last word is only the CRC32
+ v_prev_data := v_data;
+ v_data := dp_snk_in.data;
+ v_empty := TO_INTEGER(UNSIGNED(dp_snk_in.empty));
+ IF v_empty > 0 THEN
+ FOR J IN v_empty-1 DOWNTO 0 LOOP
+ v_prev_data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) := (OTHERS=>'0');
+ END LOOP;
+ IF c_tx_data_type=0 THEN
+ -- data : X"01020304", X"05060708", X"090A0B0C", etc
+ FOR J IN c_tse_symbols_per_beat-1 DOWNTO v_empty LOOP -- ignore CRC32 symbols in last data word
+ v_sym := v_sym + 1;
+ ASSERT UNSIGNED(v_prev_data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w)) = v_sym REPORT "RX: Wrong empty data symbol" SEVERITY ERROR;
+ END LOOP;
+ ELSE
+ -- data : X"00000001", X"00000002", X"00000003", etc
+ v_num := v_num + 1;
+ FOR J IN v_empty-1 DOWNTO 0 LOOP
+ v_num((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) := (OTHERS=>'0'); -- force CRC32 symbols in last data word to 0
+ END LOOP;
+ ASSERT UNSIGNED(v_prev_data) = v_num REPORT "RX: Wrong empty data word" SEVERITY ERROR;
+ END IF;
+ ELSE
+ -- No verify on CRC32 word
+ END IF;
+ END proc_rx_packet;
+
+
+ -- Clocks and reset
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL sys_clk : STD_LOGIC := '0';
+ SIGNAL dp_clk : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+
+ -- TSE MAC control interface
+ SIGNAL mm_init : STD_LOGIC := '1';
+ SIGNAL mm_miso : t_mm_bus; -- master in slave out
+ SIGNAL mm_mosi : t_mm_bus; -- master out slave in
+
+ SIGNAL pcs_rddata : NATURAL; -- [c_tse_pcs_data_w-1:0]
+
+ SIGNAL tse_led_an : STD_LOGIC;
+ SIGNAL tse_led_link : STD_LOGIC;
+
+ -- TSE MAC transmit interface
+ -- . Avalon ST source
+ SIGNAL ff_tx_src_in : t_tse_stream;
+ SIGNAL ff_tx_src_out : t_tse_stream;
+ -- . MAC specific
+ SIGNAL ff_tx_crc_fwd : STD_LOGIC;
+ SIGNAL ff_tx_septy : STD_LOGIC;
+ SIGNAL ff_tx_a_full : STD_LOGIC;
+ SIGNAL ff_tx_a_empty : STD_LOGIC;
+ SIGNAL ff_tx_uflow : STD_LOGIC;
+
+ -- TSE MAC receive interface
+ -- . Avalon ST sink
+ SIGNAL ff_rx_snk_in : t_tse_stream;
+ SIGNAL ff_rx_snk_out : t_tse_stream;
+ -- . MAC specific
+ SIGNAL ff_rx_ethertype: STD_LOGIC_VECTOR(c_tse_err_stat_w-1 DOWNTO 0);
+ SIGNAL ff_rx_frm_type : STD_LOGIC_VECTOR(c_tse_frm_type_w-1 DOWNTO 0);
+ SIGNAL ff_rx_dsav : STD_LOGIC;
+ SIGNAL ff_rx_a_full : STD_LOGIC;
+ SIGNAL ff_rx_a_empty : STD_LOGIC;
+
+ -- TSE PHY interface
+ SIGNAL eth_txp : STD_LOGIC;
+ SIGNAL eth_rxp : STD_LOGIC;
+
+ -- TSE PHY GX
+ SIGNAL tx_serial_clk : STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL rx_cdr_refclk : STD_LOGIC := '0';
+
+ -- Verification
+ SIGNAL tx_pkt_cnt : NATURAL := 0;
+ SIGNAL rx_pkt_cnt : NATURAL := 0;
+
+ -- Debug signals to combine valid in and out of records
+ SIGNAL dbg_mm : t_mm_bus;
+ SIGNAL dbg_ff_tx : t_tse_stream;
+ SIGNAL dbg_ff_rx : t_tse_stream;
+
+BEGIN
+
+ eth_clk <= NOT eth_clk AFTER eth_clk_period/2; -- TSE reference clock
+ sys_clk <= NOT sys_clk AFTER sys_clk_period/2; -- System clock
+
+ mm_clk <= sys_clk;
+ dp_clk <= sys_clk;
+
+ -- Debug signals to combine valid in and out of records
+ proc_dbg_mm_bus( mm_miso, mm_mosi, dbg_mm);
+ proc_dbg_tse_stream_src(ff_tx_src_in, ff_tx_src_out, dbg_ff_tx);
+ proc_dbg_tse_stream_snk(ff_rx_snk_in, ff_rx_snk_out, dbg_ff_rx);
+
+ -- run 1 us
+ p_mm_stimuli : PROCESS
+ BEGIN
+ mm_init <= '1';
+ mm_mosi.wr <= '0';
+ mm_mosi.rd <= '0';
+
+ -- reset release
+ mm_rst <= '1';
+ FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
+ mm_rst <= '0';
+ FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
+
+ -- PSC control
+ proc_rd_pcs(16#22#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- REV --> 0x0901
+ proc_wr_pcs(16#28#, 16#0008#, mm_clk, mm_miso, mm_mosi); -- IF_MODE <-- Force 1GbE, no autonegatiation
+ proc_rd_pcs(16#00#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- CONTROL --> 0x1140
+ proc_rd_pcs(16#02#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- STATUS --> 0x000D
+ proc_wr_pcs(16#00#, 16#0140#, mm_clk, mm_miso, mm_mosi); -- CONTROL <-- Auto negotiate disable
+
+ -- MAC control
+ proc_rd_mac(16#000#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- REV --> CUST_VERSION & 0x0901
+ IF c_tse_promis_en=FALSE THEN
+ proc_wr_mac(16#008#, 16#0100004B#, mm_clk, mm_miso, mm_mosi);
+ ELSE
+ proc_wr_mac(16#008#, 16#0100005B#, mm_clk, mm_miso, mm_mosi);
+ END IF;
+ -- COMMAND_CONFIG <--
+ -- Only the bits relevant to UniBoard are explained here, others are 0
+ -- [ 0] = TX_ENA = 1, enable tx datapath
+ -- [ 1] = RX_ENA = 1, enable rx datapath
+ -- [ 2] = XON_GEN = 0
+ -- [ 3] = ETH_SPEED = 1, enable 1GbE operation
+ -- [ 4] = PROMIS_EN = 0, when 1 then receive all frames
+ -- [ 5] = PAD_EN = 0, when 1 enable receive padding removal (requires ethertype=payload length)
+ -- [ 6] = CRC_FWD = 1, enable receive CRC forward
+ -- [ 7] = PAUSE_FWD = 0
+ -- [ 8] = PAUSE_IGNORE = 0
+ -- [ 9] = TX_ADDR_INS = 0, when 1 then MAX overwrites tx SRC MAC with mac_0,1 or one of the supplemental mac
+ -- [ 10] = HD_ENA = 0
+ -- [ 11] = EXCESS_COL = 0
+ -- [ 12] = LATE_COL = 0
+ -- [ 13] = SW_RESET = 0, when 1 MAC disables tx and rx, clear statistics and flushes receive FIFO
+ -- [ 14] = MHAS_SEL = 0, select multicast address resolutions hash-code mode
+ -- [ 15] = LOOP_ENA = 0
+ -- [18-16] = TX_ADDR_SEL[2:0] = 000, TX_ADDR_INS insert mac_0,1 or one of the supplemental mac
+ -- [ 19] = MAGIC_EN = 0
+ -- [ 20] = SLEEP = 0
+ -- [ 21] = WAKEUP = 0
+ -- [ 22] = XOFF_GEN = 0
+ -- [ 23] = CNT_FRM_ENA = 0
+ -- [ 24] = NO_LGTH_CHECK = 1, when 0 then check payload length of received frames (requires ethertype=payload length)
+ -- [ 25] = ENA_10 = 0
+ -- [ 26] = RX_ERR_DISC = 0, when 1 then discard erroneous frames (requires store and forward mode, so rx_section_full=0)
+ -- when 0 then pass on with rx_err[0]=1
+ -- [ 27] = DISABLE_RD_TIMEOUT = 0
+ -- [30-28] = RSVD = 000
+ -- [ 31] = CNT_RESET = 0, when 1 clear statistics
+ proc_wr_mac(16#00C#, 16#56789ABC#, mm_clk, mm_miso, mm_mosi); -- MAC_0
+ proc_wr_mac(16#010#, 16#00001234#, mm_clk, mm_miso, mm_mosi); -- MAC_1 <-- SRC_MAC = 12-34-56-78-9A-BC
+ proc_wr_mac(16#05C#, 16#0000000C#, mm_clk, mm_miso, mm_mosi); -- TX_IPG_LENGTH <-- interpacket gap = 12
+ proc_wr_mac(16#014#, 16#000005EE#, mm_clk, mm_miso, mm_mosi); -- FRM_LENGTH <-- receive max frame length = 1518
+
+ -- FIFO legenda:
+ -- . Tx section full = There is enough data in the FIFO to start reading it, when 0 then store and forward.
+ -- . Rx section full = There is enough data in the FIFO to start reading it, when 0 then store and forward.
+ -- . Tx section empty = There is not much empty space anymore in the FIFO, warn user via ff_tx_septy
+ -- . Rx section empty = There is not much empty space anymore in the FIFO, inform remote device via XOFF flow control
+ -- . Tx almost full = Assert ff_tx_a_full and deassert ff_tx_rdy. Furthermore TX_ALMOST_FULL = c_tx_ready_latency+3,
+ -- so choose 3 for zero tx ready latency
+ -- . Rx almost full = Assert ff_rx_a_full and if the user is not ready ff_rx_rdy then:
+ -- --> break off the reception with an error to avoid FIFO overflow
+ -- . Tx almost empty = Assert ff_tx_a_empty and if the FIFO does not contain a eop yet then:
+ -- --> break off the transmission with an error to avoid FIFO underflow
+ -- . Rx almost empty = Assert ff_rx_a_empty
+ -- Typical FIFO values:
+ -- . TX_SECTION_FULL = 16 > 8 = TX_ALMOST_EMPTY
+ -- . RX_SECTION_FULL = 16 > 8 = RX_ALMOST_EMPTY
+ -- . TX_SECTION_EMPTY = D-16 < D-3 = Tx FIFO depth - TX_ALMOST_FULL
+ -- . RX_SECTION_EMPTY = D-16 < D-8 = Rx FIFO depth - RX_ALMOST_FULL
+ -- . c_tse_tx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Tx user respects ff_tx_rdy, to store a complete
+ -- ETH packet would require 1518 byte, so 2 M9K = 2k * 8b
+ -- . c_tse_rx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Rx user ff_rx_rdy is sufficiently active
+ proc_wr_mac(16#01C#, c_tse_rx_fifo_depth-16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_wr_mac(16#020#, 16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_FULL <-- default 16
+ proc_wr_mac(16#024#, c_tse_tx_fifo_depth-16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_wr_mac(16#028#, 16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
+ proc_wr_mac(16#02C#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_EMPTY <-- default 8
+ proc_wr_mac(16#030#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_FULL <-- default 8
+ proc_wr_mac(16#034#, 8, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_EMPTY <-- default 8
+ proc_wr_mac(16#038#, c_tx_ready_latency+3, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_FULL <-- default 3
+
+ proc_rd_mac(16#0E8#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- TX_CMD_STAT --> 0x00040000 : [18]=1 TX_SHIFT16, [17]=0 OMIT_CRC
+ proc_rd_mac(16#0EC#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- RX_CMD_STAT --> 0x02000000 : [25]=1 RX_SHIFT16
+
+ WAIT UNTIL rising_edge(mm_clk);
+ mm_init <= '0';
+
+ WAIT;
+ END PROCESS;
+
+ p_tx_frame : PROCESS
+ BEGIN
+ -- . Avalon ST
+ ff_tx_src_out.data <= (OTHERS=>'0');
+ ff_tx_src_out.valid <= '0';
+ ff_tx_src_out.sop <= '0';
+ ff_tx_src_out.eop <= '0';
+ ff_tx_src_out.empty <= (OTHERS=>'0');
+ ff_tx_src_out.err <= (OTHERS=>'0');
+ -- . MAC specific
+ ff_tx_crc_fwd <= '0';
+
+ WHILE mm_init/='0' LOOP
+ WAIT UNTIL rising_edge(dp_clk);
+ END LOOP;
+ WHILE tse_led_link/='1' LOOP
+ WAIT UNTIL rising_edge(dp_clk);
+ END LOOP;
+ FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, "0000000000010000", 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+ proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1499, dp_clk, ff_tx_src_in, ff_tx_src_out); -- verify st empty
+ proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+
+ FOR I IN 0 TO 1500 * 4 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+ p_rx_frame : PROCESS
+ BEGIN
+ -- . Avalon ST
+ ff_rx_snk_out.ready <= '0';
+
+ WHILE mm_init/='0' LOOP
+ WAIT UNTIL rising_edge(dp_clk);
+ END LOOP;
+
+ -- Receive forever
+ WHILE TRUE LOOP
+ proc_rx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, dp_clk, ff_rx_snk_in, ff_rx_snk_out);
+ END LOOP;
+
+ WAIT;
+ END PROCESS;
+
+ dut : ENTITY work.ip_arria10_e1sg_tse_sgmii_gx
+ -- The ip_arria10_e1sg_tse_sgmii_gx needs to be regenerated if its parameters are changed.
+ -- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
+ -- . ENABLE_SUP_ADDR = 0 : An extra MAC addresses can e.g. be used as service MAC for tests
+ -- . ENA_HASH = 0 : A multi cast hash table can be used to address all nodes at once
+ -- . STAT_CNT_ENA = 0 : PHY statistics counts are useful for monitoring, but not realy needed
+ -- . EG_FIFO = 256 : Tx FIFO depth in nof 32 bit words (256 --> 1 M9K)
+ -- . ING_FIFO = 256 : Rx FIFO depth in nof 32 bit words (256 --> 1 M9K)
+ PORT MAP (
+ -- MAC transmit interface
+ -- . Avalon ST
+ ff_tx_clk => dp_clk, -- : in std_logic := '0'; -- transmit_clock_connection.clk
+ ff_tx_rdy => ff_tx_src_in.ready, -- : out std_logic; -- .ready
+ ff_tx_data => ff_tx_src_out.data, -- : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
+ ff_tx_wren => ff_tx_src_out.valid, -- : in std_logic := '0'; -- .valid
+ ff_tx_sop => ff_tx_src_out.sop, -- : in std_logic := '0'; -- .startofpacket
+ ff_tx_eop => ff_tx_src_out.eop, -- : in std_logic := '0'; -- .endofpacket
+ ff_tx_mod => ff_tx_src_out.empty, -- : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
+ ff_tx_err => ff_tx_src_out.err(0), -- : in std_logic := '0'; -- .error
+ -- . MAC specific
+ ff_tx_crc_fwd => ff_tx_crc_fwd, -- : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd -- when '0' MAC inserts CRC32 after eop
+ ff_tx_septy => ff_tx_septy, -- : out std_logic; -- .ff_tx_septy -- when '0' then tx FIFO goes above section-empty threshold
+ ff_tx_a_full => ff_tx_a_full, -- : out std_logic; -- .ff_tx_a_full -- when '1' then tx FIFO goes above almost-full threshold
+ ff_tx_a_empty => ff_tx_a_empty, -- : out std_logic; -- .ff_tx_a_empty -- when '1' then tx FIFO goes below almost-empty threshold
+ tx_ff_uflow => ff_tx_uflow, -- : out std_logic; -- .tx_ff_uflow -- when '1' then tx FIFO underflow
+ -- MAC receive interface
+ -- . Avalon STs
+ ff_rx_clk => dp_clk, -- : in std_logic := '0'; -- receive_clock_connection.clk
+ ff_rx_rdy => ff_rx_snk_out.ready, -- : in std_logic := '0'; -- .ready
+ ff_rx_data => ff_rx_snk_in.data, -- : out std_logic_vector(31 downto 0); -- receive.data
+ ff_rx_dval => ff_rx_snk_in.valid, -- : out std_logic; -- .valid
+ ff_rx_sop => ff_rx_snk_in.sop, -- : out std_logic; -- .startofpacket
+ ff_rx_eop => ff_rx_snk_in.eop, -- : out std_logic; -- .endofpacket
+ ff_rx_mod => ff_rx_snk_in.empty, -- : out std_logic_vector(1 downto 0); -- .empty
+ rx_err => ff_rx_snk_in.err, -- : out std_logic_vector(5 downto 0); -- .error
+ -- [5] collision error (can only occur in half duplex mode)
+ -- [4] PHY error on GMII
+ -- [3] receive frame truncated due to FIFO overflow
+ -- [2] CRC-32 error
+ -- [1] invalid length
+ -- [0] = OR of [1:5]
+ -- . MAC specific
+ rx_err_stat => ff_rx_ethertype, -- : out std_logic_vector(17 downto 0); -- .rx_err_stat -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+ rx_frm_type => ff_rx_frm_type, -- : out std_logic_vector(3 downto 0); -- .rx_frm_type -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+ ff_rx_dsav => ff_rx_dsav, -- : out std_logic; -- .ff_rx_dsav -- rx frame available, but not necessarily a complete frame
+ ff_rx_a_full => ff_rx_a_full, -- : out std_logic; -- .ff_rx_a_full -- when '1' then rx FIFO goes above almost-full threshold
+ ff_rx_a_empty => ff_rx_a_empty, -- : out std_logic; -- .ff_rx_a_empty -- when '1' sthen rx FIFO goes below almost-empty threshold
+ -- Reset
+ reset => mm_rst, -- : in std_logic := '0'; -- reset_connection.reset -- asynchronous reset (choose synchronous to mm_clk)
+ -- MM control interface
+ clk => mm_clk, -- : in std_logic := '0'; -- control_port_clock_connection.clk
+ reg_addr => mm_mosi.address(c_tse_byte_addr_w-1 DOWNTO 2), -- : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
+ reg_data_out => mm_miso.rddata, -- : out std_logic_vector(31 downto 0); -- control_port.readdata
+ reg_rd => mm_mosi.rd, -- : in std_logic := '0'; -- .read
+ reg_data_in => mm_mosi.wrdata, -- : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reg_wr => mm_mosi.wr, -- : in std_logic := '0'; -- .write
+ reg_busy => mm_miso.waitreq, -- : out std_logic; -- .waitrequest
+ -- Status LEDs
+ led_an => tse_led_an, -- : out std_logic; -- .an -- '1' = autonegation completed
+ led_link => tse_led_link, -- : out std_logic; -- .link -- '1' = successful link synchronisation
+ led_disp_err => OPEN, -- : out std_logic; -- .disp_err -- TBI character error
+ led_char_err => OPEN, -- : out std_logic; -- .char_err -- TBI disparity errorreceived
+ led_crs => OPEN, -- : out std_logic; -- status_led_connection.crs
+ led_col => OPEN, -- : out std_logic; -- .col
+ -- Serial 1.25 Gbps
+ rx_recovclkout => OPEN, -- : out std_logic; -- serdes_control_connection.export
+ ref_clk => eth_clk, -- : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
+ txp => eth_txp, -- : out std_logic -- .txp_0
+ rxp => eth_rxp, -- : in std_logic := '0'; -- serial_connection.rxp_0
+
+ tx_serial_clk => tx_serial_clk, -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk.clk
+ rx_cdr_refclk => rx_cdr_refclk, -- : in std_logic := '0'; -- rx_cdr_refclk.clk
+ tx_analogreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_digitalreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ rx_analogreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_digitalreset => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ tx_cal_busy => OPEN, -- : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
+ rx_cal_busy => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_set_locktodata => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktodata.rx_set_locktodata
+ rx_set_locktoref => (others => '0'), -- : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_set_locktoref.rx_set_locktoref
+ rx_is_lockedtoref => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_is_lockedtodata => OPEN -- : out std_logic_vector(0 downto 0) -- rx_is_lockedtodata.rx_is_lockedtodata
+ );
+
+ -- To be corrected
+ tx_serial_clk(0) <= NOT tx_serial_clk(0) AFTER serial_clk_period/2; -- ????
+ rx_cdr_refclk <= NOT rx_cdr_refclk AFTER cdr_clk_period/2; -- ????
+
+ -- Loopback
+ eth_rxp <= eth_txp;
+
+ -- Verification
+ tx_pkt_cnt <= tx_pkt_cnt + 1 WHEN ff_tx_src_out.sop='1' AND rising_edge(dp_clk);
+ rx_pkt_cnt <= rx_pkt_cnt + 1 WHEN ff_rx_snk_in.eop='1' AND rising_edge(dp_clk);
+
+ p_tb_end : PROCESS
+ BEGIN
+ WAIT UNTIL tb_end='1';
+
+ -- Verify that all transmitted packets have been received
+ IF tx_pkt_cnt=0 THEN
+ REPORT "No packets were transmitted." SEVERITY ERROR;
+ ELSIF rx_pkt_cnt=0 THEN
+ REPORT "No packets were received." SEVERITY ERROR;
+ ELSIF tx_pkt_cnt/=rx_pkt_cnt THEN
+ REPORT "Not all transmitted packets were received." SEVERITY ERROR;
+ END IF;
+
+ -- Stop the simulation
+ ASSERT FALSE REPORT "Simulation finished." SEVERITY FAILURE;
+ WAIT;
+ END PROCESS;
+
+END tb;
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.patch b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.patch
new file mode 100644
index 0000000000000000000000000000000000000000..2fdf7a6eb7602fa32297fdc9b794576feafeefe8
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.patch
@@ -0,0 +1,3 @@
+The patch is generated with:
+
+diff -cB ip_arria10_e3sge3_tse_sgmii_lvds/altera_lvds_core20_151/synth/sdc_util.tcl generated/altera_lvds_core20_151/synth/sdc_util.tcl > sdc_util.sdc.patch
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt
new file mode 100755
index 0000000000000000000000000000000000000000..0120d49c00e2d190883becf573ccc25eabdf798f
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt
@@ -0,0 +1,4 @@
+README.txt for $RADIOHDL/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+
+See README.txt for $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds
+
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..759e0042528a23b777bec5d2baed1fc684275a83
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/generate_ip.sh
@@ -0,0 +1,54 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_tse_sgmii_lvds.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
+
+# Also generate the testbench IP
+#qsys-generate ip_arria10_e1sg_tse_sgmii_lvds.qsys \
+# --synthesis=VHDL \
+# --simulation=VHDL \
+# --testbench=STANDARD \
+# --testbench-simulation=VHDL \
+# --output-directory=generated \
+# --allow-mixed-language-simulation \
+# --allow-mixed-language-testbench-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..8b7150fdc0e6f33da1141ca02576e8a130a41bac
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
@@ -0,0 +1,21 @@
+hdl_lib_name = ip_arria10_e1sg_tse_sgmii_lvds
+hdl_library_clause_name = ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_151
+hdl_lib_uses_synth = common
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+ tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+ generated/ip_arria10_e1sg_tse_sgmii_lvds.qip
+
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qsys b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..957af3182f47ae30655c86def92761c4705b02ea
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qsys
@@ -0,0 +1,244 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_tse_sgmii_lvds">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element eth_tse_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>control_port</key>
+ <value>
+ <connectionPointName>control_port</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='control_port' start='0x0' end='0x400' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>10</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+ name="control_port"
+ internal="eth_tse_0.control_port"
+ type="avalon"
+ dir="end">
+ <port name="reg_addr" internal="reg_addr" />
+ <port name="reg_busy" internal="reg_busy" />
+ <port name="reg_data_in" internal="reg_data_in" />
+ <port name="reg_data_out" internal="reg_data_out" />
+ <port name="reg_rd" internal="reg_rd" />
+ <port name="reg_wr" internal="reg_wr" />
+ </interface>
+ <interface
+ name="control_port_clock_connection"
+ internal="eth_tse_0.control_port_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="clk" internal="clk" />
+ </interface>
+ <interface name="mac_gmii_connection" internal="eth_tse_0.mac_gmii_connection" />
+ <interface name="mac_mii_connection" internal="eth_tse_0.mac_mii_connection" />
+ <interface
+ name="mac_misc_connection"
+ internal="eth_tse_0.mac_misc_connection"
+ type="conduit"
+ dir="end">
+ <port name="ff_rx_a_empty" internal="ff_rx_a_empty" />
+ <port name="ff_rx_a_full" internal="ff_rx_a_full" />
+ <port name="ff_rx_dsav" internal="ff_rx_dsav" />
+ <port name="ff_tx_a_empty" internal="ff_tx_a_empty" />
+ <port name="ff_tx_a_full" internal="ff_tx_a_full" />
+ <port name="ff_tx_crc_fwd" internal="ff_tx_crc_fwd" />
+ <port name="ff_tx_septy" internal="ff_tx_septy" />
+ <port name="rx_err_stat" internal="rx_err_stat" />
+ <port name="rx_frm_type" internal="rx_frm_type" />
+ <port name="tx_ff_uflow" internal="tx_ff_uflow" />
+ </interface>
+ <interface
+ name="mac_status_connection"
+ internal="eth_tse_0.mac_status_connection" />
+ <interface
+ name="pcs_mac_rx_clock_connection"
+ internal="eth_tse_0.pcs_mac_rx_clock_connection" />
+ <interface
+ name="pcs_mac_tx_clock_connection"
+ internal="eth_tse_0.pcs_mac_tx_clock_connection" />
+ <interface
+ name="pcs_ref_clk_clock_connection"
+ internal="eth_tse_0.pcs_ref_clk_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="ref_clk" internal="ref_clk" />
+ </interface>
+ <interface
+ name="receive"
+ internal="eth_tse_0.receive"
+ type="avalon_streaming"
+ dir="start">
+ <port name="ff_rx_data" internal="ff_rx_data" />
+ <port name="ff_rx_dval" internal="ff_rx_dval" />
+ <port name="ff_rx_eop" internal="ff_rx_eop" />
+ <port name="ff_rx_mod" internal="ff_rx_mod" />
+ <port name="ff_rx_rdy" internal="ff_rx_rdy" />
+ <port name="ff_rx_sop" internal="ff_rx_sop" />
+ <port name="rx_err" internal="rx_err" />
+ </interface>
+ <interface
+ name="receive_clock_connection"
+ internal="eth_tse_0.receive_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="ff_rx_clk" internal="ff_rx_clk" />
+ </interface>
+ <interface
+ name="reset_connection"
+ internal="eth_tse_0.reset_connection"
+ type="reset"
+ dir="end">
+ <port name="reset" internal="reset" />
+ </interface>
+ <interface
+ name="serdes_control_connection"
+ internal="eth_tse_0.serdes_control_connection"
+ type="conduit"
+ dir="end">
+ <port name="rx_recovclkout" internal="rx_recovclkout" />
+ </interface>
+ <interface
+ name="serial_connection"
+ internal="eth_tse_0.serial_connection"
+ type="conduit"
+ dir="end">
+ <port name="rxp" internal="rxp" />
+ <port name="txp" internal="txp" />
+ </interface>
+ <interface
+ name="status_led_connection"
+ internal="eth_tse_0.status_led_connection"
+ type="conduit"
+ dir="end">
+ <port name="led_an" internal="led_an" />
+ <port name="led_char_err" internal="led_char_err" />
+ <port name="led_col" internal="led_col" />
+ <port name="led_crs" internal="led_crs" />
+ <port name="led_disp_err" internal="led_disp_err" />
+ <port name="led_link" internal="led_link" />
+ </interface>
+ <interface name="tbi_connection" internal="eth_tse_0.tbi_connection" />
+ <interface
+ name="transmit"
+ internal="eth_tse_0.transmit"
+ type="avalon_streaming"
+ dir="end">
+ <port name="ff_tx_data" internal="ff_tx_data" />
+ <port name="ff_tx_eop" internal="ff_tx_eop" />
+ <port name="ff_tx_err" internal="ff_tx_err" />
+ <port name="ff_tx_mod" internal="ff_tx_mod" />
+ <port name="ff_tx_rdy" internal="ff_tx_rdy" />
+ <port name="ff_tx_sop" internal="ff_tx_sop" />
+ <port name="ff_tx_wren" internal="ff_tx_wren" />
+ </interface>
+ <interface
+ name="transmit_clock_connection"
+ internal="eth_tse_0.transmit_clock_connection"
+ type="clock"
+ dir="end">
+ <port name="ff_tx_clk" internal="ff_tx_clk" />
+ </interface>
+ <module
+ name="eth_tse_0"
+ kind="altera_eth_tse"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="AUTO_DEVICE" value="10AX115S2F45E1SG" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
+ <parameter name="core_variation" value="MAC_PCS" />
+ <parameter name="deviceFamilyName" value="Arria 10" />
+ <parameter name="eg_addr" value="8" />
+ <parameter name="ena_hash" value="false" />
+ <parameter name="enable_alt_reconfig" value="false" />
+ <parameter name="enable_ecc" value="false" />
+ <parameter name="enable_ena" value="32" />
+ <parameter name="enable_gmii_loopback" value="true" />
+ <parameter name="enable_hd_logic" value="false" />
+ <parameter name="enable_mac_flow_ctrl" value="false" />
+ <parameter name="enable_mac_vlan" value="false" />
+ <parameter name="enable_magic_detect" value="false" />
+ <parameter name="enable_ptp_1step" value="false" />
+ <parameter name="enable_sgmii" value="false" />
+ <parameter name="enable_shift16" value="true" />
+ <parameter name="enable_sup_addr" value="false" />
+ <parameter name="enable_timestamping" value="false" />
+ <parameter name="enable_use_internal_fifo" value="true" />
+ <parameter name="export_pwrdn" value="false" />
+ <parameter name="ext_stat_cnt_ena" value="false" />
+ <parameter name="ifGMII" value="MII_GMII" />
+ <parameter name="ing_addr" value="8" />
+ <parameter name="max_channels" value="1" />
+ <parameter name="mdio_clk_div" value="40" />
+ <parameter name="nf_phyip_rcfg_enable" value="false" />
+ <parameter name="phy_identifier" value="0" />
+ <parameter name="phyip_en_synce_support" value="false" />
+ <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
+ <parameter name="phyip_pll_type" value="CMU" />
+ <parameter name="phyip_pma_bonding_mode" value="x1" />
+ <parameter name="starting_channel_number" value="0" />
+ <parameter name="stat_cnt_ena" value="true" />
+ <parameter name="transceiver_type" value="LVDS_IO" />
+ <parameter name="tstamp_fp_width" value="4" />
+ <parameter name="useMDIO" value="false" />
+ <parameter name="use_mac_clken" value="false" />
+ <parameter name="use_misc_ports" value="true" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/run_patch.sh b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/run_patch.sh
new file mode 100755
index 0000000000000000000000000000000000000000..05a043f5a296d48fd8a9354894bef22b7c74d5af
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/run_patch.sh
@@ -0,0 +1,10 @@
+#!/bin/bash
+
+patchfile='sdc_util.sdc.patch'
+
+echo -e "Applying patch: $patchfile\n"
+
+cd generated/altera_lvds_core20_160/synth
+patch <../../../${patchfile}
+
+echo "done."
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/sdc_util.sdc.patch b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/sdc_util.sdc.patch
new file mode 100644
index 0000000000000000000000000000000000000000..1cd9335d8eb7728af5909e0af15591a97217f79b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/sdc_util.sdc.patch
@@ -0,0 +1,31 @@
+*** ip_arria10_e3sge3_tse_sgmii_lvds/altera_lvds_core20_160/synth/sdc_util.tcl 2016-01-29 11:25:55.709095784 +0100
+--- generated/altera_lvds_core20_160/synth/sdc_util.tcl 2016-01-29 11:27:18.456556665 +0100
+***************
+*** 63,75 ****
+
+ eval "create_generated_clock \
+ -name $opts(-name) \
+! -source $opts(-source) \
+ -multiply_by $multiply_by \
+ -divide_by $opts(-divide_by) \
+ -phase $opts(-phase) \
+ -duty_cycle $opts(-duty_cycle) \
+ $extra_params \
+! $opts(-target)"
+ }
+
+ proc altera_iosubsystem_get_clock_name_from_target { target } {
+--- 63,75 ----
+
+ eval "create_generated_clock \
+ -name $opts(-name) \
+! -source \{$opts(-source)\} \
+ -multiply_by $multiply_by \
+ -divide_by $opts(-divide_by) \
+ -phase $opts(-phase) \
+ -duty_cycle $opts(-duty_cycle) \
+ $extra_params \
+! \{$opts(-target)\}"
+ }
+
+ proc altera_iosubsystem_get_clock_name_from_target { target } {
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c849ba76746d41eaf480b9498cba70022915857a
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd
@@ -0,0 +1,730 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Testbench for ip_arria10_e1sg_tse_sgmii_lvds.
+-- Description:
+-- The testbench in /testbench/tse_sgmii_lvds/tse_sgmii_lvds_tb.vhd that is
+-- generated by the MegaWizard provides an elaborate testbench. For
+-- Uniboard purposes in tb/ a minimal testbench tb_tse_sgmii_lvds.vhd was
+-- derived manually from the generated testbench. This tb_tse_sgmii_lvds
+-- is more easy to use.
+-- The tb is self checking based on that tx_pkt_cnt=rx_pkt_cnt must be true
+-- at the tb_end.
+-- Usage:
+-- > as 10
+-- > run -all
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+
+
+ENTITY tb_ip_arria10_e1sg_tse_sgmii_lvds IS
+END tb_ip_arria10_e1sg_tse_sgmii_lvds;
+
+
+ARCHITECTURE tb OF tb_ip_arria10_e1sg_tse_sgmii_lvds IS
+
+ CONSTANT sys_clk_period : TIME := 10 ns; -- 100 MHz
+ CONSTANT eth_clk_period : TIME := 8 ns; -- 125 MHz
+
+ CONSTANT c_tse_reg_addr_w : NATURAL := 8; -- = max 256 MAC registers
+ CONSTANT c_tse_byte_addr_w : NATURAL := c_tse_reg_addr_w + 2;
+ CONSTANT c_tse_byte_addr_pcs_offset : NATURAL := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
+ CONSTANT c_tse_data_w : NATURAL := c_word_w; -- = 32
+
+ CONSTANT c_tse_symbol_w : NATURAL := c_byte_w; -- = 8
+ CONSTANT c_tse_symbol_max : NATURAL := 2**c_tse_symbol_w-1; -- = 255
+ CONSTANT c_tse_symbols_per_beat : NATURAL := c_tse_data_w / c_tse_symbol_w; -- = 4
+
+ CONSTANT c_tse_pcs_reg_addr_w : NATURAL := 5; -- = max 32 PCS registers
+ CONSTANT c_tse_pcs_halfword_addr_w : NATURAL := c_tse_pcs_reg_addr_w + 1; -- table 4.17 in ug_ethernet.pdf
+ CONSTANT c_tse_pcs_byte_addr_w : NATURAL := c_tse_pcs_reg_addr_w + 2;
+ CONSTANT c_tse_pcs_data_w : NATURAL := c_halfword_w; -- = 16;
+
+ CONSTANT c_tse_empty_w : NATURAL := 2;
+ CONSTANT c_tse_tx_error_w : NATURAL := 1;
+ CONSTANT c_tse_rx_error_w : NATURAL := 6;
+ CONSTANT c_tse_error_w : NATURAL := largest(c_tse_tx_error_w, c_tse_rx_error_w);
+ CONSTANT c_tse_err_stat_w : NATURAL := 18;
+ CONSTANT c_tse_frm_type_w : NATURAL := 4;
+
+ CONSTANT c_tse_tx_fifo_depth : NATURAL := 256; -- nof words for Tx FIFO
+ CONSTANT c_tse_rx_fifo_depth : NATURAL := 256; -- nof words for Rx FIFO
+
+ CONSTANT c_tse_promis_en : BOOLEAN := FALSE;
+ --CONSTANT c_tse_promis_en : BOOLEAN := TRUE;
+
+ CONSTANT c_tx_data_type : NATURAL := 1; -- 0 = symbols, 1 = counter
+ CONSTANT c_tx_ready_latency : NATURAL := 0;
+ CONSTANT c_nof_tx_not_valid : NATURAL := 0; -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
+
+ CONSTANT c_eth_dst_mac : STD_LOGIC_VECTOR(47 DOWNTO 0) := X"10FA01020300";
+ CONSTANT c_eth_src_mac : STD_LOGIC_VECTOR(47 DOWNTO 0) := X"123456789ABC"; -- = 12-34-56-78-9A-BC
+ CONSTANT c_eth_ethertype : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"10FA";
+
+ TYPE t_mm_bus IS RECORD
+ -- Master In Slave Out
+ waitreq : STD_LOGIC;
+ rddata : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ -- Master Out Slave In
+ address : STD_LOGIC_VECTOR(c_tse_byte_addr_w-1 DOWNTO 0);
+ wrdata : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ wr : STD_LOGIC;
+ rd : STD_LOGIC;
+ END RECORD;
+
+ PROCEDURE proc_dbg_mm_bus(SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : IN t_mm_bus;
+ SIGNAL dbg_mm : OUT t_mm_bus) IS
+ BEGIN
+ dbg_mm.waitreq <= mm_miso.waitreq;
+ dbg_mm.rddata <= mm_miso.rddata;
+ dbg_mm.address <= mm_mosi.address;
+ dbg_mm.wrdata <= mm_mosi.wrdata;
+ dbg_mm.wr <= mm_mosi.wr;
+ dbg_mm.rd <= mm_mosi.rd;
+ END proc_dbg_mm_bus;
+
+ -- Wait for MM access (either read or write) finished
+ PROCEDURE proc_mm_access(SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_waitreq : IN STD_LOGIC;
+ SIGNAL mm_access : OUT STD_LOGIC) IS
+ BEGIN
+ mm_access <= '1';
+ WAIT UNTIL rising_edge(mm_clk);
+ WHILE mm_waitreq='1' LOOP
+ WAIT UNTIL rising_edge(mm_clk);
+ END LOOP;
+ mm_access <= '0';
+ END proc_mm_access;
+
+ -- Use word addressing for MAC registers according to table 4.8, 4.9
+ PROCEDURE proc_wr_mac(CONSTANT mac_addr : IN NATURAL;
+ CONSTANT mac_data : IN NATURAL;
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : OUT t_mm_bus) IS
+ BEGIN
+ mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(mac_addr, c_tse_byte_addr_w));
+ mm_mosi.wrdata <= STD_LOGIC_VECTOR(TO_UNSIGNED(mac_data, c_tse_data_w));
+ proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.wr);
+ END proc_wr_mac;
+
+ PROCEDURE proc_rd_mac(CONSTANT mac_addr : IN NATURAL;
+ SIGNAL mac_data : OUT NATURAL;
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : OUT t_mm_bus) IS
+ BEGIN
+ mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(mac_addr, c_tse_byte_addr_w));
+ proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.rd);
+ MAC_data <= TO_INTEGER(UNSIGNED(mm_miso.rddata));
+ END proc_rd_mac;
+
+ -- Use halfword addressing for PCS register to match table 4.17
+ PROCEDURE proc_wr_pcs(CONSTANT pcs_addr : IN NATURAL;
+ CONSTANT pcs_data : IN NATURAL;
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : OUT t_mm_bus) IS
+ BEGIN
+ mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(pcs_addr*2 + c_tse_byte_addr_pcs_offset, c_tse_byte_addr_w));
+ mm_mosi.wrdata <= (OTHERS=>'0');
+ mm_mosi.wrdata(c_tse_pcs_data_w-1 DOWNTO 0) <= STD_LOGIC_VECTOR(TO_UNSIGNED(pcs_data, c_tse_pcs_data_w));
+ proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.wr);
+ END proc_wr_pcs;
+
+ PROCEDURE proc_rd_pcs(CONSTANT pcs_addr : IN NATURAL;
+ SIGNAL pcs_data : OUT NATURAL;
+ SIGNAL mm_clk : IN STD_LOGIC;
+ SIGNAL mm_miso : IN t_mm_bus;
+ SIGNAL mm_mosi : OUT t_mm_bus) IS
+ BEGIN
+ mm_mosi.address <= STD_LOGIC_VECTOR(TO_UNSIGNED(pcs_addr*2 + c_tse_byte_addr_pcs_offset, c_tse_byte_addr_w));
+ proc_mm_access(mm_clk, mm_miso.waitreq, mm_mosi.rd);
+ pcs_data <= TO_INTEGER(UNSIGNED(mm_miso.rddata(c_tse_pcs_data_w-1 DOWNTO 0)));
+ END proc_rd_pcs;
+
+ TYPE t_tse_stream IS RECORD
+ -- Source In or Sink Out
+ ready : STD_LOGIC;
+ -- Source Out or Sink In
+ data : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ valid : STD_LOGIC;
+ sop : STD_LOGIC;
+ eop : STD_LOGIC;
+ empty : STD_LOGIC_VECTOR(c_tse_empty_w-1 DOWNTO 0);
+ err : STD_LOGIC_VECTOR(c_tse_error_w-1 DOWNTO 0);
+ END RECORD;
+
+ PROCEDURE proc_dbg_tse_stream_src(SIGNAL src_in : IN t_tse_stream;
+ SIGNAL src_out : IN t_tse_stream;
+ SIGNAL dbg_src : OUT t_tse_stream) IS
+ BEGIN
+ dbg_src.ready <= src_in.ready;
+ dbg_src.data <= src_out.data;
+ dbg_src.valid <= src_out.valid;
+ dbg_src.sop <= src_out.sop;
+ dbg_src.eop <= src_out.eop;
+ dbg_src.empty <= src_out.empty;
+ dbg_src.err <= src_out.err;
+ END proc_dbg_tse_stream_src;
+
+ PROCEDURE proc_dbg_tse_stream_snk(SIGNAL snk_in : IN t_tse_stream;
+ SIGNAL snk_out : IN t_tse_stream;
+ SIGNAL dbg_snk : OUT t_tse_stream) IS
+ BEGIN
+ dbg_snk.ready <= snk_out.ready;
+ dbg_snk.data <= snk_in.data;
+ dbg_snk.valid <= snk_in.valid;
+ dbg_snk.sop <= snk_in.sop;
+ dbg_snk.eop <= snk_in.eop;
+ dbg_snk.empty <= snk_in.empty;
+ dbg_snk.err <= snk_in.err;
+ END proc_dbg_tse_stream_snk;
+
+ -- Handle TX ready
+ -- Only support tx_ready_latency=0 or 1, corresponding to TX_ALMOST_FULL=3 or 4
+ -- Support for tx_ready_latency>1 requires keeping previous ready information
+ -- in a STD_LOGIC_VECTOR(tx_ready_latency-1 DOWNTO 0).
+ PROCEDURE proc_ready_latency(CONSTANT c_latency : IN NATURAL;
+ SIGNAL clk : IN STD_LOGIC;
+ SIGNAL ready : IN STD_LOGIC;
+ CONSTANT c_valid : IN STD_LOGIC;
+ CONSTANT c_sop : IN STD_LOGIC;
+ CONSTANT c_eop : IN STD_LOGIC;
+ SIGNAL out_valid : OUT STD_LOGIC;
+ SIGNAL out_sop : OUT STD_LOGIC;
+ SIGNAL out_eop : OUT STD_LOGIC) IS
+ BEGIN
+ IF c_latency=0 THEN
+ out_valid <= c_valid;
+ out_sop <= c_sop;
+ out_eop <= c_eop;
+ WAIT UNTIL rising_edge(clk);
+ WHILE ready /= '1' LOOP
+ WAIT UNTIL rising_edge(clk);
+ END LOOP;
+ END IF;
+ IF c_latency=1 THEN
+ WHILE ready /= '1' LOOP
+ out_valid <= '0';
+ out_sop <= '0';
+ out_eop <= '0';
+ WAIT UNTIL rising_edge(clk);
+ END LOOP;
+ out_valid <= c_valid;
+ out_sop <= c_sop;
+ out_eop <= c_eop;
+ WAIT UNTIL rising_edge(clk);
+ END IF;
+ END proc_ready_latency;
+
+ -- Transmit user packet
+ -- . Use word aligned payload data, so with half word inserted before the 14 byte header
+ -- . Packets can be send immediately after eachother so new sop directly after last eop
+ -- . The word rate is controlled by respecting ready from the MAC
+ PROCEDURE proc_tx_packet(CONSTANT dst_mac_addr : IN STD_LOGIC_VECTOR(c_eth_dst_mac'RANGE);
+ CONSTANT src_mac_addr : IN STD_LOGIC_VECTOR(c_eth_src_mac'RANGE);
+ CONSTANT ethertype : IN STD_LOGIC_VECTOR(c_eth_ethertype'RANGE);
+ CONSTANT data_len : IN NATURAL; -- in symbols = octets = bytes
+ SIGNAL dp_clk : IN STD_LOGIC;
+ SIGNAL dp_src_in : IN t_tse_stream;
+ SIGNAL dp_src_out : OUT t_tse_stream) IS
+ CONSTANT c_mod : NATURAL := data_len MOD c_tse_symbols_per_beat;
+ CONSTANT c_nof_data_beats : NATURAL := data_len / c_tse_symbols_per_beat + sel_a_b(c_mod, 1, 0);
+ CONSTANT c_empty : NATURAL := sel_a_b(c_mod, c_tse_symbols_per_beat - c_mod, 0);
+ VARIABLE v_sym : UNSIGNED(c_tse_symbol_w-1 DOWNTO 0) := (OTHERS=>'0');
+ VARIABLE v_num : UNSIGNED(c_tse_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ BEGIN
+ -- DST MAC
+ dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, c_tse_empty_w));
+ dp_src_out.data <= (OTHERS=>'0');
+ dp_src_out.data(15 DOWNTO 0) <= hton(dst_mac_addr(15 DOWNTO 0)); -- send to itself
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '1', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ dp_src_out.data <= hton(dst_mac_addr(47 DOWNTO 16));
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ -- SRC MAC
+ dp_src_out.data <= hton(src_mac_addr(31 DOWNTO 0));
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ -- SRC MAC & ETHERTYPE
+ dp_src_out.data <= hton(src_mac_addr(47 DOWNTO 32)) & hton(c_eth_ethertype);
+ -- DATA
+ FOR I IN 0 TO c_nof_data_beats-1 LOOP
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ IF c_tx_data_type=0 THEN
+ -- data : X"01020304", X"05060708", X"090A0B0C", etc
+ FOR J IN c_tse_symbols_per_beat-1 DOWNTO 0 LOOP
+ v_sym := v_sym + 1;
+ dp_src_out.data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) <= STD_LOGIC_VECTOR(v_sym);
+ END LOOP;
+ ELSE
+ -- data : X"00000001", X"00000002", X"00000003", etc
+ v_num := v_num + 1;
+ dp_src_out.data <= STD_LOGIC_VECTOR(v_num);
+ END IF;
+ -- tb : pull valid low for some time during the middle of the payload
+ IF c_nof_tx_not_valid > 0 AND I=c_nof_data_beats/2 THEN
+ dp_src_out.valid <= '0';
+ FOR I IN 0 TO c_nof_tx_not_valid LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+ dp_src_out.valid <= '1';
+ END IF;
+ END LOOP;
+ IF c_empty > 0 THEN
+ dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(c_empty, c_tse_empty_w));
+ FOR J IN c_empty-1 DOWNTO 0 LOOP
+ dp_src_out.data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) <= (OTHERS=>'0');
+ END LOOP;
+ END IF;
+ proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '1', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
+ dp_src_out.data <= (OTHERS=>'0');
+ dp_src_out.valid <= '0';
+ dp_src_out.eop <= '0';
+ dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, c_tse_empty_w));
+ END proc_tx_packet;
+
+ PROCEDURE proc_valid_sop(SIGNAL clk : IN STD_LOGIC;
+ SIGNAL in_valid : IN STD_LOGIC;
+ SIGNAL in_sop : IN STD_LOGIC) IS
+ BEGIN
+ WAIT UNTIL rising_edge(clk);
+ WHILE in_valid /= '1' AND in_sop /= '1' LOOP
+ WAIT UNTIL rising_edge(clk);
+ END LOOP;
+ END proc_valid_sop;
+
+ PROCEDURE proc_valid(SIGNAL clk : IN STD_LOGIC;
+ SIGNAL in_valid : IN STD_LOGIC) IS
+ BEGIN
+ WAIT UNTIL rising_edge(clk);
+ WHILE in_valid /= '1' LOOP
+ WAIT UNTIL rising_edge(clk);
+ END LOOP;
+ END proc_valid;
+
+ -- Receive packet
+ -- . Use word aligned payload data, so with half word inserted before the 14 byte header
+ -- . Packets can be always be received, assume the user application is always ready
+ -- . The CRC32 is also passed on to the user at eop.
+ -- . Note that when empty/=0 then the CRC32 is not word aligned, so therefore use prev_data to be able
+ -- to handle part of last data word in case empty/=0 at eop
+ PROCEDURE proc_rx_packet(CONSTANT dst_mac_addr : IN STD_LOGIC_VECTOR(c_eth_dst_mac'RANGE);
+ CONSTANT src_mac_addr : IN STD_LOGIC_VECTOR(c_eth_src_mac'RANGE);
+ CONSTANT ethertype : IN STD_LOGIC_VECTOR(c_eth_ethertype'RANGE);
+ SIGNAL dp_clk : IN STD_LOGIC;
+ SIGNAL dp_snk_in : IN t_tse_stream;
+ SIGNAL dp_snk_out : OUT t_tse_stream) IS
+ VARIABLE v_sym : UNSIGNED(c_tse_symbol_w-1 DOWNTO 0) := (OTHERS=>'0');
+ VARIABLE v_num : UNSIGNED(c_tse_data_w-1 DOWNTO 0) := (OTHERS=>'0');
+ VARIABLE v_empty : NATURAL;
+ VARIABLE v_first : BOOLEAN := TRUE;
+ VARIABLE v_data : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ VARIABLE v_prev_data : STD_LOGIC_VECTOR(c_tse_data_w-1 DOWNTO 0);
+ BEGIN
+ -- Keep ff_rx_snk_out.ready='1' all the time
+ dp_snk_out.ready <= '1';
+ -- Verify DST MAC
+ proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop);
+ ASSERT dp_snk_in.data(31 DOWNTO 16) = X"0000" REPORT "RX: Alignment half word not zero" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(15 DOWNTO 0) = hton(dst_mac_addr(15 DOWNTO 0)) REPORT "RX: Wrong dst_mac_addr(15 DOWNTO 0)" SEVERITY ERROR;
+ proc_valid(dp_clk, dp_snk_in.valid);
+ ASSERT dp_snk_in.data(31 DOWNTO 0) = hton(dst_mac_addr(47 DOWNTO 16)) REPORT "RX: Wrong dst_mac_addr(47 DOWNTO 16)" SEVERITY ERROR;
+ -- Verify SRC MAC
+ proc_valid(dp_clk, dp_snk_in.valid);
+ ASSERT dp_snk_in.data(31 DOWNTO 0) = hton(src_mac_addr(31 DOWNTO 0)) REPORT "RX: Wrong src_mac_addr(31 DOWNTO 0)" SEVERITY ERROR;
+ -- Verify SRC MAC & ETHERTYPE
+ proc_valid(dp_clk, dp_snk_in.valid);
+ ASSERT dp_snk_in.data(31 DOWNTO 16) = hton(src_mac_addr(47 DOWNTO 32)) REPORT "RX: Wrong src_mac_addr(47 DOWNTO 32)" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(15 DOWNTO 0) = hton(c_eth_ethertype) REPORT "RX: Wrong ethertype" SEVERITY ERROR;
+ -- Verify DATA
+ v_first := TRUE;
+ proc_valid(dp_clk, dp_snk_in.valid);
+ WHILE dp_snk_in.eop /= '1' LOOP
+ v_prev_data := v_data;
+ v_data := dp_snk_in.data;
+ IF v_first = FALSE THEN
+ IF c_tx_data_type=0 THEN
+ -- data : X"01020304", X"05060708", X"090A0B0C", etc
+ FOR J IN c_tse_symbols_per_beat-1 DOWNTO 0 LOOP
+ v_sym := v_sym + 1;
+ ASSERT UNSIGNED(v_prev_data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w)) = v_sym REPORT "RX: Wrong data symbol" SEVERITY ERROR;
+ END LOOP;
+ ELSE
+ -- data : X"00000001", X"00000002", X"00000003", etc
+ v_num := v_num + 1;
+ ASSERT UNSIGNED(v_prev_data) = v_num REPORT "RX: Wrong data word" SEVERITY ERROR;
+ END IF;
+ END IF;
+ v_first := FALSE;
+ proc_valid(dp_clk, dp_snk_in.valid);
+ END LOOP;
+ -- Verify last DATA and CRC32 if empty /=0 else the last word is only the CRC32
+ v_prev_data := v_data;
+ v_data := dp_snk_in.data;
+ v_empty := TO_INTEGER(UNSIGNED(dp_snk_in.empty));
+ IF v_empty > 0 THEN
+ FOR J IN v_empty-1 DOWNTO 0 LOOP
+ v_prev_data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) := (OTHERS=>'0');
+ END LOOP;
+ IF c_tx_data_type=0 THEN
+ -- data : X"01020304", X"05060708", X"090A0B0C", etc
+ FOR J IN c_tse_symbols_per_beat-1 DOWNTO v_empty LOOP -- ignore CRC32 symbols in last data word
+ v_sym := v_sym + 1;
+ ASSERT UNSIGNED(v_prev_data((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w)) = v_sym REPORT "RX: Wrong empty data symbol" SEVERITY ERROR;
+ END LOOP;
+ ELSE
+ -- data : X"00000001", X"00000002", X"00000003", etc
+ v_num := v_num + 1;
+ FOR J IN v_empty-1 DOWNTO 0 LOOP
+ v_num((J+1)*c_tse_symbol_w-1 DOWNTO J*c_tse_symbol_w) := (OTHERS=>'0'); -- force CRC32 symbols in last data word to 0
+ END LOOP;
+ ASSERT UNSIGNED(v_prev_data) = v_num REPORT "RX: Wrong empty data word" SEVERITY ERROR;
+ END IF;
+ ELSE
+ -- No verify on CRC32 word
+ END IF;
+ END proc_rx_packet;
+
+
+ -- Clocks and reset
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL sys_clk : STD_LOGIC := '0';
+ SIGNAL dp_clk : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+
+ -- TSE MAC control interface
+ SIGNAL mm_init : STD_LOGIC := '1';
+ SIGNAL mm_miso : t_mm_bus; -- master in slave out
+ SIGNAL mm_mosi : t_mm_bus; -- master out slave in
+
+ SIGNAL pcs_rddata : NATURAL; -- [c_tse_pcs_data_w-1:0]
+
+ SIGNAL tse_led_an : STD_LOGIC;
+ SIGNAL tse_led_link : STD_LOGIC;
+
+ -- TSE MAC transmit interface
+ -- . Avalon ST source
+ SIGNAL ff_tx_src_in : t_tse_stream;
+ SIGNAL ff_tx_src_out : t_tse_stream;
+ -- . MAC specific
+ SIGNAL ff_tx_crc_fwd : STD_LOGIC;
+ SIGNAL ff_tx_septy : STD_LOGIC;
+ SIGNAL ff_tx_a_full : STD_LOGIC;
+ SIGNAL ff_tx_a_empty : STD_LOGIC;
+ SIGNAL ff_tx_uflow : STD_LOGIC;
+
+ -- TSE MAC receive interface
+ -- . Avalon ST sink
+ SIGNAL ff_rx_snk_in : t_tse_stream;
+ SIGNAL ff_rx_snk_out : t_tse_stream;
+ -- . MAC specific
+ SIGNAL ff_rx_ethertype: STD_LOGIC_VECTOR(c_tse_err_stat_w-1 DOWNTO 0);
+ SIGNAL ff_rx_frm_type : STD_LOGIC_VECTOR(c_tse_frm_type_w-1 DOWNTO 0);
+ SIGNAL ff_rx_dsav : STD_LOGIC;
+ SIGNAL ff_rx_a_full : STD_LOGIC;
+ SIGNAL ff_rx_a_empty : STD_LOGIC;
+
+ -- TSE PHY interface
+ SIGNAL eth_txp : STD_LOGIC;
+ SIGNAL eth_rxp : STD_LOGIC;
+
+ -- Verification
+ SIGNAL tx_pkt_cnt : NATURAL := 0;
+ SIGNAL rx_pkt_cnt : NATURAL := 0;
+
+ -- Debug signals to combine valid in and out of records
+ SIGNAL dbg_mm : t_mm_bus;
+ SIGNAL dbg_ff_tx : t_tse_stream;
+ SIGNAL dbg_ff_rx : t_tse_stream;
+
+BEGIN
+
+ eth_clk <= NOT eth_clk AFTER eth_clk_period/2; -- TSE reference clock
+ sys_clk <= NOT sys_clk AFTER sys_clk_period/2; -- System clock
+
+ mm_clk <= sys_clk;
+ dp_clk <= sys_clk;
+
+ -- Debug signals to combine valid in and out of records
+ proc_dbg_mm_bus( mm_miso, mm_mosi, dbg_mm);
+ proc_dbg_tse_stream_src(ff_tx_src_in, ff_tx_src_out, dbg_ff_tx);
+ proc_dbg_tse_stream_snk(ff_rx_snk_in, ff_rx_snk_out, dbg_ff_rx);
+
+ -- run 1 us
+ p_mm_stimuli : PROCESS
+ BEGIN
+ mm_init <= '1';
+ mm_mosi.wr <= '0';
+ mm_mosi.rd <= '0';
+
+ -- reset release
+ mm_rst <= '1';
+ FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
+ mm_rst <= '0';
+ FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(mm_clk); END LOOP;
+
+ -- PSC control
+ proc_rd_pcs(16#22#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- REV --> 0x0901
+ proc_wr_pcs(16#28#, 16#0008#, mm_clk, mm_miso, mm_mosi); -- IF_MODE <-- Force 1GbE, no autonegatiation
+ proc_rd_pcs(16#00#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- CONTROL --> 0x1140
+ proc_rd_pcs(16#02#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- STATUS --> 0x000D
+ proc_wr_pcs(16#00#, 16#0140#, mm_clk, mm_miso, mm_mosi); -- CONTROL <-- Auto negotiate disable
+
+ -- MAC control
+ proc_rd_mac(16#000#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- REV --> CUST_VERSION & 0x0901
+ IF c_tse_promis_en=FALSE THEN
+ proc_wr_mac(16#008#, 16#0100004B#, mm_clk, mm_miso, mm_mosi);
+ ELSE
+ proc_wr_mac(16#008#, 16#0100005B#, mm_clk, mm_miso, mm_mosi);
+ END IF;
+ -- COMMAND_CONFIG <--
+ -- Only the bits relevant to UniBoard are explained here, others are 0
+ -- [ 0] = TX_ENA = 1, enable tx datapath
+ -- [ 1] = RX_ENA = 1, enable rx datapath
+ -- [ 2] = XON_GEN = 0
+ -- [ 3] = ETH_SPEED = 1, enable 1GbE operation
+ -- [ 4] = PROMIS_EN = 0, when 1 then receive all frames
+ -- [ 5] = PAD_EN = 0, when 1 enable receive padding removal (requires ethertype=payload length)
+ -- [ 6] = CRC_FWD = 1, enable receive CRC forward
+ -- [ 7] = PAUSE_FWD = 0
+ -- [ 8] = PAUSE_IGNORE = 0
+ -- [ 9] = TX_ADDR_INS = 0, when 1 then MAX overwrites tx SRC MAC with mac_0,1 or one of the supplemental mac
+ -- [ 10] = HD_ENA = 0
+ -- [ 11] = EXCESS_COL = 0
+ -- [ 12] = LATE_COL = 0
+ -- [ 13] = SW_RESET = 0, when 1 MAC disables tx and rx, clear statistics and flushes receive FIFO
+ -- [ 14] = MHAS_SEL = 0, select multicast address resolutions hash-code mode
+ -- [ 15] = LOOP_ENA = 0
+ -- [18-16] = TX_ADDR_SEL[2:0] = 000, TX_ADDR_INS insert mac_0,1 or one of the supplemental mac
+ -- [ 19] = MAGIC_EN = 0
+ -- [ 20] = SLEEP = 0
+ -- [ 21] = WAKEUP = 0
+ -- [ 22] = XOFF_GEN = 0
+ -- [ 23] = CNT_FRM_ENA = 0
+ -- [ 24] = NO_LGTH_CHECK = 1, when 0 then check payload length of received frames (requires ethertype=payload length)
+ -- [ 25] = ENA_10 = 0
+ -- [ 26] = RX_ERR_DISC = 0, when 1 then discard erroneous frames (requires store and forward mode, so rx_section_full=0)
+ -- when 0 then pass on with rx_err[0]=1
+ -- [ 27] = DISABLE_RD_TIMEOUT = 0
+ -- [30-28] = RSVD = 000
+ -- [ 31] = CNT_RESET = 0, when 1 clear statistics
+ proc_wr_mac(16#00C#, 16#56789ABC#, mm_clk, mm_miso, mm_mosi); -- MAC_0
+ proc_wr_mac(16#010#, 16#00001234#, mm_clk, mm_miso, mm_mosi); -- MAC_1 <-- SRC_MAC = 12-34-56-78-9A-BC
+ proc_wr_mac(16#05C#, 16#0000000C#, mm_clk, mm_miso, mm_mosi); -- TX_IPG_LENGTH <-- interpacket gap = 12
+ proc_wr_mac(16#014#, 16#000005EE#, mm_clk, mm_miso, mm_mosi); -- FRM_LENGTH <-- receive max frame length = 1518
+
+ -- FIFO legenda:
+ -- . Tx section full = There is enough data in the FIFO to start reading it, when 0 then store and forward.
+ -- . Rx section full = There is enough data in the FIFO to start reading it, when 0 then store and forward.
+ -- . Tx section empty = There is not much empty space anymore in the FIFO, warn user via ff_tx_septy
+ -- . Rx section empty = There is not much empty space anymore in the FIFO, inform remote device via XOFF flow control
+ -- . Tx almost full = Assert ff_tx_a_full and deassert ff_tx_rdy. Furthermore TX_ALMOST_FULL = c_tx_ready_latency+3,
+ -- so choose 3 for zero tx ready latency
+ -- . Rx almost full = Assert ff_rx_a_full and if the user is not ready ff_rx_rdy then:
+ -- --> break off the reception with an error to avoid FIFO overflow
+ -- . Tx almost empty = Assert ff_tx_a_empty and if the FIFO does not contain a eop yet then:
+ -- --> break off the transmission with an error to avoid FIFO underflow
+ -- . Rx almost empty = Assert ff_rx_a_empty
+ -- Typical FIFO values:
+ -- . TX_SECTION_FULL = 16 > 8 = TX_ALMOST_EMPTY
+ -- . RX_SECTION_FULL = 16 > 8 = RX_ALMOST_EMPTY
+ -- . TX_SECTION_EMPTY = D-16 < D-3 = Tx FIFO depth - TX_ALMOST_FULL
+ -- . RX_SECTION_EMPTY = D-16 < D-8 = Rx FIFO depth - RX_ALMOST_FULL
+ -- . c_tse_tx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Tx user respects ff_tx_rdy, to store a complete
+ -- ETH packet would require 1518 byte, so 2 M9K = 2k * 8b
+ -- . c_tse_rx_fifo_depth = 1 M9K = 256*32b = 1k * 8b is sufficient when the Rx user ff_rx_rdy is sufficiently active
+ proc_wr_mac(16#01C#, c_tse_rx_fifo_depth-16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_wr_mac(16#020#, 16, mm_clk, mm_miso, mm_mosi); -- RX_SECTION_FULL <-- default 16
+ proc_wr_mac(16#024#, c_tse_tx_fifo_depth-16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_EMPTY <-- default FIFO depth - 16, >3
+ proc_wr_mac(16#028#, 16, mm_clk, mm_miso, mm_mosi); -- TX_SECTION_FULL <-- default 16, >~ 8 otherwise no tx
+ proc_wr_mac(16#02C#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_EMPTY <-- default 8
+ proc_wr_mac(16#030#, 8, mm_clk, mm_miso, mm_mosi); -- RX_ALMOST_FULL <-- default 8
+ proc_wr_mac(16#034#, 8, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_EMPTY <-- default 8
+ proc_wr_mac(16#038#, c_tx_ready_latency+3, mm_clk, mm_miso, mm_mosi); -- TX_ALMOST_FULL <-- default 3
+
+ proc_rd_mac(16#0E8#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- TX_CMD_STAT --> 0x00040000 : [18]=1 TX_SHIFT16, [17]=0 OMIT_CRC
+ proc_rd_mac(16#0EC#, pcs_rddata, mm_clk, mm_miso, mm_mosi); -- RX_CMD_STAT --> 0x02000000 : [25]=1 RX_SHIFT16
+
+ WAIT UNTIL rising_edge(mm_clk);
+ mm_init <= '0';
+
+ WAIT;
+ END PROCESS;
+
+ p_tx_frame : PROCESS
+ BEGIN
+ -- . Avalon ST
+ ff_tx_src_out.data <= (OTHERS=>'0');
+ ff_tx_src_out.valid <= '0';
+ ff_tx_src_out.sop <= '0';
+ ff_tx_src_out.eop <= '0';
+ ff_tx_src_out.empty <= (OTHERS=>'0');
+ ff_tx_src_out.err <= (OTHERS=>'0');
+ -- . MAC specific
+ ff_tx_crc_fwd <= '0';
+
+ WHILE mm_init/='0' LOOP
+ WAIT UNTIL rising_edge(dp_clk);
+ END LOOP;
+ WHILE tse_led_link/='1' LOOP
+ WAIT UNTIL rising_edge(dp_clk);
+ END LOOP;
+ FOR I IN 0 TO 9 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, "0000000000010000", 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 16, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+ proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1499, dp_clk, ff_tx_src_in, ff_tx_src_out); -- verify st empty
+ proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
+
+ FOR I IN 0 TO 1500 * 2 LOOP WAIT UNTIL rising_edge(dp_clk); END LOOP;
+ tb_end <= '1';
+ WAIT;
+ END PROCESS;
+
+ p_rx_frame : PROCESS
+ BEGIN
+ -- . Avalon ST
+ ff_rx_snk_out.ready <= '0';
+
+ WHILE mm_init/='0' LOOP
+ WAIT UNTIL rising_edge(dp_clk);
+ END LOOP;
+
+ -- Receive forever
+ WHILE TRUE LOOP
+ proc_rx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, dp_clk, ff_rx_snk_in, ff_rx_snk_out);
+ END LOOP;
+
+ WAIT;
+ END PROCESS;
+
+ dut : ENTITY work.ip_arria10_e1sg_tse_sgmii_lvds
+ -- The ip_arria10_e1sg_tse_sgmii_lvds needs to be regenerated if its parameters are changed.
+ -- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
+ -- . ENABLE_SUP_ADDR = 0 : An extra MAC addresses can e.g. be used as service MAC for tests
+ -- . ENA_HASH = 0 : A multi cast hash table can be used to address all nodes at once
+ -- . STAT_CNT_ENA = 0 : PHY statistics counts are useful for monitoring, but not realy needed
+ -- . EG_FIFO = 256 : Tx FIFO depth in nof 32 bit words (256 --> 1 M9K)
+ -- . ING_FIFO = 256 : Rx FIFO depth in nof 32 bit words (256 --> 1 M9K)
+ PORT MAP (
+ -- MAC transmit interface
+ -- . Avalon ST
+ ff_tx_clk => dp_clk, -- : in std_logic := '0'; -- transmit_clock_connection.clk
+ ff_tx_rdy => ff_tx_src_in.ready, -- : out std_logic; -- .ready
+ ff_tx_data => ff_tx_src_out.data, -- : in std_logic_vector(31 downto 0) := (others => '0'); -- transmit.data
+ ff_tx_wren => ff_tx_src_out.valid, -- : in std_logic := '0'; -- .valid
+ ff_tx_sop => ff_tx_src_out.sop, -- : in std_logic := '0'; -- .startofpacket
+ ff_tx_eop => ff_tx_src_out.eop, -- : in std_logic := '0'; -- .endofpacket
+ ff_tx_mod => ff_tx_src_out.empty, -- : in std_logic_vector(1 downto 0) := (others => '0'); -- .empty
+ ff_tx_err => ff_tx_src_out.err(0), -- : in std_logic := '0'; -- .error
+ -- . MAC specific
+ ff_tx_crc_fwd => ff_tx_crc_fwd, -- : in std_logic := '0'; -- mac_misc_connection.ff_tx_crc_fwd -- when '0' MAC inserts CRC32 after eop
+ ff_tx_septy => ff_tx_septy, -- : out std_logic; -- .ff_tx_septy -- when '0' then tx FIFO goes above section-empty threshold
+ ff_tx_a_full => ff_tx_a_full, -- : out std_logic; -- .ff_tx_a_full -- when '1' then tx FIFO goes above almost-full threshold
+ ff_tx_a_empty => ff_tx_a_empty, -- : out std_logic; -- .ff_tx_a_empty -- when '1' then tx FIFO goes below almost-empty threshold
+ tx_ff_uflow => ff_tx_uflow, -- : out std_logic; -- .tx_ff_uflow -- when '1' then tx FIFO underflow
+ -- MAC receive interface
+ -- . Avalon STs
+ ff_rx_clk => dp_clk, -- : in std_logic := '0'; -- receive_clock_connection.clk
+ ff_rx_rdy => ff_rx_snk_out.ready, -- : in std_logic := '0'; -- .ready
+ ff_rx_data => ff_rx_snk_in.data, -- : out std_logic_vector(31 downto 0); -- receive.data
+ ff_rx_dval => ff_rx_snk_in.valid, -- : out std_logic; -- .valid
+ ff_rx_sop => ff_rx_snk_in.sop, -- : out std_logic; -- .startofpacket
+ ff_rx_eop => ff_rx_snk_in.eop, -- : out std_logic; -- .endofpacket
+ ff_rx_mod => ff_rx_snk_in.empty, -- : out std_logic_vector(1 downto 0); -- .empty
+ rx_err => ff_rx_snk_in.err, -- : out std_logic_vector(5 downto 0); -- .error
+ -- [5] collision error (can only occur in half duplex mode)
+ -- [4] PHY error on GMII
+ -- [3] receive frame truncated due to FIFO overflow
+ -- [2] CRC-32 error
+ -- [1] invalid length
+ -- [0] = OR of [1:5]
+ -- . MAC specific
+ rx_err_stat => ff_rx_ethertype, -- : out std_logic_vector(17 downto 0); -- .rx_err_stat -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+ rx_frm_type => ff_rx_frm_type, -- : out std_logic_vector(3 downto 0); -- .rx_frm_type -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+ ff_rx_dsav => ff_rx_dsav, -- : out std_logic; -- .ff_rx_dsav -- rx frame available, but not necessarily a complete frame
+ ff_rx_a_full => ff_rx_a_full, -- : out std_logic; -- .ff_rx_a_full -- when '1' then rx FIFO goes above almost-full threshold
+ ff_rx_a_empty => ff_rx_a_empty, -- : out std_logic; -- .ff_rx_a_empty -- when '1' sthen rx FIFO goes below almost-empty threshold
+ -- Reset
+ reset => mm_rst, -- : in std_logic := '0'; -- reset_connection.reset -- asynchronous reset (choose synchronous to mm_clk)
+ -- MM control interface
+ clk => mm_clk, -- : in std_logic := '0'; -- control_port_clock_connection.clk
+ reg_addr => mm_mosi.address(c_tse_byte_addr_w-1 DOWNTO 2), -- : in std_logic_vector(7 downto 0) := (others => '0'); -- .address
+ reg_data_out => mm_miso.rddata, -- : out std_logic_vector(31 downto 0); -- control_port.readdata
+ reg_rd => mm_mosi.rd, -- : in std_logic := '0'; -- .read
+ reg_data_in => mm_mosi.wrdata, -- : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ reg_wr => mm_mosi.wr, -- : in std_logic := '0'; -- .write
+ reg_busy => mm_miso.waitreq, -- : out std_logic; -- .waitrequest
+ -- Status LEDs
+ led_an => tse_led_an, -- : out std_logic; -- .an -- '1' = autonegation completed
+ led_link => tse_led_link, -- : out std_logic; -- .link -- '1' = successful link synchronisation
+ led_disp_err => OPEN, -- : out std_logic; -- .disp_err -- TBI character error
+ led_char_err => OPEN, -- : out std_logic; -- .char_err -- TBI disparity errorreceived
+ led_crs => OPEN, -- : out std_logic; -- status_led_connection.crs
+ led_col => OPEN, -- : out std_logic; -- .col
+ -- Serial 1.25 Gbps
+ rx_recovclkout => OPEN, -- : out std_logic; -- serdes_control_connection.export
+ ref_clk => eth_clk, -- : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk
+ txp => eth_txp, -- : out std_logic -- .txp_0
+ rxp => eth_rxp -- : in std_logic := '0'; -- serial_connection.rxp_0
+ );
+
+ -- Loopback
+ eth_rxp <= eth_txp;
+
+ -- Verification
+ tx_pkt_cnt <= tx_pkt_cnt + 1 WHEN ff_tx_src_out.sop='1' AND rising_edge(dp_clk);
+ rx_pkt_cnt <= rx_pkt_cnt + 1 WHEN ff_rx_snk_in.eop='1' AND rising_edge(dp_clk);
+
+ p_tb_end : PROCESS
+ BEGIN
+ WAIT UNTIL tb_end='1';
+
+ -- Verify that all transmitted packets have been received
+ IF tx_pkt_cnt=0 THEN
+ REPORT "No packets were transmitted." SEVERITY ERROR;
+ ELSIF rx_pkt_cnt=0 THEN
+ REPORT "No packets were received." SEVERITY ERROR;
+ ELSIF tx_pkt_cnt/=rx_pkt_cnt THEN
+ REPORT "Not all transmitted packets were received." SEVERITY ERROR;
+ END IF;
+
+ -- Stop the simulation
+ ASSERT FALSE REPORT "Simulation finished." SEVERITY FAILURE;
+ WAIT;
+ END PROCESS;
+
+END tb;
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh b/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh
new file mode 100755
index 0000000000000000000000000000000000000000..df1e1b6ff727ca0cd5c9bc91047f547d0ff2fb9b
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/generate_ip.sh
@@ -0,0 +1,44 @@
+#!/bin/bash
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# -------------------------------------------------------------------------- #
+#
+# Purpose: Generate IP with Qsys
+# Description:
+# Generate the IP in a separate generated/ subdirectory.
+#
+# Usage:
+#
+# ./generate_ip.sh
+#
+
+# Tool settings for selected target "unb2" with arria10
+. ${RADIOHDL}/tools/quartus/set_quartus unb2b
+
+#qsys-generate --help
+
+# Only generate the source IP
+# - use --synthesis=VHDL to have top level in VHDL similar as with MegaWizard
+qsys-generate ip_arria10_e1sg_voltage_sense.qsys \
+ --synthesis=VHDL \
+ --simulation=VHDL \
+ --output-directory=generated \
+ --allow-mixed-language-simulation
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..4cd22866aae4fe8db79559111d5f0bdd2728a66d
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
@@ -0,0 +1,19 @@
+hdl_lib_name = ip_arria10_e1sg_voltage_sense
+hdl_library_clause_name = ip_arria10_e1sg_voltage_sense_altera_voltage_sense_151
+hdl_lib_uses_synth =
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+
+test_bench_files =
+
+
+[modelsim_project_file]
+# There is no simulation model for the FPGA voltage sensor IP
+#modelsim_compile_ip_files =
+# $RADIOHDL/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files = generated/ip_arria10_e1sg_voltage_sense.qip
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/ip_arria10_e1sg_voltage_sense.qsys b/libraries/technology/ip_arria10_e1sg/voltage_sense/ip_arria10_e1sg_voltage_sense.qsys
new file mode 100644
index 0000000000000000000000000000000000000000..cf55c9c2b1b50c8eb2297fba11666bae428abf12
--- /dev/null
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/ip_arria10_e1sg_voltage_sense.qsys
@@ -0,0 +1,145 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="ip_arria10_e1sg_voltage_sense">
+ <component
+ name="$${FILENAME}"
+ displayName="$${FILENAME}"
+ version="1.0"
+ description=""
+ tags="INTERNAL_COMPONENT=true"
+ categories="System"
+ tool="QsysStandard" />
+ <parameter name="bonusData"><![CDATA[bonusData
+{
+ element voltage_sensor_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="10AX115S2F45E1SG" />
+ <parameter name="deviceFamily" value="Arria 10" />
+ <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>controller_csr</key>
+ <value>
+ <connectionPointName>controller_csr</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='controller_csr' start='0x0' end='0x8' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>3</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>sample_store_csr</key>
+ <value>
+ <connectionPointName>sample_store_csr</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='sample_store_csr' start='0x0' end='0x40' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>6</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></parameter>
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface name="clock" internal="voltage_sensor_0.clock" type="clock" dir="end">
+ <port name="clock_clk" internal="clock_clk" />
+ </interface>
+ <interface
+ name="controller_csr"
+ internal="voltage_sensor_0.controller_csr"
+ type="avalon"
+ dir="end">
+ <port name="controller_csr_address" internal="controller_csr_address" />
+ <port name="controller_csr_read" internal="controller_csr_read" />
+ <port name="controller_csr_readdata" internal="controller_csr_readdata" />
+ <port name="controller_csr_write" internal="controller_csr_write" />
+ <port name="controller_csr_writedata" internal="controller_csr_writedata" />
+ </interface>
+ <interface
+ name="reset_sink"
+ internal="voltage_sensor_0.reset_sink"
+ type="reset"
+ dir="end">
+ <port name="reset_sink_reset" internal="reset_sink_reset" />
+ </interface>
+ <interface
+ name="sample_store_csr"
+ internal="voltage_sensor_0.sample_store_csr"
+ type="avalon"
+ dir="end">
+ <port name="sample_store_csr_address" internal="sample_store_csr_address" />
+ <port name="sample_store_csr_read" internal="sample_store_csr_read" />
+ <port name="sample_store_csr_readdata" internal="sample_store_csr_readdata" />
+ <port name="sample_store_csr_write" internal="sample_store_csr_write" />
+ <port
+ name="sample_store_csr_writedata"
+ internal="sample_store_csr_writedata" />
+ </interface>
+ <interface
+ name="sample_store_irq"
+ internal="voltage_sensor_0.sample_store_irq"
+ type="interrupt"
+ dir="end">
+ <port name="sample_store_irq_irq" internal="sample_store_irq_irq" />
+ </interface>
+ <module
+ name="voltage_sensor_0"
+ kind="altera_voltage_sensor"
+ version="16.0"
+ enabled="1"
+ autoexport="1">
+ <parameter name="AUTO_DEVICE" value="10AX115S2F45E1SG" />
+ <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
+ <parameter name="CORE_VAR" value="0" />
+ <parameter name="MEM_TYPE" value="0" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>