Added in_data and si_data debug signals.

libraries/dsp/si/src/vhdl/si.vhd

@@ -60,8 +60,15 @@ ARCHITECTURE rtl OF si IS
   SIGNAL si_plus       : STD_LOGIC;
   SIGNAL si_sosi       : t_dp_sosi;
 
+  -- For view in Wave window
+  SIGNAL in_data       : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+  SIGNAL si_data       : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+
 BEGIN
 
+  in_data <= in_sosi.data(g_dat_w-1 DOWNTO 0);
+  si_data <= si_sosi.data(g_dat_w-1 DOWNTO 0);
+
   p_reg : PROCESS(rst, clk)
   BEGIN
     IF rst='1' THEN
@@ -85,7 +92,7 @@ BEGIN
   -- Use SI when enabled, else pass on input
   si_plus <= plus WHEN si_en = '1' ELSE '1';
 
-  si_data : PROCESS (si_plus, in_sosi)
+  p_si_data : PROCESS (si_plus, in_sosi)
   BEGIN
     si_sosi <= in_sosi;
     IF si_plus = '0' THEN