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Commit 4ac513b4 authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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10GbE settings

parent 807c7367
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boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
+ 3
− 5
View file @ 4ac513b4
......@@ -612,11 +612,6 @@ set_location_assignment PIN_A34 -to RING_1_TX[11]
set_location_assignment PIN_BA25 -to PMBUS_SC
set_location_assignment PIN_BD25 -to PMBUS_SD
set_location_assignment PIN_BD26 -to PMBUS_ALERT
......@@ -624,6 +619,9 @@ set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SC
set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_SD
set_instance_assignment -name IO_STANDARD "1.2 V" -to PMBUS_ALERT
set_location_assignment PIN_R14 -to BCK_SCL[0]
set_location_assignment PIN_Y13 -to BCK_SCL[1]
set_location_assignment PIN_U14 -to BCK_SCL[2]
......
boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+ 5
− 0
View file @ 4ac513b4
......@@ -61,8 +61,13 @@ set_location_assignment PIN_U13 -to ID[6]
set_location_assignment PIN_T13 -to ID[7]
set_location_assignment PIN_AU31 -to INTA
set_location_assignment PIN_AR30 -to INTB
set_location_assignment PIN_BC31 -to SENS_SC
set_location_assignment PIN_BB31 -to SENS_SD
set_location_assignment PIN_AN32 -to TESTIO[0]
set_location_assignment PIN_AP32 -to TESTIO[1]
set_location_assignment PIN_AT30 -to TESTIO[2]
......
boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+ 21
− 0
View file @ 4ac513b4
......@@ -83,6 +83,27 @@ set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
#set_location_assignment HSSIPMALCPLL_X0_Y88_N29 -to |unb2_test_10GbE|unb2_test:u_revision|unb2_board_10gbe:\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|pll_serial_clk_16g
#set_location_assignment FPLL_X0_Y120_N26 -to |unb2_test_10GbE|unb2_test:u_revision|ctrl_unb2_board:u_ctrl|unb2_board_clk200_pll:\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|tech_fractional_pll_clk200:\gen_st_fractional_pll:u_st_fractional_pll|ip_arria10_fractional_pll_clk200:\gen_ip_arria10:u0|altera_xcvr_fpll_a10:xcvr_fpll_a10_0|pll_avmmreaddata_cmu_fpll[0]
#set_location_assignment FPLL_X0_Y143_N26 -to |unb2_test_10GbE|unb2_test:u_revision|unb2_board_10gbe:\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tech_pll_xgmii_mac_clocks:u_unb2_board_clk644_pll|ip_arria10_pll_xgmii_mac_clocks:\gen_ip_arria10:u0|altera_xcvr_fpll_a10:xcvr_fpll_a10_0|pll_avmmreaddata_cmu_fpll[0]
#set_location_assignment HSSIPMALCPLL_X0_Y88_N29 -to \\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|pll_serial_clk_16g
#wrong set_location_assignment HSSIPMALCPLL_X0_Y65_N29 -to \\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|pll_serial_clk_16g
#set_location_assignment FPLL_X0_Y120_N26 -to \\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|tech_fractional_pll_clk200:\gen_st_fractional_pll:u_st_fractional_pll|ip_arria10_fractional_pll_clk200:\gen_ip_arria10:u0|altera_xcvr_fpll_a10:xcvr_fpll_a10_0|pll_avmmreaddata_cmu_fpll[0]
#set_location_assignment FPLL_X0_Y143_N26 -to \\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tech_pll_xgmii_mac_clocks:u_unb2_board_clk644_pll|ip_arria10_pll_xgmii_mac_clocks:\gen_ip_arria10:u0|altera_xcvr_fpll_a10:xcvr_fpll_a10_0|pll_avmmreaddata_cmu_fpll[0]
#
#set_location_assignment HSSIPMALCPLL_X0_Y65_N29 -to "\|unb2_test_10GbE|unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|pll_serial_clk_16g"
#set_parameter -name dbg_user_identifier 1 -to "\\Generate_XCVR_LANE_INSTANCES:1:xcvr_lane_inst|xcvr_txrx_inst|xcvr_native_a10_0"
#set_parameter -name dbg_user_identifier 0 -to "\\Generate_XCVR_LANE_INSTANCES:0:xcvr_lane_inst|xcvr_pll_inst|xcvr_atx_pll_a10_0"
#set_parameter -name dbg_user_identifier 1 -to "\\Generate_XCVR_LANE_INSTANCES:1:xcvr_lane_inst|xcvr_pll_inst|xcvr_atx_pll_a10_0"
set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_0|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_phy_10gbase_r_12:\\gen_phy_12:u_ip_arria10_phy_10gbase_r_12"
set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_1|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_phy_10gbase_r_12:\\gen_phy_12:u_ip_arria10_phy_10gbase_r_12"
set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_0|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0"
set_parameter -name dbg_user_identifier 1 -to "unb2_test:u_revision|unb2_board_10gbe:\\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|tr_10GbE:u_tr_10GbE_1|tech_eth_10g:u_tech_eth_10g|tech_eth_10g_arria10:\\gen_ip_arria10:u0|tech_10gbase_r:u_tech_10gbase_r|tech_10gbase_r_arria10:\\gen_ip_arria10:u0|ip_arria10_transceiver_pll_10g:u_ip_arria10_transceiver_pll_10g|altera_xcvr_atx_pll_a10:xcvr_atx_pll_a10_0"
# Pass compile stamps as generics (passed to top-level when $UNB_COMPILE_STAMPS is set)
if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
......
boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ 17
− 32
View file @ 4ac513b4
......@@ -22,58 +22,43 @@
set_time_format -unit ns -decimal_places 3
create_clock -name {CLK} -period 5.000 -waveform { 0.000 2.500 } [get_ports {CLK}]
create_clock -name {ETH_CLK} -period 8.000 -waveform { 0.000 4.000 } [get_ports {ETH_CLK}]
create_clock -period 125Mhz [get_ports {ETH_CLK}]
create_clock -period 200Mhz [get_ports {CLK}]
create_clock -period 100Mhz [get_ports {CLKUSR}]
create_clock -period 644.53125Mhz [get_ports {SA_CLK}]
create_clock -period 644.53125Mhz [get_ports {SB_CLK}]
create_clock -period 1.552 -name {BCK_REF_CLK} { BCK_REF_CLK }
derive_pll_clocks
derive_clock_uncertainty
# Effectively set false path from this clock to all other clocks
#set_clock_groups -asynchronous -group [get_clocks BCK_REF_CLK]
#set_clock_groups -asynchronous -group [get_clocks SB_CLK]
#set_clock_groups -asynchronous -group [get_clocks SA_CLK]
#set_clock_groups -asynchronous -group [get_clocks ETH_CLK]
#set_clock_groups -asynchronous -group [get_clocks CLK]
set_clock_groups -asynchronous -group [get_clocks {u_revision|u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
#set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_stream_MB_I:u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\gen_ip:gen_ip_arria10:u0|\gen_ip_arria10_ddr4_4g_1600:u_ip_arria10_ddr4_4g_1600|emif_0_core_usr_clk}]
#set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_stream_MB_I:u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\gen_ip:gen_ip_arria10:u0|\gen_ip_arria10_ddr4_4g_1600:u_ip_arria10_ddr4_4g_1600|emif_0_ref_clock}]
#set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_stream_MB_II:u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\gen_ip:gen_ip_arria10:u0|\gen_ip_arria10_ddr4_4g_1600:u_ip_arria10_ddr4_4g_1600|emif_0_core_usr_clk}]
#set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_stream_MB_II:u_mms_io_ddr_diag|u_mms_io_ddr|u_io_ddr|u_tech_ddr|\gen_ip:gen_ip_arria10:u0|\gen_ip_arria10_ddr4_4g_1600:u_ip_arria10_ddr4_4g_1600|emif_0_ref_clock}]
set_clock_groups -asynchronous -group {CLK}
set_clock_groups -asynchronous -group {ETH_CLK}
set_clock_groups -asynchronous -group {BCK_REF_CLK}
set_clock_groups -asynchronous -group {CLK_USR}
set_clock_groups -asynchronous -group {CLKUSR}
set_clock_groups -asynchronous -group {SA_CLK}
set_clock_groups -asynchronous -group {SB_CLK}
set_clock_groups -asynchronous -group [get_clocks pll_clk20]
set_clock_groups -asynchronous -group [get_clocks pll_clk50]
set_clock_groups -asynchronous -group [get_clocks pll_clk100]
set_clock_groups -asynchronous -group [get_clocks pll_clk125]
set_clock_groups -asynchronous -group [get_clocks pll_clk200]
set_clock_groups -asynchronous -group [get_clocks pll_clk200p]
set_clock_groups -asynchronous -group [get_clocks pll_clk400]
set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}]
set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_back|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}]
set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_back|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
#set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
#set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_unb2_board_clk644_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk1}]
set_clock_groups -asynchronous -group [get_clocks {u_revision|u_ctrl|\gen_mm_clk_hardware:u_unb2_board_clk125_pll|\gen_fractional_pll:u_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk3}]
set_clock_groups -asynchronous -group [get_clocks {u_revision|u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10:u0|xcvr_fpll_a10_0|outclk0}]
set_clock_groups -asynchronous -group [get_clocks {u_revision|\gen_udp_stream_10GbE:u_tr_10GbE_qsfp_and_ring|u_tr_10GbE_0|u_tech_eth_10g|\gen_ip_arria10:u0|u_tech_10gbase_r|\gen_ip_arria10:u0|\gen_phy_12:u_ip_arria10_phy_10gbase_r_12|xcvr_native_a10_0|g_xcvr_native_insts[*]|rx_pma_clk}]
set_clock_groups -asynchronous \
-group {CLKUSR} \
-group {SA_CLK} \
-group {SB_CLK} \
-group {altera_ts_clk}
#\
#-group [get_clocks {\Generate_XCVR_LANE_INSTANCES:?:xcvr_lane_inst|xcvr_txrx_inst|xcvr_native_a10_0|g_xcvr_native_insts[*]|tx_pma_clk }]\
#-group [get_clocks {\Generate_XCVR_LANE_INSTANCES:?:xcvr_lane_inst|xcvr_txrx_inst|xcvr_native_a10_0|g_xcvr_native_insts[*]|rx_pma_clk }]
#set_clock_groups -asynchronous \
#-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \
#-group [get_clocks {inst2|xcvr_pll_inst|xcvr_fpll_a10_0|tx_bonding_clocks[0]}]
#JTAG Signal Constraints
......
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