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Commit 4a75cb4f authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Finished skeleton (everything compiles OK in ModelSim).

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hdl_lib_name = arts_unb1_sc4 hdl_lib_name = arts_unb1_sc4
hdl_library_clause_name = arts_unb1_sc4_lib hdl_library_clause_name = arts_unb1_sc4_lib
hdl_lib_uses_synth = common dp mm diag bf tr_10GbE apertif unb1_board hdl_lib_uses_synth = common dp mm diag bf tr_10GbE apertif unb1_board arts_unb1_sc4_bg
hdl_lib_uses_sim = apertif_unb1_fn_bf_emu hdl_lib_uses_sim = apertif_unb1_fn_bf_emu
hdl_lib_technology = ip_stratixiv hdl_lib_technology = ip_stratixiv
synth_files = synth_files =
../../../apertif/designs/apertif_unb1_correlator/src/vhdl/node_apertif_unb1_correlator_mesh.vhd ../../../apertif/designs/apertif_unb1_correlator/src/vhdl/node_apertif_unb1_correlator_mesh.vhd
src/vhdl/arts_unb1_sc4_mm_master.vhd
src/vhdl/arts_unb1_sc4_input.vhd src/vhdl/arts_unb1_sc4_input.vhd
src/vhdl/arts_unb1_sc4_output.vhd
src/vhdl/arts_unb1_sc4_processing.vhd src/vhdl/arts_unb1_sc4_processing.vhd
src/vhdl/arts_unb1_sc4_mm_master.vhd
src/vhdl/arts_unb1_sc4.vhd src/vhdl/arts_unb1_sc4.vhd
test_bench_files = test_bench_files =
......
...@@ -44,6 +44,7 @@ LIBRARY unb1_board_lib; ...@@ -44,6 +44,7 @@ LIBRARY unb1_board_lib;
LIBRARY tr_10GbE_lib; LIBRARY tr_10GbE_lib;
LIBRARY apertif_lib; LIBRARY apertif_lib;
USE apertif_lib.apertif_udp_offload_pkg.ALL; USE apertif_lib.apertif_udp_offload_pkg.ALL;
LIBRARY arts_unb1_sc4_bg_lib;
ENTITY arts_unb1_sc4 IS ENTITY arts_unb1_sc4 IS
GENERIC ( GENERIC (
...@@ -107,7 +108,7 @@ ARCHITECTURE str OF arts_unb1_sc4 IS ...@@ -107,7 +108,7 @@ ARCHITECTURE str OF arts_unb1_sc4 IS
-- CONSTANT c_nof_polarizations : NATURAL := 2; -- CONSTANT c_nof_polarizations : NATURAL := 2;
CONSTANT c_nof_telescopes : NATURAL := 12; CONSTANT c_nof_telescopes : NATURAL := 12;
CONSTANT c_nof_tabs : NATURAL := 1; --FIXME First 1, then upgrade to 12 TABs CONSTANT c_nof_tabs : NATURAL := 1; --FIXME First 1, then upgrade to 12 TABs
CONSTANT c_nof_abs : NATURAL := c_nof_tabs+1; -- + 1 IAB CONSTANT c_nof_iabs : NATURAL := c_nof_tabs+1; -- + 1 IAB
-- CONSTANT c_channel_compl_dat_w : NATURAL := 8; -- CONSTANT c_channel_compl_dat_w : NATURAL := 8;
-- CONSTANT c_channel_dat_w : NATURAL := 2*c_channel_compl_dat_w; -- CONSTANT c_channel_dat_w : NATURAL := 2*c_channel_compl_dat_w;
-- CONSTANT c_nof_beamlets : NATURAL := 88; --88 beamlets per node, 704 in total -- CONSTANT c_nof_beamlets : NATURAL := 88; --88 beamlets per node, 704 in total
...@@ -115,14 +116,39 @@ ARCHITECTURE str OF arts_unb1_sc4 IS ...@@ -115,14 +116,39 @@ ARCHITECTURE str OF arts_unb1_sc4 IS
-- CONSTANT c_nof_timesamples_per_packet : NATURAL := 50; -- CONSTANT c_nof_timesamples_per_packet : NATURAL := 50;
-- CONSTANT c_nof_apertif_bf_units : NATURAL := 4; -- 4 bf_units per Apertif FN -- CONSTANT c_nof_apertif_bf_units : NATURAL := 4; -- 4 bf_units per Apertif FN
-------------------------------------------------------------------------------
-- Input
-------------------------------------------------------------------------------
SIGNAL arts_unb1_sc4_input_src_out_arr : t_dp_sosi_arr(c_nof_telescopes-1 DOWNTO 0);
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Beam Former -- Processing
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
SIGNAL arts_unb1_sc4_processing_snk_in_arr : t_dp_sosi_arr(c_nof_telescopes-1 DOWNTO 0); SIGNAL arts_unb1_sc4_processing_snk_in_arr : t_dp_sosi_arr(c_nof_telescopes-1 DOWNTO 0);
SIGNAL arts_unb1_sc4_processing_src_out_arr : t_dp_sosi_arr(c_nof_tabs-1 DOWNTO 0); SIGNAL arts_unb1_sc4_processing_src_out_arr : t_dp_sosi_arr(c_nof_tabs-1 DOWNTO 0);
-------------------------------------------------------------------------------
-- Output
-------------------------------------------------------------------------------
CONSTANT c_nof_10GbE_tx_streams : NATURAL := 1;
SIGNAL arts_unb1_sc4_output_snk_in_arr : t_dp_sosi_arr(c_nof_tabs-1 DOWNTO 0);
SIGNAL arts_unb1_sc4_output_src_out : t_dp_sosi;
SIGNAL arts_unb1_sc4_output_src_in : t_dp_siso := c_dp_siso_rdy;
SIGNAL reg_dp_xonoff_iquv_mosi : t_mem_mosi;
SIGNAL reg_dp_xonoff_iquv_miso : t_mem_miso;
SIGNAL reg_dp_offload_tx_iquv_hdr_dat_mosi : t_mem_mosi;
SIGNAL reg_dp_offload_tx_iquv_hdr_dat_miso : t_mem_miso;
SIGNAL reg_dp_xonoff_i_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_dp_xonoff_i_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL reg_dp_offload_tx_i_hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_dp_offload_tx_i_hdr_dat_miso : t_mem_miso := c_mem_miso_rst;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- ctrl_unb1_board -- ctrl_unb1_board
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -140,7 +166,7 @@ ARCHITECTURE str OF arts_unb1_sc4 IS ...@@ -140,7 +166,7 @@ ARCHITECTURE str OF arts_unb1_sc4 IS
SIGNAL sa_rst : STD_LOGIC; SIGNAL sa_rst : STD_LOGIC;
SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb1_board_nof_chip_w-1 DOWNTO 0); SIGNAL chip_id : STD_LOGIC_VECTOR(c_unb1_board_nof_chip_w-1 DOWNTO 0);
SIGNAL pout_wdi : STD_LOGIC; SIGNAL pout_wdi : STD_LOGIC;
SIGNAL pio_system_info_mosi : t_mem_mosi; SIGNAL pio_system_info_mosi : t_mem_mosi;
...@@ -178,18 +204,46 @@ ARCHITECTURE str OF arts_unb1_sc4 IS ...@@ -178,18 +204,46 @@ ARCHITECTURE str OF arts_unb1_sc4 IS
BEGIN BEGIN
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Input & reordering & stage -- Input & reordering stage
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
u_arts_unb1_sc4_input: ENTITY work.arts_unb1_sc4_input u_arts_unb1_sc4_input: ENTITY work.arts_unb1_sc4_input
GENERIC MAP ( GENERIC MAP (
g_sim => g_sim g_sim => g_sim
) )
PORT MAP ( PORT MAP (
mm_clk => mm_clk,
mm_rst => mm_rst,
dp_clk => dp_clk, dp_clk => dp_clk,
dp_rst => dp_rst, dp_rst => dp_rst,
dp_pps => dp_pps,
mm_clk => mm_clk, chip_id => chip_id,
mm_rst => mm_rst,
cal_rec_clk => cal_rec_clk,
SB_CLK => SB_CLK,
FN_BN_0_TX => FN_BN_0_TX,
FN_BN_0_RX => FN_BN_0_RX,
FN_BN_1_TX => FN_BN_1_TX,
FN_BN_1_RX => FN_BN_1_RX,
FN_BN_2_TX => FN_BN_2_TX,
FN_BN_2_RX => FN_BN_2_RX,
FN_BN_3_TX => FN_BN_3_TX,
FN_BN_3_RX => FN_BN_3_RX,
SA_CLK => SA_CLK,
SI_FN_0_TX => SI_FN_0_TX,
SI_FN_0_RX => SI_FN_0_RX,
SI_FN_1_TX => SI_FN_1_TX,
SI_FN_1_RX => SI_FN_1_RX,
SI_FN_2_TX => SI_FN_2_TX,
SI_FN_2_RX => SI_FN_2_RX,
SI_FN_0_CNTRL => SI_FN_0_CNTRL,
SI_FN_1_CNTRL => SI_FN_1_CNTRL,
SI_FN_2_CNTRL => SI_FN_2_CNTRL,
SI_FN_3_CNTRL => SI_FN_3_CNTRL,
SI_FN_RSTN => SI_FN_RSTN,
src_out_arr => arts_unb1_sc4_input_src_out_arr src_out_arr => arts_unb1_sc4_input_src_out_arr
); );
...@@ -217,9 +271,18 @@ BEGIN ...@@ -217,9 +271,18 @@ BEGIN
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Output reordering & packetizing stage -- Output reordering & packetizing stage
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
u_arts_unb1_sc4_output: ENTITY work.arts_unb1_sc4_output u_arts_unb1_sc4_output: ENTITY arts_unb1_sc4_bg_lib.arts_unb1_sc4_output
GENERIC MAP ( GENERIC MAP (
g_sim => g_sim g_sim => g_sim,
g_override_payload_data => FALSE,
g_nof_tabs => 12,
g_nof_compound_beams => 12,
g_nof_subbands_per_compound_beam => 24,
g_nof_stokes => 4,
g_nof_channels => 8,
g_nof_timesamples => 25000,
g_nof_bytes_per_iquv_packet => 8500,
g_nof_bytes_per_i_packet => 6250
) )
PORT MAP ( PORT MAP (
dp_clk => dp_clk, dp_clk => dp_clk,
...@@ -228,11 +291,25 @@ BEGIN ...@@ -228,11 +291,25 @@ BEGIN
mm_clk => mm_clk, mm_clk => mm_clk,
mm_rst => mm_rst, mm_rst => mm_rst,
snk_in_arr => arts_unb1_sc4_output_snk_in_arr reg_dp_offload_tx_iquv_hdr_dat_mosi => reg_dp_offload_tx_iquv_hdr_dat_mosi,
); reg_dp_offload_tx_iquv_hdr_dat_miso => reg_dp_offload_tx_iquv_hdr_dat_miso,
reg_dp_xonoff_iquv_mosi => reg_dp_xonoff_iquv_mosi,
reg_dp_xonoff_iquv_miso => reg_dp_xonoff_iquv_miso,
reg_dp_offload_tx_i_hdr_dat_mosi => reg_dp_offload_tx_i_hdr_dat_mosi,
reg_dp_offload_tx_i_hdr_dat_miso => reg_dp_offload_tx_i_hdr_dat_miso,
reg_dp_xonoff_i_mosi => reg_dp_xonoff_i_mosi,
reg_dp_xonoff_i_miso => reg_dp_xonoff_i_miso,
snk_in_arr => arts_unb1_sc4_output_snk_in_arr,
src_out => arts_unb1_sc4_output_src_out,
src_in => arts_unb1_sc4_output_src_in,
ID => ID
);
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- ctrl_unb1_board -- ctrl_unb1_board
...@@ -269,7 +346,7 @@ BEGIN ...@@ -269,7 +346,7 @@ BEGIN
dp_pps => dp_pps, dp_pps => dp_pps,
cal_rec_clk => cal_rec_clk, cal_rec_clk => cal_rec_clk,
this_chip_id => this_chip_id, this_chip_id => chip_id,
-- Toggle WDI -- Toggle WDI
pout_wdi => pout_wdi, pout_wdi => pout_wdi,
......
...@@ -74,29 +74,29 @@ ARCHITECTURE str OF arts_unb1_sc4_processing IS ...@@ -74,29 +74,29 @@ ARCHITECTURE str OF arts_unb1_sc4_processing IS
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- WPFB -- WPFB
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
CONSTANT c_use_prefilter : BOOLEAN := FALSE; -- CONSTANT c_use_prefilter : BOOLEAN := FALSE;
CONSTANT c_wpfb_wb_factor : NATURAL := 1; -- CONSTANT c_wpfb_wb_factor : NATURAL := 1;
CONSTANT c_wpfb_nof_wb_streams : NATURAL := g_nof_telescopes; -- CONSTANT c_wpfb_nof_wb_streams : NATURAL := g_nof_telescopes;
CONSTANT c_wpfb_nof_chan : NATURAL := g_nof_polarizations; -- CONSTANT c_wpfb_nof_chan : NATURAL := g_nof_polarizations;
CONSTANT c_wpfb_nof_points : NATURAL := c_nof_channels; -- CONSTANT c_wpfb_nof_points : NATURAL := c_nof_channels;
CONSTANT c_wpfb_nof_taps : NATURAL := 8; -- CONSTANT c_wpfb_nof_taps : NATURAL := 8;
CONSTANT c_wpfb_coef_w : NATURAL := 9; -- CONSTANT c_wpfb_coef_w : NATURAL := 9;
CONSTANT c_wpfb_in_backoff_w : natural := 0; -- CONSTANT c_wpfb_in_backoff_w : natural := 0;
CONSTANT c_wpfb_in_dat_w : NATURAL := g_input_data_w; -- CONSTANT c_wpfb_in_dat_w : NATURAL := g_input_data_w;
CONSTANT c_wpfb_fft_in_dat_w : NATURAL := g_input_data_w; -- CONSTANT c_wpfb_fft_in_dat_w : NATURAL := g_input_data_w;
CONSTANT c_wpfb_out_dat_w : NATURAL := 12; -- CONSTANT c_wpfb_out_dat_w : NATURAL := 12;
CONSTANT c_wpfb_out_dat_significant_w : NATURAL := sel_a_b(g_input_data_w = 6, 10, 12); -- CONSTANT c_wpfb_out_dat_significant_w : NATURAL := sel_a_b(g_input_data_w = 6, 10, 12);
CONSTANT c_wpfb_out_gain_w : NATURAL := 0; -- CONSTANT c_wpfb_out_gain_w : NATURAL := 0;
CONSTANT c_wpfb_use_separate : BOOLEAN := FALSE; -- CONSTANT c_wpfb_use_separate : BOOLEAN := FALSE;
CONSTANT c_wpfb_use_reorder : BOOLEAN := FALSE; -- CONSTANT c_wpfb_use_reorder : BOOLEAN := FALSE;
CONSTANT c_wpfb_use_fft_shift : BOOLEAN := FALSE; -- CONSTANT c_wpfb_use_fft_shift : BOOLEAN := FALSE;
--
CONSTANT c_wpfb : t_wpfb := (c_wpfb_wb_factor, c_wpfb_nof_points, c_wpfb_nof_chan, c_wpfb_nof_wb_streams, -- CONSTANT c_wpfb : t_wpfb := (c_wpfb_wb_factor, c_wpfb_nof_points, c_wpfb_nof_chan, c_wpfb_nof_wb_streams,
c_wpfb_nof_taps, c_wpfb_in_backoff_w, c_wpfb_in_dat_w, 16, c_wpfb_coef_w, -- c_wpfb_nof_taps, c_wpfb_in_backoff_w, c_wpfb_in_dat_w, 16, c_wpfb_coef_w,
c_wpfb_use_reorder, c_wpfb_use_fft_shift, c_wpfb_use_separate, c_wpfb_fft_in_dat_w, c_wpfb_out_dat_w, c_wpfb_out_gain_w, 18, 2, true, 56, 2, c_nof_blocks_per_sync, -- c_wpfb_use_reorder, c_wpfb_use_fft_shift, c_wpfb_use_separate, c_wpfb_fft_in_dat_w, c_wpfb_out_dat_w, c_wpfb_out_gain_w, 18, 2, true, 56, 2, c_nof_blocks_per_sync,
c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline); -- c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);
--
CONSTANT c_wpfb_coefs_file_prefix : STRING := "hex/chan_fil_coefs_wide1_p32_t8"; -- CONSTANT c_wpfb_coefs_file_prefix : STRING := "hex/chan_fil_coefs_wide1_p32_t8";
SIGNAL wpfb_snk_in_arr : t_dp_sosi_arr(g_nof_telescopes-1 DOWNTO 0); SIGNAL wpfb_snk_in_arr : t_dp_sosi_arr(g_nof_telescopes-1 DOWNTO 0);
SIGNAL wpfb_src_out_arr : t_dp_sosi_arr(g_nof_telescopes-1 DOWNTO 0); SIGNAL wpfb_src_out_arr : t_dp_sosi_arr(g_nof_telescopes-1 DOWNTO 0);
...@@ -118,6 +118,8 @@ ARCHITECTURE str OF arts_unb1_sc4_processing IS ...@@ -118,6 +118,8 @@ ARCHITECTURE str OF arts_unb1_sc4_processing IS
-- stat_data_w : POSITIVE; -- = 32 -- stat_data_w : POSITIVE; -- = 32
-- stat_data_sz : POSITIVE; -- = 2 -- stat_data_sz : POSITIVE; -- = 2
CONSTANT c_nof_bf_subbands : NATURAL := 240;
CONSTANT c_channel_dat_w : NATURAL := 8;
CONSTANT c_bf_bf : t_c_bf := (g_nof_telescopes, g_nof_telescopes, c_nof_bf_subbands, c_nof_bf_subbands, g_nof_tabs, c_channel_dat_w, 16, 1, 16, 1, 8, 32, 2); CONSTANT c_bf_bf : t_c_bf := (g_nof_telescopes, g_nof_telescopes, c_nof_bf_subbands, c_nof_bf_subbands, g_nof_tabs, c_channel_dat_w, 16, 1, 16, 1, 8, 32, 2);
CONSTANT c_bf_bf_weights_file_name : STRING := "hex/bf_weights"; CONSTANT c_bf_bf_weights_file_name : STRING := "hex/bf_weights";
...@@ -227,26 +229,26 @@ BEGIN ...@@ -227,26 +229,26 @@ BEGIN
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- TAB Beam former FIFO stage: BF module requires flow control -- TAB Beam former FIFO stage: BF module requires flow control
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
gen_dp_fifo_sc : FOR i IN 0 TO g_nof_telescopes-1 GENERATE -- gen_dp_fifo_sc : FOR i IN 0 TO g_nof_telescopes-1 GENERATE
u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc -- u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
GENERIC MAP( -- GENERIC MAP(
g_data_w => g_input_data_w, -- g_data_w => g_input_data_w,
g_bsn_w => 64, -- g_bsn_w => 64,
g_fifo_size => 30, -- g_fifo_size => 30,
g_use_bsn => TRUE, -- g_use_bsn => TRUE,
g_use_sync => TRUE, -- g_use_sync => TRUE,
g_use_ctrl => TRUE -- g_use_ctrl => TRUE
) -- )
PORT MAP ( -- PORT MAP (
rst => dp_rst, -- rst => dp_rst,
clk => dp_clk, -- clk => dp_clk,
--
snk_in => wpfb_src_out_arr(i), -- snk_in => wpfb_src_out_arr(i),
--
src_in => bf_src_out_arr(i), -- src_in => bf_src_out_arr(i),
src_out => bf_snk_in_arr(i) -- src_out => bf_snk_in_arr(i)
); -- );
END GENERATE; -- END GENERATE;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- TAB Beam Former -- TAB Beam Former
......
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