diff --git a/applications/arts/designs/arts_unb1_sc4/hdllib.cfg b/applications/arts/designs/arts_unb1_sc4/hdllib.cfg
index aa8c6c5781fb7874c6807b3aa1cf4689262246a9..fdd07905db2b99d336c1c909598fa38e74054a8a 100644
--- a/applications/arts/designs/arts_unb1_sc4/hdllib.cfg
+++ b/applications/arts/designs/arts_unb1_sc4/hdllib.cfg
@@ -1,15 +1,14 @@
hdl_lib_name = arts_unb1_sc4
hdl_library_clause_name = arts_unb1_sc4_lib
-hdl_lib_uses_synth = common dp mm diag bf tr_10GbE apertif unb1_board
+hdl_lib_uses_synth = common dp mm diag bf tr_10GbE apertif unb1_board arts_unb1_sc4_bg
hdl_lib_uses_sim = apertif_unb1_fn_bf_emu
hdl_lib_technology = ip_stratixiv
synth_files =
../../../apertif/designs/apertif_unb1_correlator/src/vhdl/node_apertif_unb1_correlator_mesh.vhd
- src/vhdl/arts_unb1_sc4_mm_master.vhd
src/vhdl/arts_unb1_sc4_input.vhd
- src/vhdl/arts_unb1_sc4_output.vhd
src/vhdl/arts_unb1_sc4_processing.vhd
+ src/vhdl/arts_unb1_sc4_mm_master.vhd
src/vhdl/arts_unb1_sc4.vhd
test_bench_files =
diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4.vhd
index de5916d9c000f4962b64cbbe96504ee016bb922c..a3b5489114b49f33a12dc68e5bcc38fa802e1b59 100644
--- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4.vhd
@@ -44,6 +44,7 @@ LIBRARY unb1_board_lib;
LIBRARY tr_10GbE_lib;
LIBRARY apertif_lib;
USE apertif_lib.apertif_udp_offload_pkg.ALL;
+LIBRARY arts_unb1_sc4_bg_lib;
ENTITY arts_unb1_sc4 IS
GENERIC (
@@ -107,7 +108,7 @@ ARCHITECTURE str OF arts_unb1_sc4 IS
-- CONSTANT c_nof_polarizations : NATURAL := 2;
CONSTANT c_nof_telescopes : NATURAL := 12;
CONSTANT c_nof_tabs : NATURAL := 1; --FIXME First 1, then upgrade to 12 TABs
- CONSTANT c_nof_abs : NATURAL := c_nof_tabs+1; -- + 1 IAB
+ CONSTANT c_nof_iabs : NATURAL := c_nof_tabs+1; -- + 1 IAB
-- CONSTANT c_channel_compl_dat_w : NATURAL := 8;
-- CONSTANT c_channel_dat_w : NATURAL := 2*c_channel_compl_dat_w;
-- CONSTANT c_nof_beamlets : NATURAL := 88; --88 beamlets per node, 704 in total
@@ -115,14 +116,39 @@ ARCHITECTURE str OF arts_unb1_sc4 IS
-- CONSTANT c_nof_timesamples_per_packet : NATURAL := 50;
-- CONSTANT c_nof_apertif_bf_units : NATURAL := 4; -- 4 bf_units per Apertif FN
-
+ -------------------------------------------------------------------------------
+ -- Input
+ -------------------------------------------------------------------------------
+ SIGNAL arts_unb1_sc4_input_src_out_arr : t_dp_sosi_arr(c_nof_telescopes-1 DOWNTO 0);
-------------------------------------------------------------------------------
- -- Beam Former
+ -- Processing
-------------------------------------------------------------------------------
SIGNAL arts_unb1_sc4_processing_snk_in_arr : t_dp_sosi_arr(c_nof_telescopes-1 DOWNTO 0);
SIGNAL arts_unb1_sc4_processing_src_out_arr : t_dp_sosi_arr(c_nof_tabs-1 DOWNTO 0);
+ -------------------------------------------------------------------------------
+ -- Output
+ -------------------------------------------------------------------------------
+ CONSTANT c_nof_10GbE_tx_streams : NATURAL := 1;
+
+ SIGNAL arts_unb1_sc4_output_snk_in_arr : t_dp_sosi_arr(c_nof_tabs-1 DOWNTO 0);
+
+ SIGNAL arts_unb1_sc4_output_src_out : t_dp_sosi;
+ SIGNAL arts_unb1_sc4_output_src_in : t_dp_siso := c_dp_siso_rdy;
+
+ SIGNAL reg_dp_xonoff_iquv_mosi : t_mem_mosi;
+ SIGNAL reg_dp_xonoff_iquv_miso : t_mem_miso;
+
+ SIGNAL reg_dp_offload_tx_iquv_hdr_dat_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_tx_iquv_hdr_dat_miso : t_mem_miso;
+
+ SIGNAL reg_dp_xonoff_i_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_dp_xonoff_i_miso : t_mem_miso := c_mem_miso_rst;
+
+ SIGNAL reg_dp_offload_tx_i_hdr_dat_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_dp_offload_tx_i_hdr_dat_miso : t_mem_miso := c_mem_miso_rst;
+
------------------------------------------------------------------------------
-- ctrl_unb1_board
-------------------------------------------------------------------------------
@@ -140,7 +166,7 @@ ARCHITECTURE str OF arts_unb1_sc4 IS
SIGNAL sa_rst : STD_LOGIC;
- SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb1_board_nof_chip_w-1 DOWNTO 0);
+ SIGNAL chip_id : STD_LOGIC_VECTOR(c_unb1_board_nof_chip_w-1 DOWNTO 0);
SIGNAL pout_wdi : STD_LOGIC;
SIGNAL pio_system_info_mosi : t_mem_mosi;
@@ -178,22 +204,50 @@ ARCHITECTURE str OF arts_unb1_sc4 IS
BEGIN
-----------------------------------------------------------------------------
- -- Input & reordering & stage
+ -- Input & reordering stage
-----------------------------------------------------------------------------
u_arts_unb1_sc4_input: ENTITY work.arts_unb1_sc4_input
GENERIC MAP (
g_sim => g_sim
)
PORT MAP (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
-
mm_clk => mm_clk,
mm_rst => mm_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
+ dp_pps => dp_pps,
+
+ chip_id => chip_id,
+
+ cal_rec_clk => cal_rec_clk,
+
+ SB_CLK => SB_CLK,
+ FN_BN_0_TX => FN_BN_0_TX,
+ FN_BN_0_RX => FN_BN_0_RX,
+ FN_BN_1_TX => FN_BN_1_TX,
+ FN_BN_1_RX => FN_BN_1_RX,
+ FN_BN_2_TX => FN_BN_2_TX,
+ FN_BN_2_RX => FN_BN_2_RX,
+ FN_BN_3_TX => FN_BN_3_TX,
+ FN_BN_3_RX => FN_BN_3_RX,
+
+ SA_CLK => SA_CLK,
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL,
+ SI_FN_RSTN => SI_FN_RSTN,
+
src_out_arr => arts_unb1_sc4_input_src_out_arr
);
-
+
-----------------------------------------------------------------------------
-- Processing stage
-----------------------------------------------------------------------------
@@ -217,23 +271,46 @@ BEGIN
-----------------------------------------------------------------------------
-- Output reordering & packetizing stage
-----------------------------------------------------------------------------
- u_arts_unb1_sc4_output: ENTITY work.arts_unb1_sc4_output
+ u_arts_unb1_sc4_output: ENTITY arts_unb1_sc4_bg_lib.arts_unb1_sc4_output
GENERIC MAP (
- g_sim => g_sim
+ g_sim => g_sim,
+ g_override_payload_data => FALSE,
+ g_nof_tabs => 12,
+ g_nof_compound_beams => 12,
+ g_nof_subbands_per_compound_beam => 24,
+ g_nof_stokes => 4,
+ g_nof_channels => 8,
+ g_nof_timesamples => 25000,
+ g_nof_bytes_per_iquv_packet => 8500,
+ g_nof_bytes_per_i_packet => 6250
)
PORT MAP (
- dp_clk => dp_clk,
- dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_rst => dp_rst,
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- snk_in_arr => arts_unb1_sc4_output_snk_in_arr
- );
-
+ reg_dp_offload_tx_iquv_hdr_dat_mosi => reg_dp_offload_tx_iquv_hdr_dat_mosi,
+ reg_dp_offload_tx_iquv_hdr_dat_miso => reg_dp_offload_tx_iquv_hdr_dat_miso,
+
+ reg_dp_xonoff_iquv_mosi => reg_dp_xonoff_iquv_mosi,
+ reg_dp_xonoff_iquv_miso => reg_dp_xonoff_iquv_miso,
+ reg_dp_offload_tx_i_hdr_dat_mosi => reg_dp_offload_tx_i_hdr_dat_mosi,
+ reg_dp_offload_tx_i_hdr_dat_miso => reg_dp_offload_tx_i_hdr_dat_miso,
+ reg_dp_xonoff_i_mosi => reg_dp_xonoff_i_mosi,
+ reg_dp_xonoff_i_miso => reg_dp_xonoff_i_miso,
+ snk_in_arr => arts_unb1_sc4_output_snk_in_arr,
+
+ src_out => arts_unb1_sc4_output_src_out,
+ src_in => arts_unb1_sc4_output_src_in,
+
+ ID => ID
+ );
+
-------------------------------------------------------------------------------
-- ctrl_unb1_board
-------------------------------------------------------------------------------
@@ -269,7 +346,7 @@ BEGIN
dp_pps => dp_pps,
cal_rec_clk => cal_rec_clk,
- this_chip_id => this_chip_id,
+ this_chip_id => chip_id,
-- Toggle WDI
pout_wdi => pout_wdi,
diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_input.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_input.vhd
index 6a9d33aef7aad8e3e265fc61bac0dd546a6becf4..404e23cc14d0d41ad361b18cd471f5ebbd0dbf45 100644
--- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_input.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_input.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------------------
--
--- Copyright (C) 2015
+-- Copyright (C) 2017
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
@@ -20,203 +20,268 @@
-------------------------------------------------------------------------------
-- Purpose:
--- . Wrapper containing dp_offload_tx and design-specific header fields
+-- . Input stage from 10GbE receivers to mesh output
-- Description:
--- .
+-- . TODO: This input stage has been taken from SC1.
+-- . We need to take into account the transposed input beamlets!
+-- . Output should be interleaved
-LIBRARY IEEE, common_lib, work, technology_lib, mm_lib, unb1_board_lib, dp_lib, tech_tse_lib;
+LIBRARY IEEE, common_lib, work, technology_lib, mm_lib, unb1_board_lib, dp_lib, tech_tse_lib, tr_10GbE_lib, apertif_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-USE common_lib.common_field_pkg.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
USE tech_tse_lib.tech_tse_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE apertif_lib.apertif_udp_offload_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
-ENTITY arts_unb1_sc4_output IS
+ENTITY arts_unb1_sc4_input IS
GENERIC (
- g_technology : NATURAL := c_tech_select_default;
- g_nof_streams : POSITIVE := 1;
- g_nof_blocks : NATURAL := 50;
- g_nof_channels : NATURAL := 24;
g_sim : BOOLEAN
);
PORT (
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
- dp_rst : IN STD_LOGIC;
- dp_clk : IN STD_LOGIC;
-
- reg_dp_offload_tx_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_offload_tx_hdr_dat_miso : OUT t_mem_miso := c_mem_miso_rst;
-
- reg_dp_xonoff_output_mosi : IN t_mem_mosi;
- reg_dp_xonoff_output_miso : OUT t_mem_miso;
-
- snk_in : IN t_dp_sosi;
- snk_out : OUT t_dp_siso;
-
- src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- src_in_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
-
- ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0)
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+ dp_pps : IN STD_LOGIC;
+
+ chip_id : STD_LOGIC_VECTOR(c_unb1_board_nof_chip_w-1 DOWNTO 0);
+
+ cal_rec_clk : STD_LOGIC;
+
+ -- Mesh Serial I/O
+ SB_CLK : IN STD_LOGIC; -- SerDes clock FN-BN (tr_mesh)
+ FN_BN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+
+ -- Serial I/O: 10GbE receivers
+ SA_CLK : IN STD_LOGIC; -- SerDes Clock BN-BI / SI_FN
+ SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_RSTN : OUT STD_LOGIC := '1';
+
+ src_out_arr : OUT t_dp_sosi_arr(12-1 DOWNTO 0)
);
-END arts_unb1_sc4_output;
-
-
-ARCHITECTURE wrap OF arts_unb1_sc4_output IS
-
- -- Word align + Eth + IP + UDP + ID + Flags
- CONSTANT c_nof_hdr_fields : NATURAL := 1 + 3 + 12 + 4 + 6 + 8 ; -- 34 fields
- -- Numer of bytes: 2 + <-----42-----> + 16 + 8*24/8 -- 2 + 42 + 40 = 84 bytes = 672 bits
-
- CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("word_align" ), " ", 16, field_default(0) ),
- ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(x"1418774428B8") ),
- ( field_name_pad("eth_src_mac" ), " ", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), " ", 16, field_default(x"800") ),
- ( field_name_pad("ip_version" ), " ", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), " ", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), " ", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), " ", 16, field_default(4868) ),
- ( field_name_pad("ip_identification" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), " ", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), " ", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), " ", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), " ", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("ip_src_addr" ), " ", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), " ", 32, field_default(x"0A63C82A") ),
- ( field_name_pad("udp_src_port" ), " ", 16, field_default(4000) ),
- ( field_name_pad("udp_dst_port" ), " ", 16, field_default(4000) ),
- ( field_name_pad("udp_total_length" ), " ", 16, field_default(4848) ),
- ( field_name_pad("udp_checksum" ), " ", 16, field_default(0) ),
- ( field_name_pad("id_marker_byte" ), " ", 8, field_default(65) ),
- ( field_name_pad("id_format_version" ), " ", 8, field_default(1) ),
- ( field_name_pad("id_source_id" ), " ", 16, field_default(0) ),
- ( field_name_pad("id_n_channels" ), " ", 16, field_default(0) ),
- ( field_name_pad("id_n_blocks" ), " ", 16, field_default(0) ),
- ( field_name_pad("id_timestamp" ), " ", 64, field_default(0) ),
- ( field_name_pad("flags_crc_error" ), " ", 24, field_default(0) ),
- ( field_name_pad("flags_no_input_present" ), " ", 24, field_default(0) ),
- ( field_name_pad("flags_uploading_weights" ), " ", 24, field_default(0) ),
- ( field_name_pad("flags_noise_source_enabled" ), " ", 24, field_default(0) ),
- ( field_name_pad("flags_telescope_pointing_off" ), " ", 24, field_default(0) ),
- ( field_name_pad("flags_antenna_broken" ), " ", 24, field_default(0) ),
- ( field_name_pad("flags_reserved_0" ), " ", 24, field_default(0) ),
- ( field_name_pad("flags_reserved_1" ), " ", 24, field_default(0) ) );
-
- CONSTANT c_hdr_field_sel : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1101" & -- Eth header fields: eth_src_mac from data path (others use MM default value).
- "111111111101" & -- IP header fields: ip_src_addr from data path (others use MM default value).
- "1111" & -- UDP header fields
- "110000" & -- ID header fields: MM controlled: marker byte, format version. From data path: source ID, n_channels, n_blocks and timestamp.
- "00111111"; -- Flag fields: crc_error and no_input_present from data path, others via MM.
-
- CONSTANT c_nof_hdr_words : NATURAL := field_slv_len(c_hdr_field_arr)/c_tech_tse_data_w;
- CONSTANT c_bsn_w : NATURAL := 64;
- CONSTANT c_nof_words_per_block : NATURAL := 24;
- CONSTANT c_nof_blocks_per_packet : NATURAL := 50;
- CONSTANT c_fifo_size : NATURAL := 4096;
-
- SIGNAL mms_dp_xonoff_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL mms_dp_xonoff_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
-
- SIGNAL dp_fifo_sc_snk_in_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL dp_fifo_sc_snk_out_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
-
- SIGNAL dp_fifo_sc_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL dp_fifo_sc_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
-
- SIGNAL dp_offload_tx_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL dp_offload_tx_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
-
- SIGNAL hdr_fields_in_arr : t_slv_1024_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL id_backplane : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
- SIGNAL id_chip : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0);
+END arts_unb1_sc4_input;
+
+
+ARCHITECTURE str OF arts_unb1_sc4_input IS
+
+ -------------------------------------------------------------------------------
+ -- ARTS SC4
+ -------------------------------------------------------------------------------
+ CONSTANT c_nof_polarizations : NATURAL := 2;
+ CONSTANT c_nof_telescopes : NATURAL := 12;
+ CONSTANT c_nof_apertif_bf_units : NATURAL := 4; -- 4 bf_units per Apertif FN
+ CONSTANT c_channel_compl_dat_w : NATURAL := 8;
+ CONSTANT c_channel_dat_w : NATURAL := 2*c_channel_compl_dat_w;
+ CONSTANT c_nof_beamlets : NATURAL := 88; --88 beamlets per node, 704 in total
+
+ -------------------------------------------------------------------------------
+ -- 10GbE input stage
+ -------------------------------------------------------------------------------
+ CONSTANT c_nof_10GbE_streams : NATURAL := 3; -- The number of 10G input streams
+
+ SIGNAL sa_rst : STD_LOGIC;
+ SIGNAL xaui_tx_arr : t_xaui_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL xaui_rx_arr : t_xaui_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL unb_xaui_tx_arr : t_unb1_board_xaui_sl_2arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL unb_xaui_rx_arr : t_unb1_board_xaui_sl_2arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL mdio_mdc_arr : STD_LOGIC_VECTOR(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL mdio_mdat_in_arr : STD_LOGIC_VECTOR(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL mdio_mdat_oen_arr : STD_LOGIC_VECTOR(c_nof_10GbE_streams-1 DOWNTO 0);
+
+ SIGNAL reg_tr_10gbe_mosi : t_mem_mosi;
+ SIGNAL reg_tr_10gbe_miso : t_mem_miso;
+ SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
+ SIGNAL reg_tr_xaui_miso : t_mem_miso;
+ SIGNAL reg_mdio_0_mosi : t_mem_mosi;
+ SIGNAL reg_mdio_0_miso : t_mem_miso;
+ SIGNAL reg_mdio_1_mosi : t_mem_mosi;
+ SIGNAL reg_mdio_1_miso : t_mem_miso;
+ SIGNAL reg_mdio_2_mosi : t_mem_mosi;
+ SIGNAL reg_mdio_2_miso : t_mem_miso;
+
+ SIGNAL reg_mdio_mosi_arr : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
+ SIGNAL reg_mdio_miso_arr : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
+
+ -- DP offload RX
+ SIGNAL dp_offload_rx_snk_in_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_snk_out_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_offload_rx_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=> c_dp_siso_rdy);
+ SIGNAL dp_offload_rx_restored_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0) := (OTHERS=> c_dp_sosi_rst);
+ SIGNAL hdr_fields_out_arr : t_slv_1024_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL reg_dp_offload_rx_hdr_dat_mosi : t_mem_mosi;
+ SIGNAL reg_dp_offload_rx_hdr_dat_miso : t_mem_miso;
+
+ -- BSN monitors
+ SIGNAL dp_bsn_monitor_input_in_sosi_arr : t_dp_sosi_arr(c_nof_10GbE_streams*2-1 DOWNTO 0);
+ SIGNAL dp_bsn_monitor_input_in_siso_arr : t_dp_siso_arr(c_nof_10GbE_streams*2-1 DOWNTO 0);
+
+ SIGNAL reg_dp_bsn_monitor_input_mosi : t_mem_mosi;
+ SIGNAL reg_dp_bsn_monitor_input_miso : t_mem_miso;
+ SIGNAL reg_dp_bsn_monitor_mesh_mosi : t_mem_mosi;
+ SIGNAL reg_dp_bsn_monitor_mesh_miso : t_mem_miso;
+
+ -- BSN Aligner + FIFOs
+ CONSTANT c_block_period : NATURAL := 186; -- FIXME Based on....?
+ CONSTANT c_block_size : NATURAL := 176;
+ CONSTANT c_bsn_align_latency : NATURAL := 3;
+ CONSTANT c_bsn_align_sop_timeout : NATURAL := (c_bsn_align_latency + 1) * c_block_period; -- wait somewhat more than c_bsn_align_latency periods
+ CONSTANT c_bsn_align_xoff_timeout : NATURAL := c_bsn_align_latency * 2 * c_block_period; -- flush factor 2 longer than needed
+ CONSTANT c_dp_fifo_size : NATURAL := (c_bsn_align_latency + 5) * c_block_size; -- be able to fit blocks for as long as sop time out;
+ CONSTANT c_dp_fifo_fill : NATURAL := c_block_size;
+
+ SIGNAL dp_fifo_fill_src_in_arr : t_dp_siso_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_fifo_fill_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_bsn_align_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL reg_dp_bsn_align_mesh_mosi : t_mem_mosi;
+ SIGNAL reg_dp_bsn_align_mesh_miso : t_mem_miso := c_mem_miso_rst;
+ SIGNAL reg_dp_bsn_align_input_mosi : t_mem_mosi;
+ SIGNAL reg_dp_bsn_align_input_miso : t_mem_miso := c_mem_miso_rst;
+
+ -------------------------------------------------------------------------------
+ -- Beamlet distribution & Mesh terminal preparation
+ -------------------------------------------------------------------------------
+ CONSTANT c_nof_nodes : NATURAL := 8;
+ SIGNAL dp_deinterleave_snk_in_2arr_4 : t_dp_sosi_2arr_4(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_deinterleave_src_out_3arr_4_2 : t_dp_sosi_3arr_4_2(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_deinterleave_src_out_2arr_8 : t_dp_sosi_2arr_8(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_deinterleave_src_out_2arr_3 : t_dp_sosi_2arr_3(c_nof_nodes-1 DOWNTO 0);
+ SIGNAL dp_deinterleave_src_out_arr : t_dp_sosi_arr(c_nof_nodes-1 DOWNTO 0);
+
+ SIGNAL dp_fifo_sc_0_src_out_2arr_8 : t_dp_sosi_2arr_8(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_fifo_sc_0_src_in_2arr_8 : t_dp_siso_2arr_8(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_repack_data_0_snk_in_2arr_8 : t_dp_sosi_2arr_8(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_repack_data_0_snk_out_2arr_8 : t_dp_siso_2arr_8(c_nof_10GbE_streams-1 DOWNTO 0);
+ SIGNAL dp_repack_data_0_src_out_2arr_8 : t_dp_sosi_2arr_8(c_nof_10GbE_streams-1 DOWNTO 0);
+
+ -------------------------------------------------------------------------------
+ -- Mesh Terminals
+ -------------------------------------------------------------------------------
+ SIGNAL node_apertif_unb1_correlator_mesh_snk_in_arr : t_dp_sosi_arr(c_nof_nodes-1 DOWNTO 0);
+ SIGNAL node_apertif_unb1_correlator_mesh_src_out_arr : t_dp_sosi_arr(c_nof_nodes-1 DOWNTO 0);
+ SIGNAL node_apertif_unb1_correlator_mesh_src_out_2arr_12 : t_dp_sosi_2arr_12(c_nof_polarizations-1 DOWNTO 0);
BEGIN
- ---------------------------------------------------------------------------------------
- -- Swap the bytes in the 32b words to make them little-endian
- ---------------------------------------------------------------------------------------
- p_connect : PROCESS(snk_in)
- BEGIN
- -- Control
- mms_dp_xonoff_snk_in_arr(0) <= snk_in;
- -- Data: re&im concatenated so real part is put on the line first: re,im,re,im, ..
- mms_dp_xonoff_snk_in_arr(0).data( c_byte_w-1 DOWNTO 0) <= snk_in.data(4*c_byte_w-1 DOWNTO 3*c_byte_w);
- mms_dp_xonoff_snk_in_arr(0).data(2*c_byte_w-1 DOWNTO c_byte_w) <= snk_in.data(3*c_byte_w-1 DOWNTO 2*c_byte_w);
- mms_dp_xonoff_snk_in_arr(0).data(3*c_byte_w-1 DOWNTO 2*c_byte_w) <= snk_in.data(2*c_byte_w-1 DOWNTO c_byte_w);
- mms_dp_xonoff_snk_in_arr(0).data(4*c_byte_w-1 DOWNTO 3*c_byte_w) <= snk_in.data( c_byte_w-1 DOWNTO 0);
- END PROCESS;
-
-----------------------------------------------------------------------------
- -- DP Xon Off. --> output to the GPU machine(s) can be switched on or off.
+ -- Interface : 10GbE
-----------------------------------------------------------------------------
- u_mms_dp_xonoff : ENTITY dp_lib.mms_dp_xonoff
- GENERIC MAP(
- g_nof_streams => 1,
- g_combine_streams => TRUE,
- g_bypass => FALSE,
- g_default_value => sel_a_b(g_sim, '1', '0') -- Sim: on by default like block gens
+ -- Wire together different types
+ gen_wires: FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ unb_xaui_tx_arr(i) <= xaui_tx_arr(i);
+ xaui_rx_arr(i) <= unb_xaui_rx_arr(i);
+ END GENERATE;
+
+ u_front_io : ENTITY unb1_board_lib.unb1_board_front_io
+ GENERIC MAP (
+ g_nof_xaui => c_nof_10GbE_streams
)
- PORT MAP(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- reg_mosi => reg_dp_xonoff_output_mosi,
- reg_miso => reg_dp_xonoff_output_miso,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
-
- snk_out_arr => mms_dp_xonoff_snk_out_arr,
- snk_in_arr => mms_dp_xonoff_snk_in_arr,
-
- src_in_arr => dp_fifo_sc_snk_out_arr,
- src_out_arr => dp_fifo_sc_snk_in_arr
+ PORT MAP (
+ xaui_tx_arr => unb_xaui_tx_arr,
+ xaui_rx_arr => unb_xaui_rx_arr,
+
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr,
+
+ SI_FN_0_TX => SI_FN_0_TX,
+ SI_FN_0_RX => SI_FN_0_RX,
+ SI_FN_1_TX => SI_FN_1_TX,
+ SI_FN_1_RX => SI_FN_1_RX,
+ SI_FN_2_TX => SI_FN_2_TX,
+ SI_FN_2_RX => SI_FN_2_RX,
+
+ SI_FN_0_CNTRL => SI_FN_0_CNTRL,
+ SI_FN_1_CNTRL => SI_FN_1_CNTRL,
+ SI_FN_2_CNTRL => SI_FN_2_CNTRL,
+ SI_FN_3_CNTRL => SI_FN_3_CNTRL
);
-
- ---------------------------------------------------------------------------------------
- -- FIFO
- ---------------------------------------------------------------------------------------
- u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
+
+ u_areset_sa_rst : ENTITY common_lib.common_areset
GENERIC MAP(
- g_technology => g_technology,
- g_data_w => c_tech_tse_data_w,
- g_bsn_w => c_bsn_w,
- g_fifo_size => c_fifo_size,
- g_use_bsn => TRUE,
- g_use_sync => TRUE, --Used to realign to 50 timesample grid in dp_offload_tx
- g_use_ctrl => TRUE
+ g_rst_level => '1',
+ g_delay_len => 4
)
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_out => dp_fifo_sc_snk_out_arr(0),
- snk_in => dp_fifo_sc_snk_in_arr(0),
-
- src_in => dp_fifo_sc_src_in_arr(0),
- src_out => dp_fifo_sc_src_out_arr(0)
+ PORT MAP(
+ clk => SA_CLK,
+ in_rst => '0',
+ out_rst => sa_rst
+ );
+
+ u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_macs => c_nof_10GbE_streams,
+ g_use_mdio => TRUE
+ )
+
+ PORT MAP (
+ tr_ref_clk_156 => SA_CLK,
+ tr_ref_rst_156 => sa_rst,
+
+ cal_rec_clk => mm_clk,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mac_mosi => reg_tr_10GbE_mosi,
+ reg_mac_miso => reg_tr_10GbE_miso,
+
+ xaui_mosi => reg_tr_xaui_mosi,
+ xaui_miso => reg_tr_xaui_miso,
+
+ mdio_mosi_arr => reg_mdio_mosi_arr(c_nof_10GbE_streams-1 DOWNTO 0),
+ mdio_miso_arr => reg_mdio_miso_arr(c_nof_10GbE_streams-1 DOWNTO 0),
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ src_out_arr => dp_offload_rx_snk_in_arr,
+ src_in_arr => dp_offload_rx_snk_out_arr,
+
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr,
+
+ mdio_rst => SI_FN_RSTN,
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr
);
-
- ---------------------------------------------------------------------------------------
- -- dp_offload_tx
- ---------------------------------------------------------------------------------------
- u_dp_offload_tx : ENTITY dp_lib.dp_offload_tx
+
+ -----------------------------------------------------------------------------
+ -- RX: dp_offload_rx
+ -----------------------------------------------------------------------------
+ u_dp_offload_rx : ENTITY dp_lib.dp_offload_rx
GENERIC MAP (
- g_technology => g_technology,
- g_nof_streams => g_nof_streams,
- g_data_w => c_tech_tse_data_w,
- g_use_complex => FALSE,
- g_nof_words_per_block => c_nof_words_per_block,
- g_nof_blocks_per_packet => c_nof_blocks_per_packet,
- g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_sel,
- g_pkt_merge_align_at_sync => TRUE -- Maintain 50 timesample grid during packet merging
+ g_nof_streams => c_nof_10GbE_streams,
+ g_data_w => c_xgmii_data_w,
+ g_hdr_field_arr => c_apertif_udp_offload_hdr_field_arr,
+ g_remove_crc => FALSE,
+ g_crc_nof_words => 0
)
PORT MAP (
mm_rst => mm_rst,
@@ -224,41 +289,285 @@ BEGIN
dp_rst => dp_rst,
dp_clk => dp_clk,
+
+ reg_hdr_dat_mosi => reg_dp_offload_rx_hdr_dat_mosi,
+ reg_hdr_dat_miso => reg_dp_offload_rx_hdr_dat_miso,
+
+ snk_in_arr => dp_offload_rx_snk_in_arr,
+ snk_out_arr => dp_offload_rx_snk_out_arr,
+
+ src_out_arr => dp_offload_rx_src_out_arr,
+ src_in_arr => (OTHERS=>c_dp_siso_rdy), --dp_offload_rx_src_in_arr,
+
+ hdr_fields_out_arr => hdr_fields_out_arr
+ );
+
+ gen_restore_bf_out_i : FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ dp_offload_rx_restored_src_out_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_sync") DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_sync" )));
+ dp_offload_rx_restored_src_out_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" ) DOWNTO field_lo(c_apertif_udp_offload_hdr_field_arr, "dp_bsn" )), c_dp_stream_bsn_w);
+
+ dp_offload_rx_restored_src_out_arr(i).re <= dp_offload_rx_src_out_arr(i).re;
+ dp_offload_rx_restored_src_out_arr(i).im <= dp_offload_rx_src_out_arr(i).im;
+ dp_offload_rx_restored_src_out_arr(i).valid <= dp_offload_rx_src_out_arr(i).valid;
+ dp_offload_rx_restored_src_out_arr(i).sop <= dp_offload_rx_src_out_arr(i).sop;
+ dp_offload_rx_restored_src_out_arr(i).eop <= dp_offload_rx_src_out_arr(i).eop;
+ dp_offload_rx_restored_src_out_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
+ END GENERATE;
- reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi,
- reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso,
-
- snk_in_arr => dp_fifo_sc_src_out_arr,
- snk_out_arr => dp_fifo_sc_src_in_arr,
+ -----------------------------------------------------------------------------
+ -- RX: BSN monitors
+ -----------------------------------------------------------------------------
+ dp_bsn_monitor_input_in_sosi_arr(2 DOWNTO 0) <= dp_offload_rx_restored_src_out_arr; --Un-aligned, non-flow controlled input streams
+ dp_bsn_monitor_input_in_siso_arr(2 DOWNTO 0) <= (OTHERS=>c_dp_siso_rdy);
- src_out_arr => dp_offload_tx_src_out_arr,
- src_in_arr => dp_offload_tx_src_in_arr,
+ dp_bsn_monitor_input_in_sosi_arr(5 DOWNTO 3) <= dp_bsn_align_src_out_arr; --BSN aligned streams
+ dp_bsn_monitor_input_in_siso_arr(5 DOWNTO 3) <= dp_fifo_fill_src_in_arr;
- hdr_fields_in_arr => hdr_fields_in_arr
+ u_dp_bsn_monitor_input : ENTITY dp_lib.mms_dp_bsn_monitor
+ GENERIC MAP (
+ g_nof_streams => c_nof_10GbE_streams*2,
+ g_sync_timeout => 225280000, --200000000*1.024*1.1 (1.1 = margin)
+ g_log_first_bsn => FALSE
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ reg_mosi => reg_dp_bsn_monitor_input_mosi,
+ reg_miso => reg_dp_bsn_monitor_input_miso,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ sync_in => dp_pps,
+ in_siso_arr => dp_bsn_monitor_input_in_siso_arr,
+ in_sosi_arr => dp_bsn_monitor_input_in_sosi_arr
);
+
+ -----------------------------------------------------------------------------
+ -- RX: BSN alignment
+ -----------------------------------------------------------------------------
+ gen_dp_fifo_fill: FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ u_dp_fifo_fill : ENTITY dp_lib.dp_fifo_fill
+ GENERIC MAP (
+ g_data_w => c_xgmii_data_w,
+ g_bsn_w => c_dp_stream_bsn_w,
+ g_channel_w => c_dp_stream_channel_w,
+ g_use_bsn => TRUE,
+ g_use_channel => TRUE,
+ g_use_error => TRUE,
+ g_use_sync => TRUE,
+ g_use_complex => TRUE,
+ g_fifo_fill => c_dp_fifo_fill,
+ g_fifo_size => c_dp_fifo_size
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_out => dp_offload_rx_src_in_arr(i),
+ snk_in => dp_offload_rx_restored_src_out_arr(i),
+
+ src_in => dp_fifo_fill_src_in_arr(i),
+ src_out => dp_fifo_fill_src_out_arr(i)
+ );
+ END GENERATE;
+
+ u_mms_dp_bsn_align : ENTITY dp_lib.mms_dp_bsn_align
+ GENERIC MAP (
+ g_block_size => c_block_size,
+ g_block_period => c_block_period,
+ g_nof_input => c_nof_10GbE_streams,
+ g_xoff_timeout => c_bsn_align_xoff_timeout,
+ g_sop_timeout => c_bsn_align_sop_timeout,
+ g_bsn_latency => c_bsn_align_latency,
+ g_bsn_request_pipeline => 2
+ )
+ PORT MAP (
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ snk_out_arr => dp_fifo_fill_src_in_arr,
+ snk_in_arr => dp_fifo_fill_src_out_arr,
+
+ src_in_arr => (OTHERS=>c_dp_siso_rdy),
+ src_out_arr => dp_bsn_align_src_out_arr,
+
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ reg_mosi => reg_dp_bsn_align_input_mosi,
+ reg_miso => reg_dp_bsn_align_input_miso
+ );
+
+ -------------------------------------------------------------------------------
+ -- Extract the 4 bf_unit substreams from each 10GbE input stream
+ -- . 3 64b streams -> 3*4 16b streams
+ -- . Incoming beamlets (same for each of the 3 10GbE inputs): 3 inputs*704 beamlets/FPGA
+ -- . 10GbE 64b word index ) [0],[1], ..[175]
+ -- . BF Stream 0 ) 0, 1 , .. 175
+ -- . BF Stream 1 ) 256,257 , .. 431
+ -- . BF Stream 2 ) 512,513 , .. 687
+ -- . BF Stream 3 ) 768,769 , .. 943
+ -------------------------------------------------------------------------------
+ gen_dp_stream_deconcat : FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ dp_deinterleave_snk_in_2arr_4(i) <= func_dp_stream_deconcat(dp_bsn_align_src_out_arr(i), c_nof_apertif_bf_units, c_channel_dat_w);
+ END GENERATE;
- src_out_arr <= dp_offload_tx_src_out_arr;
- dp_offload_tx_src_in_arr <= src_in_arr;
-
- ---------------------------------------------------------------------------------------
- -- Extract the backplane number from ID
- ---------------------------------------------------------------------------------------
- id_backplane <= RESIZE_UVEC(ID(7 DOWNTO 3), c_byte_w);
- id_chip <= RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w);
-
- ---------------------------------------------------------------------------------------
- -- Assign DP record fields and ID to header fields
- ---------------------------------------------------------------------------------------
- gen_slv_hard_fields : FOR i IN 0 TO g_nof_streams-1 GENERATE
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_src_mac" )) <= x"00228608" & id_backplane & id_chip;
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_src_port" ) DOWNTO field_lo(c_hdr_field_arr, "udp_src_port" )) <= x"D0" & ID;
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_dst_port" ) DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port" )) <= x"D0" & ID;
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_src_addr" )) <= x"0A63" & id_backplane & INCR_UVEC(id_chip, 1);
-
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_source_id" ) DOWNTO field_lo(c_hdr_field_arr, "id_source_id" )) <= x"00" & id_backplane;
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_n_channels" ) DOWNTO field_lo(c_hdr_field_arr, "id_n_channels" )) <= TO_UVEC(g_nof_channels, c_halfword_w);
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_n_blocks" ) DOWNTO field_lo(c_hdr_field_arr, "id_n_blocks" )) <= TO_UVEC(g_nof_blocks, c_halfword_w);
- hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_timestamp" ) DOWNTO field_lo(c_hdr_field_arr, "id_timestamp" )) <= dp_fifo_sc_src_out_arr(0).bsn;
+ -------------------------------------------------------------------------------
+ -- Deinterleave 3*4 into 3*4*2
+ -------------------------------------------------------------------------------
+ gen_deinterleave_i : FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ gen_deinterleave_j : FOR j IN 0 TO c_nof_apertif_bf_units-1 GENERATE
+ u_deinterleave : ENTITY dp_lib.dp_deinterleave
+ GENERIC MAP (
+ g_nof_out => 2,
+ g_block_size_int => 1,
+ g_block_size_output => c_nof_beamlets,
+ g_dat_w => c_channel_dat_w,
+ g_use_ctrl => TRUE,
+ g_use_sync_bsn => TRUE,
+ g_align_out => TRUE,
+ g_use_complex => FALSE
+ )
+ PORT MAP (
+ rst => dp_rst,
+ clk => dp_clk,
+
+ snk_in => dp_deinterleave_snk_in_2arr_4(i)(j),
+ src_out_arr => dp_deinterleave_src_out_3arr_4_2(i)(j)
+ );
+ END GENERATE;
END GENERATE;
-END wrap;
+ -------------------------------------------------------------------------------
+ -- Rewire 3*4*2 into 3*8
+ -------------------------------------------------------------------------------
+ gen_rewire : FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ -- Deinterleaver output 0 = even beamlet indices
+ dp_deinterleave_src_out_2arr_8(i)(0) <= dp_deinterleave_src_out_3arr_4_2(i)(0)(0); -- Beamlet 0, 2, 4, .. 174
+ dp_deinterleave_src_out_2arr_8(i)(1) <= dp_deinterleave_src_out_3arr_4_2(i)(1)(0); -- Beamlet 256, 258, 260, .. 430
+ dp_deinterleave_src_out_2arr_8(i)(2) <= dp_deinterleave_src_out_3arr_4_2(i)(2)(0); -- Beamlet 512, 514, 516, .. 686
+ dp_deinterleave_src_out_2arr_8(i)(3) <= dp_deinterleave_src_out_3arr_4_2(i)(3)(0); -- Beamlet 768, 770, 772, .. 942
+ -- Deinterleaver output 1 = odd beamlet indices
+ dp_deinterleave_src_out_2arr_8(i)(4) <= dp_deinterleave_src_out_3arr_4_2(i)(0)(1); -- Beamlet 1, 3, 5, .. 175
+ dp_deinterleave_src_out_2arr_8(i)(5) <= dp_deinterleave_src_out_3arr_4_2(i)(1)(1); -- Beamlet 257, 259, 261, .. 431
+ dp_deinterleave_src_out_2arr_8(i)(6) <= dp_deinterleave_src_out_3arr_4_2(i)(2)(1); -- Beamlet 513, 515, 517, .. 689
+ dp_deinterleave_src_out_2arr_8(i)(7) <= dp_deinterleave_src_out_3arr_4_2(i)(3)(1); -- Beamlet 769, 771, 773, .. 943
+ END GENERATE;
+
+ -------------------------------------------------------------------------------
+ -- Transpose 3*8 into 8*3 streams
+ -------------------------------------------------------------------------------
+ gen_transpose_i : FOR i IN 0 TO c_nof_10GbE_streams-1 GENERATE
+ gen_transpose_j : FOR j IN 0 TO c_nof_nodes-1 GENERATE
+ dp_deinterleave_src_out_2arr_3(j)(i) <= dp_deinterleave_src_out_2arr_8(i)(j);
+ END GENERATE;
+ END GENERATE;
+
+ -------------------------------------------------------------------------------
+ -- Concatenate 8*3 16b streams into 8 48b streams
+ -------------------------------------------------------------------------------
+ gen_concat : FOR i IN 0 TO c_nof_nodes-1 GENERATE
+ dp_deinterleave_src_out_arr(i) <= func_dp_stream_concat(dp_deinterleave_src_out_2arr_3(i), c_channel_dat_w);
+ END GENERATE;
+
+ -------------------------------------------------------------------------------
+ -- Mesh Terminals: transpose
+ -- . Input : 8 destination FPGAs * 3 local inputs 0..2
+ -- . Output : 8 source FPGAs * 3 remote inputs (total: inputs 0..23)
+ -- . Processed beamlet/FPGA should match the Apertif XC and ARTS SC4: 24 inputs*88 beamlets/FPGA
+ -- . FPGA 0 = FN0 - 0, 2, 4, .. 174 (88 beamlets*24 inputs) <- Output enabled only on this FPGA; central beam should be in these beamlets.
+ -- . FPGA 1 = FN1 - 256, 258, 260, .. 430 (88 beamlets*24 inputs)
+ -- . FPGA 2 = FN2 - 512, 514, 516, .. 686 (88 beamlets*24 inputs)
+ -- . FPGA 3 = FN3 - 768, 770, 772, .. 942 (88 beamlets*24 inputs)
+ -- . FPGA 4 = BN0 - 1, 3, 5, .. 175 (88 beamlets*24 inputs)
+ -- . FPGA 5 = BN1 - 257, 259, 261, .. 431 (88 beamlets*24 inputs)
+ -- . FPGA 6 = BN2 - 513, 515, 517, .. 689 (88 beamlets*24 inputs)
+ -- . FPGA 7 = BN3 - 769, 771, 773, .. 943 (88 beamlets*24 inputs)
+ -------------------------------------------------------------------------------
+ node_apertif_unb1_correlator_mesh_snk_in_arr <= dp_deinterleave_src_out_arr;
+
+ u_node_apertif_unb1_correlator_mesh : ENTITY work.node_apertif_unb1_correlator_mesh
+ GENERIC MAP(
+ g_sim => g_sim,
+ g_sim_level => 1,
+ g_nof_input_streams => c_nof_nodes,
+ g_nof_output_streams => c_nof_nodes,
+ g_usr_use_complex => FALSE,
+ g_usr_frame_len => c_nof_beamlets
+ )
+ PORT MAP(
+ chip_id => chip_id,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ tr_mesh_clk => SB_CLK,
+ cal_clk => cal_rec_clk,
+
+ snk_in_arr => node_apertif_unb1_correlator_mesh_snk_in_arr,
+ src_out_arr => node_apertif_unb1_correlator_mesh_src_out_arr,
+
+ reg_bsn_monitor_mosi => reg_dp_bsn_monitor_mesh_mosi,
+ reg_bsn_monitor_miso => reg_dp_bsn_monitor_mesh_miso,
+
+ reg_dp_bsn_align_mosi => reg_dp_bsn_align_mesh_mosi,
+ reg_dp_bsn_align_miso => reg_dp_bsn_align_mesh_miso,
+
+ FN_BN_0_TX => FN_BN_0_TX,
+ FN_BN_0_RX => FN_BN_0_RX,
+ FN_BN_1_TX => FN_BN_1_TX,
+ FN_BN_1_RX => FN_BN_1_RX,
+ FN_BN_2_TX => FN_BN_2_TX,
+ FN_BN_2_RX => FN_BN_2_RX,
+ FN_BN_3_TX => FN_BN_3_TX,
+ FN_BN_3_RX => FN_BN_3_RX
+ );
+
+ -------------------------------------------------------------------------------
+ -- Unconcatenate the 8 48b streams into 2*12 16b streams
+ -------------------------------------------------------------------------------
+ p_unconcat_mesh_src_out: PROCESS(node_apertif_unb1_correlator_mesh_src_out_arr)
+ BEGIN
+ FOR i IN 0 TO c_nof_polarizations-1 LOOP
+ FOR j IN 0 TO c_nof_telescopes-1 LOOP
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(i)(j) <= node_apertif_unb1_correlator_mesh_src_out_arr(0); --Sop, Eop, BSN, sync etc.
+ END LOOP;
+ END LOOP;
+
+ -- Y polarization
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(1)(11).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(7).data(47 DOWNTO 32); --FIXME Put this in a FOR loop.
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(1)(10).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(7).data(31 DOWNTO 16);
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(1)(9).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(7).data(15 DOWNTO 0);
+
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(1)(8).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(6).data(47 DOWNTO 32);
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(1)(7).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(6).data(31 DOWNTO 16);
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(1)(6).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(6).data(15 DOWNTO 0);
+
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(1)(5).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(5).data(47 DOWNTO 32);
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(1)(4).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(5).data(31 DOWNTO 16);
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(1)(3).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(5).data(15 DOWNTO 0);
+
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(1)(2).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(4).data(47 DOWNTO 32);
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(1)(1).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(4).data(31 DOWNTO 16);
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(1)(0).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(4).data(15 DOWNTO 0);
+ -- X polarization
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(0)(11).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(3).data(47 DOWNTO 32);
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(0)(10).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(3).data(31 DOWNTO 16);
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(0)(9).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(3).data(15 DOWNTO 0);
+
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(0)(8).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(2).data(47 DOWNTO 32);
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(0)(7).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(2).data(31 DOWNTO 16);
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(0)(6).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(2).data(15 DOWNTO 0);
+
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(0)(5).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(1).data(47 DOWNTO 32);
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(0)(4).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(1).data(31 DOWNTO 16);
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(0)(3).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(1).data(15 DOWNTO 0);
+
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(0)(2).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(0).data(47 DOWNTO 32);
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(0)(1).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(0).data(31 DOWNTO 16);
+ node_apertif_unb1_correlator_mesh_src_out_2arr_12(0)(0).data(15 DOWNTO 0) <= node_apertif_unb1_correlator_mesh_src_out_arr(0).data(15 DOWNTO 0);
+ END PROCESS;
+
+
+END str;
diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_processing.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_processing.vhd
index 05457804666028c523fc823c702e5a7fbbe266f7..7fab99f4446dca08ac17e069dd7c759d8f463053 100644
--- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_processing.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_processing.vhd
@@ -74,29 +74,29 @@ ARCHITECTURE str OF arts_unb1_sc4_processing IS
-------------------------------------------------------------------------------
-- WPFB
-------------------------------------------------------------------------------
- CONSTANT c_use_prefilter : BOOLEAN := FALSE;
- CONSTANT c_wpfb_wb_factor : NATURAL := 1;
- CONSTANT c_wpfb_nof_wb_streams : NATURAL := g_nof_telescopes;
- CONSTANT c_wpfb_nof_chan : NATURAL := g_nof_polarizations;
- CONSTANT c_wpfb_nof_points : NATURAL := c_nof_channels;
- CONSTANT c_wpfb_nof_taps : NATURAL := 8;
- CONSTANT c_wpfb_coef_w : NATURAL := 9;
- CONSTANT c_wpfb_in_backoff_w : natural := 0;
- CONSTANT c_wpfb_in_dat_w : NATURAL := g_input_data_w;
- CONSTANT c_wpfb_fft_in_dat_w : NATURAL := g_input_data_w;
- CONSTANT c_wpfb_out_dat_w : NATURAL := 12;
- CONSTANT c_wpfb_out_dat_significant_w : NATURAL := sel_a_b(g_input_data_w = 6, 10, 12);
- CONSTANT c_wpfb_out_gain_w : NATURAL := 0;
- CONSTANT c_wpfb_use_separate : BOOLEAN := FALSE;
- CONSTANT c_wpfb_use_reorder : BOOLEAN := FALSE;
- CONSTANT c_wpfb_use_fft_shift : BOOLEAN := FALSE;
-
- CONSTANT c_wpfb : t_wpfb := (c_wpfb_wb_factor, c_wpfb_nof_points, c_wpfb_nof_chan, c_wpfb_nof_wb_streams,
- c_wpfb_nof_taps, c_wpfb_in_backoff_w, c_wpfb_in_dat_w, 16, c_wpfb_coef_w,
- c_wpfb_use_reorder, c_wpfb_use_fft_shift, c_wpfb_use_separate, c_wpfb_fft_in_dat_w, c_wpfb_out_dat_w, c_wpfb_out_gain_w, 18, 2, true, 56, 2, c_nof_blocks_per_sync,
- c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);
-
- CONSTANT c_wpfb_coefs_file_prefix : STRING := "hex/chan_fil_coefs_wide1_p32_t8";
+-- CONSTANT c_use_prefilter : BOOLEAN := FALSE;
+-- CONSTANT c_wpfb_wb_factor : NATURAL := 1;
+-- CONSTANT c_wpfb_nof_wb_streams : NATURAL := g_nof_telescopes;
+-- CONSTANT c_wpfb_nof_chan : NATURAL := g_nof_polarizations;
+-- CONSTANT c_wpfb_nof_points : NATURAL := c_nof_channels;
+-- CONSTANT c_wpfb_nof_taps : NATURAL := 8;
+-- CONSTANT c_wpfb_coef_w : NATURAL := 9;
+-- CONSTANT c_wpfb_in_backoff_w : natural := 0;
+-- CONSTANT c_wpfb_in_dat_w : NATURAL := g_input_data_w;
+-- CONSTANT c_wpfb_fft_in_dat_w : NATURAL := g_input_data_w;
+-- CONSTANT c_wpfb_out_dat_w : NATURAL := 12;
+-- CONSTANT c_wpfb_out_dat_significant_w : NATURAL := sel_a_b(g_input_data_w = 6, 10, 12);
+-- CONSTANT c_wpfb_out_gain_w : NATURAL := 0;
+-- CONSTANT c_wpfb_use_separate : BOOLEAN := FALSE;
+-- CONSTANT c_wpfb_use_reorder : BOOLEAN := FALSE;
+-- CONSTANT c_wpfb_use_fft_shift : BOOLEAN := FALSE;
+--
+-- CONSTANT c_wpfb : t_wpfb := (c_wpfb_wb_factor, c_wpfb_nof_points, c_wpfb_nof_chan, c_wpfb_nof_wb_streams,
+-- c_wpfb_nof_taps, c_wpfb_in_backoff_w, c_wpfb_in_dat_w, 16, c_wpfb_coef_w,
+-- c_wpfb_use_reorder, c_wpfb_use_fft_shift, c_wpfb_use_separate, c_wpfb_fft_in_dat_w, c_wpfb_out_dat_w, c_wpfb_out_gain_w, 18, 2, true, 56, 2, c_nof_blocks_per_sync,
+-- c_fft_pipeline, c_fft_pipeline, c_fil_ppf_pipeline);
+--
+-- CONSTANT c_wpfb_coefs_file_prefix : STRING := "hex/chan_fil_coefs_wide1_p32_t8";
SIGNAL wpfb_snk_in_arr : t_dp_sosi_arr(g_nof_telescopes-1 DOWNTO 0);
SIGNAL wpfb_src_out_arr : t_dp_sosi_arr(g_nof_telescopes-1 DOWNTO 0);
@@ -118,6 +118,8 @@ ARCHITECTURE str OF arts_unb1_sc4_processing IS
-- stat_data_w : POSITIVE; -- = 32
-- stat_data_sz : POSITIVE; -- = 2
+ CONSTANT c_nof_bf_subbands : NATURAL := 240;
+ CONSTANT c_channel_dat_w : NATURAL := 8;
CONSTANT c_bf_bf : t_c_bf := (g_nof_telescopes, g_nof_telescopes, c_nof_bf_subbands, c_nof_bf_subbands, g_nof_tabs, c_channel_dat_w, 16, 1, 16, 1, 8, 32, 2);
CONSTANT c_bf_bf_weights_file_name : STRING := "hex/bf_weights";
@@ -227,26 +229,26 @@ BEGIN
-------------------------------------------------------------------------------
-- TAB Beam former FIFO stage: BF module requires flow control
-------------------------------------------------------------------------------
- gen_dp_fifo_sc : FOR i IN 0 TO g_nof_telescopes-1 GENERATE
- u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
- GENERIC MAP(
- g_data_w => g_input_data_w,
- g_bsn_w => 64,
- g_fifo_size => 30,
- g_use_bsn => TRUE,
- g_use_sync => TRUE,
- g_use_ctrl => TRUE
- )
- PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
-
- snk_in => wpfb_src_out_arr(i),
-
- src_in => bf_src_out_arr(i),
- src_out => bf_snk_in_arr(i)
- );
- END GENERATE;
+-- gen_dp_fifo_sc : FOR i IN 0 TO g_nof_telescopes-1 GENERATE
+-- u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
+-- GENERIC MAP(
+-- g_data_w => g_input_data_w,
+-- g_bsn_w => 64,
+-- g_fifo_size => 30,
+-- g_use_bsn => TRUE,
+-- g_use_sync => TRUE,
+-- g_use_ctrl => TRUE
+-- )
+-- PORT MAP (
+-- rst => dp_rst,
+-- clk => dp_clk,
+--
+-- snk_in => wpfb_src_out_arr(i),
+--
+-- src_in => bf_src_out_arr(i),
+-- src_out => bf_snk_in_arr(i)
+-- );
+-- END GENERATE;
-------------------------------------------------------------------------------
-- TAB Beam Former