Merge branch 'L2SDP-79' into 'master'

Added the IP variant ip_arria10_e1sg_ddr4_16g_1600.

Closes L2SDP-79

See merge request desp/hdl!31

libraries/technology/ddr/hdllib.cfg

@@ -15,6 +15,7 @@ hdl_lib_uses_ip = ip_stratixiv_ddr3_uphy_4g_800_master
                   ip_arria10_e3sge3_ddr4_8g_2400
                   ip_arria10_e1sg_ddr4_4g_1600
                   ip_arria10_e1sg_ddr4_8g_1600
+                  ip_arria10_e1sg_ddr4_16g_1600
                   ip_arria10_e1sg_ddr4_4g_2000
                   ip_arria10_e1sg_ddr4_8g_2400
                   ip_arria10_e2sg_ddr4_8g_1600
@@ -37,6 +38,7 @@ hdl_lib_disclose_library_clause_names =
     ip_arria10_e3sge3_ddr4_8g_2400                   ip_arria10_e3sge3_ddr4_8g_2400_altera_emif_151
     ip_arria10_e1sg_ddr4_4g_1600                     ip_arria10_e1sg_ddr4_4g_1600_altera_emif_180
     ip_arria10_e1sg_ddr4_8g_1600                     ip_arria10_e1sg_ddr4_8g_1600_altera_emif_180
+    ip_arria10_e1sg_ddr4_16g_1600                    ip_arria10_e1sg_ddr4_16g_1600_altera_emif_180
     ip_arria10_e1sg_ddr4_4g_2000                     ip_arria10_e1sg_ddr4_4g_2000_altera_emif_180
     ip_arria10_e1sg_ddr4_8g_2400                     ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180
     ip_stratixiv_ddr3_mem_model                      ip_stratixiv_ddr3_mem_model_lib

libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd

@@ -36,6 +36,7 @@
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_e1sg_ddr4_4g_1600_altera_emif_180;
 LIBRARY ip_arria10_e1sg_ddr4_8g_1600_altera_emif_180;
+LIBRARY ip_arria10_e1sg_ddr4_16g_1600_altera_emif_180;
 LIBRARY ip_arria10_e1sg_ddr4_4g_2000_altera_emif_180;
 LIBRARY ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180;
 
@@ -258,5 +259,59 @@ BEGIN
     ctlr_miso.cal_fail <= local_cal_fail;
     
   END GENERATE;
+  
+  gen_ip_arria10_e1sg_ddr4_16g_1600 : IF g_tech_ddr.name="DDR4" AND c_gigabytes=16 AND g_tech_ddr.mts=1600 GENERATE
+
+    u_ip_arria10_e1sg_ddr4_16g_1600 : ip_arria10_e1sg_ddr4_16g_1600
+    PORT MAP (
+      amm_ready_0         => ctlr_miso.waitrequest_n,                                   --     ctrl_amm_avalon_slave_0.waitrequest_n
+      amm_read_0          => ctlr_mosi.rd,                                              --                            .read
+      amm_write_0         => ctlr_mosi.wr,                                              --                            .write
+      amm_address_0       => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0),            --                            .address
+      amm_readdata_0      => ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0),                --                            .readdata
+      amm_writedata_0     => ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0),                --                            .writedata
+      amm_burstcount_0    => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), --                            .burstcount
+      amm_byteenable_0    => (OTHERS=>'1'),                                             --                            .byteenable
+      amm_readdatavalid_0 => ctlr_miso.rdval,                                           --                            .readdatavalid
+      emif_usr_clk        => i_ctlr_gen_clk,                                            --   emif_usr_clk_clock_source.clk
+      emif_usr_reset_n    => ctlr_gen_rst_n,                                            -- emif_usr_reset_reset_source.reset_n
+      global_reset_n      => ref_rst_n,                                                 --     global_reset_reset_sink.reset_n
+      mem_ck              => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0),                     --             mem_conduit_end.mem_ck
+      mem_ck_n            => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0),                   --                            .mem_ck_n
+      mem_a               => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0),                       --                            .mem_a
+   sl(mem_act_n)          => phy_ou.act_n,                                              --                            .mem_act_n
+      mem_ba              => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0),                     --                            .mem_ba
+      mem_bg              => phy_ou.bg(g_tech_ddr.bg_w-1 DOWNTO 0),                     --                            .mem_bg
+      mem_cke             => phy_ou.cke(g_tech_ddr.cke_w-1 DOWNTO 0),                   --                            .mem_cke
+      mem_cs_n            => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0),                   --                            .mem_cs_n
+      mem_odt             => phy_ou.odt(g_tech_ddr.odt_w-1 DOWNTO 0),                   --                            .mem_odt
+   sl(mem_reset_n)        => phy_ou.reset_n,                                            --                            .mem_reset_n
+   sl(mem_par)            => phy_ou.par,                                                --                            .mem_par
+      mem_alert_n         => slv(phy_in.alert_n),                                       --                            .mem_alert_n
+      mem_dqs             => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0),                   --                            .mem_dqs
+      mem_dqs_n           => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0),                 --                            .mem_dqs_n
+      mem_dq              => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0),                     --                            .mem_dq
+      mem_dbi_n           => phy_io.dbi_n(g_tech_ddr.dbi_w-1 DOWNTO 0),                 --                            .mem_dbi_n
+      oct_rzqin           => phy_in.oct_rzqin,                                          --             oct_conduit_end.oct_rzqin
+      pll_ref_clk         => ref_clk,                                                   --      pll_ref_clk_clock_sink.clk
+      local_cal_success   => local_cal_success,                                         --          status_conduit_end.local_cal_success
+      local_cal_fail      => local_cal_fail                                             --                            .local_cal_fail
+    );
+    
+    -- Signals in DDR3 that are not available with DDR4:
+    --
+    --avl_burstbegin             => ctlr_mosi.burstbegin,                               --             .beginbursttransfer
+    --   beginbursttransfer is obselete for new Avalon designs, because the slave can count valid data itself to know when a new burst starts
+    --
+    --local_init_done            => ctlr_miso.done,                                     --       status.local_init_done
+    --   local_init_done = ctlr_init_done originally and mapped to ctlr_miso.done for the DDR3 IP. For the DDR4 IP the local_cal_success and
+    --   NOT local_cal_fail seem  to serve as local_init_done
+    
+    ctlr_miso.done     <= local_cal_success AND NOT local_cal_fail WHEN rising_edge(i_ctlr_gen_clk);
+    ctlr_miso.cal_ok   <= local_cal_success;
+    ctlr_miso.cal_fail <= local_cal_fail;
+    
+  END GENERATE;
+
 
 END str;

libraries/technology/ddr/tech_ddr_component_pkg.vhd

@@ -567,6 +567,43 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
+  COMPONENT ip_arria10_e1sg_ddr4_16g_1600 IS
+  PORT (
+    amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
+    amm_read_0          : in    std_logic                      := '0';             --                            .read
+    amm_write_0         : in    std_logic                      := '0';             --                            .write
+    amm_address_0       : in    std_logic_vector(27 downto 0)  := (others => '0'); --                            .address
+    amm_readdata_0      : out   std_logic_vector(575 downto 0);                    --                            .readdata
+    amm_writedata_0     : in    std_logic_vector(575 downto 0) := (others => '0'); --                            .writedata
+    amm_burstcount_0    : in    std_logic_vector(6 downto 0)   := (others => '0'); --                            .burstcount
+    amm_byteenable_0    : in    std_logic_vector(71 downto 0)  := (others => '0'); --                            .byteenable
+    amm_readdatavalid_0 : out   std_logic;                                         --                            .readdatavalid
+    emif_usr_clk        : out   std_logic;                                         --   emif_usr_clk_clock_source.clk
+    emif_usr_reset_n    : out   std_logic;                                         -- emif_usr_reset_reset_source.reset_n
+    global_reset_n      : in    std_logic                      := '0';             --     global_reset_reset_sink.reset_n
+    mem_ck              : out   std_logic_vector(1 downto 0);                      --             mem_conduit_end.mem_ck
+    mem_ck_n            : out   std_logic_vector(1 downto 0);                      --                            .mem_ck_n
+    mem_a               : out   std_logic_vector(16 downto 0);                     --                            .mem_a
+    mem_act_n           : out   std_logic_vector(0 downto 0);                      --                            .mem_act_n
+    mem_ba              : out   std_logic_vector(1 downto 0);                      --                            .mem_ba
+    mem_bg              : out   std_logic_vector(1 downto 0);                      --                            .mem_bg
+    mem_cke             : out   std_logic_vector(1 downto 0);                      --                            .mem_cke
+    mem_cs_n            : out   std_logic_vector(1 downto 0);                      --                            .mem_cs_n
+    mem_odt             : out   std_logic_vector(1 downto 0);                      --                            .mem_odt
+    mem_reset_n         : out   std_logic_vector(0 downto 0);                      --                            .mem_reset_n
+    mem_par             : out   std_logic_vector(0 downto 0);                      --                            .mem_par
+    mem_alert_n         : in    std_logic_vector(0 downto 0)   := (others => '0'); --                            .mem_alert_n
+    mem_dqs             : inout std_logic_vector(8 downto 0)   := (others => '0'); --                            .mem_dqs
+    mem_dqs_n           : inout std_logic_vector(8 downto 0)   := (others => '0'); --                            .mem_dqs_n
+    mem_dq              : inout std_logic_vector(71 downto 0)  := (others => '0'); --                            .mem_dq
+    mem_dbi_n           : inout std_logic_vector(8 downto 0)   := (others => '0'); --                            .mem_dbi_n
+    oct_rzqin           : in    std_logic                      := '0';             --             oct_conduit_end.oct_rzqin
+    pll_ref_clk         : in    std_logic                      := '0';             --      pll_ref_clk_clock_sink.clk
+    local_cal_success   : out   std_logic;                                         --          status_conduit_end.local_cal_success
+    local_cal_fail      : out   std_logic                                          --                            .local_cal_fail
+  );
+  END COMPONENT;
+
   -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
   COMPONENT ip_arria10_e1sg_ddr4_4g_2000 IS
   PORT (

libraries/technology/ddr/tech_ddr_pkg.vhd

@@ -97,6 +97,7 @@ PACKAGE tech_ddr_pkg IS
   
   CONSTANT c_tech_ddr4_4g_1600m                   : t_c_tech_ddr := ("DDR4", 1600,  TRUE, "DUAL  ", 17, 15, 10, 2, 72, 9,  0, 9,  2, 1, 1,  1, 0,   1,   0,  8,  3,    8,  64,   7);
   CONSTANT c_tech_ddr4_8g_1600m                   : t_c_tech_ddr := ("DDR4", 1600,  TRUE, "DUAL  ", 17, 15, 10, 2, 72, 9,  0, 9,  2, 2, 2,  2, 1,   2,   0,  8,  3,    8,  64,   7);
+  CONSTANT c_tech_ddr4_16g_1600m                  : t_c_tech_ddr := ("DDR4", 1600,  TRUE, "DUAL  ", 17, 16, 10, 2, 72, 9,  0, 9,  2, 2, 2,  2, 1,   2,   0,  8,  3,    8,  64,   7);
   CONSTANT c_tech_ddr4_8g_1600m_64                : t_c_tech_ddr := ("DDR4", 1600,  TRUE, "DUAL  ", 17, 15, 10, 2, 64, 8,  0, 8,  2, 2, 2,  2, 1,   2,   0,  8,  3,    8,  64,   7);
   CONSTANT c_tech_ddr4_4g_2000m                   : t_c_tech_ddr := ("DDR4", 2000,  TRUE, "DUAL  ", 17, 15, 10, 2, 72, 9,  0, 9,  2, 1, 1,  1, 0,   1,   0,  8,  3,    8,  64,   7);
   CONSTANT c_tech_ddr4_8g_2400m                   : t_c_tech_ddr := ("DDR4", 2400,  TRUE, "DUAL  ", 17, 15, 10, 2, 72, 9,  0, 9,  2, 2, 2,  2, 1,   2,   0,  8,  3,    8,  64,   7);

libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/compile_ip.tcl

+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2017
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+
+#vlib ./work/         ;# Assume library work already exist                                                                                        
+
+
+set IP_DIR   "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_16g_1600/sim"
+                    
+  vcom         "$IP_DIR/ip_arria10_e1sg_ddr4_16g_1600.vhd"                                                                              

libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/copy_hex_files.tcl

+#------------------------------------------------------------------------------
+#
+# Copyright (C) 2015
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+#------------------------------------------------------------------------------
+
+# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_16g_1600/sim"
+
+# Copy ROM/RAM files to simulation directory
+if {[file isdirectory $IP_DIR]} {
+    file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_151_4thorvi_seq_cal_sim.hex ./
+    file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_151_4thorvi_seq_cal_synth.hex ./
+    file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_151_4thorvi_seq_params_sim.hex ./
+    file copy -force $IP_DIR/../altera_emif_arch_nf_151/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_151_4thorvi_seq_params_synth.hex ./
+}

libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/hdllib.cfg

+hdl_lib_name = ip_arria10_e1sg_ddr4_16g_1600
+hdl_library_clause_name = ip_arria10_e1sg_ddr4_16g_1600_altera_emif_180
+hdl_lib_uses_synth = 
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_merlin_master_translator_180 ip_arria10_e1sg_altera_emif_cal_slave_nf_180 ip_arria10_e1sg_altera_avalon_onchip_memory2_180 ip_arria10_e1sg_altera_mm_interconnect_180 ip_arria10_e1sg_altera_reset_controller_180 ip_arria10_e1sg_altera_emif_arch_nf_180 ip_arria10_e1sg_altera_emif_180 ip_arria10_e1sg_altera_avalon_mm_bridge_180 ip_arria10_e1sg_altera_merlin_slave_translator_180 ip_arria10_e1sg_altera_avalon_sc_fifo_180 ip_arria10_e1sg_altera_avalon_st_packets_to_bytes_180 ip_arria10_e1sg_altera_ip_col_if_180 ip_arria10_e1sg_altera_jtag_dc_streaming_180 ip_arria10_e1sg_alt_mem_if_jtag_master_180 ip_arria10_e1sg_altera_avalon_st_bytes_to_packets_180 ip_arria10_e1sg_altera_avalon_packets_to_master_180 ip_arria10_e1sg_channel_adapter_180 ip_arria10_e1sg_timing_adapter_180
+
+hdl_lib_technology = ip_arria10_e1sg
+
+synth_files =
+    
+test_bench_files = 
+
+
+[modelsim_project_file]
+modelsim_compile_ip_files =
+    #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/compile_ip.tcl
+
+
+[quartus_project_file]
+quartus_qip_files =
+    $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_16g_1600/ip_arria10_e1sg_ddr4_16g_1600.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_ddr4_16g_1600.qsys
+