Removed g_r2_mul_extra_w because it more clear to increase stage_dat_w.

libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd

@@ -77,8 +77,7 @@ entity fft_r2_wide is
   generic (
     g_fft            : t_fft := c_fft;                   -- generics for the FFT
     g_pft_pipeline   : t_fft_pipeline := c_fft_pipeline; -- For the pipelined part, from rTwoSDF_lib.rTwoSDFPkg
-    g_fft_pipeline   : t_fft_pipeline := c_fft_pipeline; -- For the parallel part, from rTwoSDF_lib.rTwoSDFPkg
-    g_r2_mul_extra_w : natural := 0   -- extra bits at rTwoWMul output in rTwoSDFStage to improve rTwoSDFStage output requantization in fft_r2_pipe
+    g_fft_pipeline   : t_fft_pipeline := c_fft_pipeline  -- For the parallel part, from rTwoSDF_lib.rTwoSDFPkg
   );
   port (
     clk        : in  std_logic;
@@ -187,8 +186,7 @@ begin
     u_fft_r2_pipe : entity work.fft_r2_pipe
     generic map (
       g_fft            => g_fft,
-      g_pipeline       => g_pft_pipeline,
-      g_r2_mul_extra_w => g_r2_mul_extra_w
+      g_pipeline       => g_pft_pipeline
     )
     port map (
       clk        => clk,
@@ -243,8 +241,7 @@ begin
       u_pft : entity work.fft_r2_pipe
       generic map (
         g_fft            => c_fft_r2_pipe_arr(I),   -- generics for the pipelined FFTs
-        g_pipeline       => g_pft_pipeline,         -- pipeline generics for the pipelined FFTs
-        g_r2_mul_extra_w => g_r2_mul_extra_w
+        g_pipeline       => g_pft_pipeline          -- pipeline generics for the pipelined FFTs
       )
       port map (
         clk       => clk,