Removed g_r2_mul_extra_w because it more clear to increase stage_dat_w.

libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFStage.vhd

@@ -32,7 +32,6 @@ entity rTwoSDFStage is
     g_stage_offset   : natural := 0; -- The Stage offset: 0 for normal FFT. Other than 0 in wideband FFT
     g_twiddle_offset : natural := 0; -- The twiddle offset: 0 for normal FFT. Other than 0 in wideband FFT
     g_scale_enable   : boolean := TRUE; -- 
-    g_r2_mul_extra_w : natural := 0;    -- extra bits at rTwoMult output to improve FFT stage output requantization
     g_pipeline       : t_fft_pipeline := c_fft_pipeline  -- internal pipeline settings
   );
   port (
@@ -70,8 +69,8 @@ architecture str of rTwoSDFStage is
   signal weight_re      : wTyp;
   signal weight_im      : wTyp;
   
-  signal mul_out_re     : std_logic_vector(out_re'length-1 + g_r2_mul_extra_w downto 0);
-  signal mul_out_im     : std_logic_vector(out_im'length-1 + g_r2_mul_extra_w downto 0);
+  signal mul_out_re     : std_logic_vector(out_re'length-1 downto 0);
+  signal mul_out_im     : std_logic_vector(out_im'length-1 downto 0);
   signal mul_out_val    : std_logic;
 
   signal quant_out_re   : std_logic_vector(out_re'range);
@@ -170,7 +169,7 @@ begin
   u_requantize_re : entity common_lib.common_requantize
   generic map (
     g_representation      => "SIGNED",      
-    g_lsb_w               => c_r2_stage_bit_growth + g_r2_mul_extra_w,
+    g_lsb_w               => c_r2_stage_bit_growth,
     g_lsb_round           => TRUE,           
     g_lsb_round_clip      => FALSE,      
     g_msb_clip            => FALSE,            
@@ -191,7 +190,7 @@ begin
   u_requantize_im : entity common_lib.common_requantize
   generic map (
     g_representation      => "SIGNED",      
-    g_lsb_w               => c_r2_stage_bit_growth + g_r2_mul_extra_w,               
+    g_lsb_w               => c_r2_stage_bit_growth,
     g_lsb_round           => TRUE,           
     g_lsb_round_clip      => FALSE,      
     g_msb_clip            => FALSE,