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Commit 48614549 authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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currently using 24x 10G on QSFP

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boards/uniboard2/designs/unb2_test/doc/README
+ 9
− 0
View file @ 48614549
......@@ -13,6 +13,9 @@ Generate MMM for QSYS (select one of these revisions):
run_qsys unb2 unb2_test_10GbE
run_qsys unb2 unb2_test_ddr
run_qsys unb2 unb2_test_all
run_qsys unb2 unb2_test_ddr_MB_I
run_qsys unb2 unb2_test_ddr_MB_II
run_qsys unb2 unb2_test_ddr_MB_I_II
-> From here either continue to Modelsim (simulation) or Quartus (synthesis)
......@@ -47,6 +50,9 @@ Quartus instructions: (select one of these revisions):
run_qcomp unb2 unb2_test_1GbE
run_qcomp unb2 unb2_test_ddr
run_qcomp unb2 unb2_test_all
run_qcomp unb2 unb2_test_ddr_MB_I
run_qcomp unb2 unb2_test_ddr_MB_II
run_qcomp unb2 unb2_test_ddr_MB_I_II
In case of needing the Quartus GUI for inspection:
......@@ -59,6 +65,9 @@ Convert .sof to .rbf:
run_rbf unb2 unb2_test_1GbE
run_rbf unb2 unb2_test_ddr
run_rbf unb2 unb2_test_all
run_rbf unb2 unb2_test_ddr_MB_I
run_rbf unb2 unb2_test_ddr_MB_II
run_rbf unb2 unb2_test_ddr_MB_I_II
Send to LCU capture5:
......
boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
+ 1
− 1
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......@@ -2,7 +2,7 @@ hdl_lib_name = unb2_test_10GbE
hdl_library_clause_name = unb2_test_10GbE_lib
hdl_lib_uses_synth = common mm technology unb2_board unb2_test
hdl_lib_uses_sim =
hdl_lib_excludes = ip_arria10_ddr4_4g_1600 ip_arria10_ddr4_8g_2400
hdl_lib_excludes = ip_arria10_ddr4_4g_1600 ip_arria10_ddr4_8g_2400 ip_arria10_ddr4_4g_2000
hdl_lib_technology = ip_arria10
......
boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
+ 12
− 12
View file @ 48614549
......@@ -92,12 +92,12 @@ ENTITY unb2_test_10GbE IS
QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
--QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
--QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
--QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
--QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
--QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
--QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
......@@ -172,12 +172,12 @@ BEGIN
QSFP_1_TX => QSFP_1_TX,
QSFP_2_RX => QSFP_2_RX,
QSFP_2_TX => QSFP_2_TX,
--QSFP_3_RX => QSFP_3_RX,
--QSFP_3_TX => QSFP_3_TX,
--QSFP_4_RX => QSFP_4_RX,
--QSFP_4_TX => QSFP_4_TX,
--QSFP_5_RX => QSFP_5_RX,
--QSFP_5_TX => QSFP_5_TX,
QSFP_3_RX => QSFP_3_RX,
QSFP_3_TX => QSFP_3_TX,
QSFP_4_RX => QSFP_4_RX,
QSFP_4_TX => QSFP_4_TX,
QSFP_5_RX => QSFP_5_RX,
QSFP_5_TX => QSFP_5_TX,
QSFP_SDA => QSFP_SDA,
QSFP_SCL => QSFP_SCL,
......
boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+ 17
− 16
View file @ 48614549
......@@ -109,12 +109,12 @@ ENTITY unb2_test IS
QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
--QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
--QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
--QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
--QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
--QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
--QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0) := (OTHERS=>'0');
QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
......@@ -153,7 +153,7 @@ ARCHITECTURE str OF unb2_test IS
CONSTANT c_use_MB_II : BOOLEAN := g_design_name="unb2_test_ddr_MB_II" OR g_design_name="unb2_test_ddr_MB_I_II" OR g_design_name="unb2_test_all";
-- transceivers
CONSTANT c_nof_qsfp : NATURAL := 12;--c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;--8
CONSTANT c_nof_qsfp : NATURAL := c_unb2_board_tr_qsfp.nof_bus * c_unb2_board_tr_qsfp.bus_w;
CONSTANT c_nof_ring : NATURAL := 0;--8;--12;--c_unb2_board_tr_ring.nof_bus * c_unb2_board_tr_ring.bus_w;
CONSTANT c_nof_back0 : NATURAL := 0;--c_unb2_board_tr_back.bus_w;
CONSTANT c_nof_back1 : NATURAL := c_unb2_board_tr_back.bus_w;
......@@ -877,16 +877,16 @@ BEGIN
i_QSFP_RX(0) <= QSFP_0_RX;
i_QSFP_RX(1) <= QSFP_1_RX;
i_QSFP_RX(2) <= QSFP_2_RX;
-- --i_QSFP_RX(3) <= QSFP_3_RX;
-- --i_QSFP_RX(4) <= QSFP_4_RX;
-- --i_QSFP_RX(5) <= QSFP_5_RX;
--
i_QSFP_RX(3) <= QSFP_3_RX;
i_QSFP_RX(4) <= QSFP_4_RX;
i_QSFP_RX(5) <= QSFP_5_RX;
QSFP_0_TX <= i_QSFP_TX(0);
QSFP_1_TX <= i_QSFP_TX(1);
QSFP_2_TX <= i_QSFP_TX(2);
-- --QSFP_3_TX <= i_QSFP_TX(3);
-- --QSFP_4_TX <= i_QSFP_TX(4);
-- --QSFP_5_TX <= i_QSFP_TX(5);
QSFP_3_TX <= i_QSFP_TX(3);
QSFP_4_TX <= i_QSFP_TX(4);
QSFP_5_TX <= i_QSFP_TX(5);
......@@ -1033,7 +1033,7 @@ BEGIN
gen_no_udp_stream_10GbE : IF c_use_10GbE = FALSE GENERATE
u_front_io : ENTITY unb2_board_lib.unb2_board_front_io
GENERIC MAP (
g_nof_qsfp_bus => 2--c_unb2_board_tr_qsfp.nof_bus
g_nof_qsfp_bus => c_unb2_board_tr_qsfp.nof_bus
)
PORT MAP (
green_led_arr => qsfp_green_led_arr,
......@@ -1044,7 +1044,7 @@ BEGIN
GENERIC MAP (
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => 2,--c_unb2_board_tr_qsfp.nof_bus,
g_nof_qsfp => c_unb2_board_tr_qsfp.nof_bus,
g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
)
PORT MAP (
......@@ -1063,6 +1063,7 @@ BEGIN
ASSERT func_tech_ddr_ctlr_data_w(g_ddr_MB_I)=func_tech_ddr_ctlr_data_w(g_ddr_MB_II) REPORT "unb2_test: DDR4 MB_I and MB_II must have the same ctlr data widths" SEVERITY FAILURE;
gen_stream_MB_I : IF c_use_MB_I = TRUE GENERATE
u_mms_io_ddr_diag : ENTITY io_ddr_lib.mms_io_ddr_diag
GENERIC MAP (
-- System
......
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