Add ERROR note to proc_common_stop_simulation in case of timeout.

libraries/base/common/tb/vhdl/tb_common_pkg.vhd

@@ -527,6 +527,7 @@ PACKAGE BODY tb_common_pkg IS
                                         SIGNAL tb_end      : IN STD_LOGIC) IS
   BEGIN
     WHILE tb_end='0' LOOP
+      ASSERT NOW < c_timeout REPORT "Test bench timeout." SEVERITY ERROR;
       ASSERT NOW < c_timeout REPORT "Test bench timeout." SEVERITY FAILURE;
       WAIT FOR 1 us;
     END LOOP;