Merge branch 'master' into L2SDP-206

applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc.sdc

@@ -92,10 +92,10 @@ set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_nat
 
 
 # false paths added for the jesd test design
-set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|link_clk}]
-set_false_path -from [get_clocks {*core_pll|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
-set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|frame_clk}]
-set_false_path -from [get_clocks {*core_pll|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*corepll_200MHz|link_clk}]
+set_false_path -from [get_clocks {*corepll_200MHz|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*corepll_200MHz|frame_clk}]
+set_false_path -from [get_clocks {*corepll_200MHz|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
 
 # Constraint on the SYSREF input pin
 #    Adjust this to account for any board trace difference between SYSREF and REFCLK

applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd

@@ -107,10 +107,23 @@ PACKAGE sdp_pkg is
  
   -- In SDP c_nof_channels = 2**nof_chan = 1 and wb_factor = 1, 
   -- therefore these parameters are not explicitly used in calculation of derived constants
+  -- LTS 2020_11_23:
+  --CONSTANT c_sdp_wpfb_subbands : t_wpfb :=
+  -- (1, c_sdp_N_fft, 0, c_sdp_P_pfb,
+  -- c_sdp_N_taps, 1, c_sdp_W_adc, 16, c_sdp_W_fir_coef,
+  -- true, false, true, 16, c_sdp_W_subband, 1, 18, 2, 
+  -- true, 54, 2, 195313, c_fft_pipeline, c_fft_pipeline, 
+  -- c_fil_ppf_pipeline);
+  -- LTS 2021-02-03, changes based on results from u_wpfb_stage22 in tb_tb_verify_pfb_wg.vhd:
+  -- . fil_backoff_w = 0 (was 1)
+  -- . fil_out_dat_w = fft_in_dat_w = 17 (was 16)
+  -- . g_fft_out_gain_w = 0 (was 1)
+  -- . g_fft_stage_dat_w = 22 (was 18)
+  -- . g_fft_guard_w = 1 (was 2)
   CONSTANT c_sdp_wpfb_subbands : t_wpfb :=
    (1, c_sdp_N_fft, 0, c_sdp_P_pfb,
-         c_sdp_N_taps, 1, c_sdp_W_adc, 16, c_sdp_W_fir_coef,
-         true, false, true, 16, c_sdp_W_subband, 1, 18, 2, 
+   c_sdp_N_taps, 0, c_sdp_W_adc, 17, c_sdp_W_fir_coef,
+   true, false, true, 17, c_sdp_W_subband, 0, 22, 1, 
    true, 54, 2, 195313, c_fft_pipeline, c_fft_pipeline, 
    c_fil_ppf_pipeline);
 
@@ -118,7 +131,6 @@ PACKAGE sdp_pkg is
   CONSTANT c_sdp_jesd204b_bus_w   : NATURAL := 12;
   CONSTANT c_sdp_jesd204b_nof_bus : NATURAL := 1;
 
-
   -- AIT MM address widths
   CONSTANT c_sdp_jesd204b_addr_w               : NATURAL := 8 + ceil_log2(c_sdp_S_pn); 
   CONSTANT c_sdp_reg_bsn_monitor_input_addr_w  : NATURAL := 8;