clock correct

applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc.sdc

@@ -92,10 +92,10 @@ set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_nat
 
 
 # false paths added for the jesd test design
-set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|link_clk}]
-set_false_path -from [get_clocks {*core_pll|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
-set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|frame_clk}]
-set_false_path -from [get_clocks {*core_pll|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*corepll_200MHz|link_clk}]
+set_false_path -from [get_clocks {*corepll_200MHz|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*corepll_200MHz|frame_clk}]
+set_false_path -from [get_clocks {*corepll_200MHz|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
 
 # Constraint on the SYSREF input pin
 #    Adjust this to account for any board trace difference between SYSREF and REFCLK