From 4630e881d3c7db4ecb83fdce2cab20f52ede2d38 Mon Sep 17 00:00:00 2001
From: David Brouwer <dbrouwer@astron.nl>
Date: Thu, 26 Oct 2023 09:24:14 +0200
Subject: [PATCH] Copied from ip_arria10_e2sg/fifo/hdllib.cfg. Changed the
 technology_name from ip_arria10 to ip_agi027_xxxx for hdl_lib_name,
 hdl_library_clause_name, hdl_lib_technology, synth_files. Removed the IPs
 under qsys-generate_ip_libs.

---
 .../technology/ip_agi027_xxxx/fifo/hdllib.cfg | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 libraries/technology/ip_agi027_xxxx/fifo/hdllib.cfg

diff --git a/libraries/technology/ip_agi027_xxxx/fifo/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/fifo/hdllib.cfg
new file mode 100644
index 0000000000..8aa3ed16ba
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/fifo/hdllib.cfg
@@ -0,0 +1,25 @@
+hdl_lib_name = ip_agi027_xxxx_fifo
+hdl_library_clause_name = ip_agi027_xxxx_fifo_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files =
+    ip_agi027_xxxx_fifo_sc.vhd
+    ip_agi027_xxxx_fifo_dc.vhd
+    ip_agi027_xxxx_fifo_dc_mixed_widths.vhd
+    
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+synth_top_level_entity = 
+
+quartus_qsf_files =
+
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
-- 
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