add yaml files for args

boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.system.yaml

+schema_name   : args
+schema_version: 1.0
+schema_type   : fpga
+
+hdl_library_name: unb1_minimal_sopc
+
+fpga_name       : unb1_minimal_sopc
+fpga_description: |
+        "unb1_minimal system for sopc"
+
+peripherals:
+  - peripheral_name: rom_system_info
+    subsystem_name : ''
+    slave_port_names:
+        - rom_system_info
+    parameters:
+      - { name: lock_base_address,  value: 0x1000 }    
+    
+  - peripheral_name: reg_system_info
+  
+    subsystem_name : ''
+    slave_port_names:
+        - pio_system_info
+    parameters:
+      - { name: lock_base_address, value: 0x0 }    
+
+  - peripheral_name: ctrl_unb1_board
+    subsystem_name : ''
+    slave_port_names:
+        - pio_wdi
+
+  - peripheral_name: unb1_board_wdi_reg
+    subsystem_name : ''
+    slave_port_names:
+        - reg_wdi
+  
+  - peripheral_name: eth1g
+    subsystem_name : ''
+    slave_port_names:
+        - avs_eth_0_mms_tse
+        - avs_eth_0_mms_reg
+        - avs_eth_0_mms_ram
+    
+  - peripheral_name: ppsh
+    subsystem_name : ''
+    slave_port_names:
+        - pio_pps
+
+  - peripheral_name: epcs_reg
+    subsystem_name : ''
+    slave_port_names:
+        - reg_epcs
+        - reg_mmdp_ctrl
+        - reg_mmdp_data
+        - reg_dpmm_ctrl
+        - reg_dpmm_data
+    parameters:
+      - { name : g_sim_flash_model, value: FALSE }
+
+  - peripheral_name: remu_reg
+    subsystem_name : ''
+    slave_port_names:
+        - reg_remu
+
+  - peripheral_name: unb1_board_sens_reg
+    subsystem_name : ''
+    slave_port_names:
+        - reg_unb_sens
+    parameters:
+      - { name : g_sim,       value: FALSE }
+      - { name : g_clk_freq,  value: 125E6 }
+      - { name : g_temp_high, value: 85 }

boards/uniboard1/libraries/unb1_board/unb1_board.peripheral.yaml

+schema_name   : args
+schema_version: 1.0
+schema_type   : peripheral
+
+hdl_library_name       : unb1_board
+hdl_library_description: " This is the description for the unb1_board package "
+
+peripherals:
+  -  
+    peripheral_name: rom_system_info
+    slave_ports:
+      - 
+        # rom_system_info
+        slave_prefix : WORK 
+        slave_name   : ROM_SYSTEM_INFO  
+        slave_postfix: REG
+        slave_type   : REG
+        fields:
+          -
+            field_name    : field_rom_info
+            access_mode   : RO
+            address_offset: 0x0
+            number_of_fields: 1024
+            field_description: |
+                "address place for rom_system_info"
+        slave_description: " rom_info  "
+        
+    peripheral_description: |
+        " settings for rom_system_info register "
+  - 
+    peripheral_name: reg_system_info
+    slave_ports:
+      -
+        # reg_system_info
+        slave_prefix : WORK
+        slave_name   : REG_SYSTEM_INFO  
+        slave_postfix: REG
+        slave_type   : REG
+        fields:
+          -
+            field_name    : field_reg_info
+            access_mode   : RO
+            address_offset: 0x0
+            number_of_fields: 31
+            field_description: |
+                "address place for reg_system_info"
+        slave_description: " reg_info "
+        
+    peripheral_description: |
+        " settings for reg_system_info register "
+
+  # peripheral, unb1_board_wdi_reg
+  - 
+    peripheral_name: ctrl_unb1_board
+
+    slave_ports:
+      - 
+        # actual hdl name: unb1_board_wdi_reg
+        slave_prefix : UNB1_BOARD
+        slave_name   : PIO_WDI
+        slave_postfix: REG
+        slave_type   : REG
+        fields:
+          -
+            field_name      : nios_reset
+            access_mode     : WO
+            address_offset  : 0x0
+            number_of_fields: 4
+            field_description: " Reset done by nios "
+         
+        slave_description:  "Reset register, for nios "
+    
+    peripheral_description: " "
+  
+  # peripheral, unb1_board_wdi_reg
+  - 
+    peripheral_name: unb1_board_wdi_reg
+
+    slave_ports:
+      - 
+        # actual hdl name: unb1_board_wdi_reg
+        slave_prefix : UNB1_BOARD
+        slave_name   : WDI
+        slave_postfix: REG
+        slave_type   : REG
+        fields:
+          -
+            field_name    : reset_word
+            access_mode   : WO
+            address_offset: 0x0
+            field_description: " Only the value 0xB007FAC7 'Boot factory' will result in a reset "
+         
+        slave_description:  "Reset register, if the right value is provided the factory image will be reloaded "
+    
+    peripheral_description: " "
+  
+  # periheral, unb1_board_sens
+  - 
+    peripheral_name: unb1_board_sens_reg
+
+    parameters:
+      - { name: g_sim,       value: FALSE }
+      - { name: g_clk_freq,  value: c_unb1_board_mm_clk_freq_125M }
+      - { name: g_temp_high, value: 85 }
+
+    slave_ports:
+      - 
+        # actual hdl name: reg_unb1_sens
+        slave_prefix : UNB1_BOARD
+        slave_name   : SENS
+        slave_postfix: REG
+        slave_type   : REG
+        fields:
+          -
+            field_name    : sens_data
+            width         : 8
+            access_mode   : RO
+            address_offset: 0x0
+            number_of_fields: 4
+            field_description: | 
+                " data array with sens data 
+                0x0 = fpga temperature in degrees (two's complement) 
+                0x1 = eth_temp temperature in degrees (two's complement)
+                0x2 = hot_swap_v_sens
+                0x3 = hot_swap_v_source"
+        
+          -
+            field_name    : sens_err
+            width         : 1
+            access_mode   : RO
+            address_offset: 0x4
+            radix         : unsigned 
+            field_description: ""
+        
+          -
+            field_name    : temp_high
+            width         : 7
+            address_offset: 0x5
+            reset_value   : g_temp_high
+            software_value: g_temp_high
+            field_description: ""
+
+        slave_description:  " "
+    
+    peripheral_description: |
+        "
+        +-----------------------------------------------------------------------------+
+        |31   (byte3)   24|23   (byte2)   16|15   (byte1)    8|7    (byte0)    0|  wi |
+        |-----------------------------------------------------------------------|-----|
+        |                xxx                     fpga_temp   = sens_data[0][7:0]|  0  |
+        |-----------------------------------------------------------------------|-----|
+        |                xxx                     eth_temp    = sens_data[1][7:0]|  1  |
+        |-----------------------------------------------------------------------|-----|
+        |                xxx               hot_swap_v_sense  = sens_data[2][7:0]|  2  |
+        |-----------------------------------------------------------------------|-----|
+        |                xxx               hot_swap_v_source = sens_data[3][7:0]|  3  |
+        |-----------------------------------------------------------------------|-----|
+        |                xxx                                         sens_err[0]|  4  |
+        |-----------------------------------------------------------------------|-----|
+        |                xxx                                      temp_high[6:0]|  5  |
+        +-----------------------------------------------------------------------------+
+        * The fpga_temp and eth_temp are in degrees (two's complement)
+        * The hot swap voltages depend on:
+            . From i2c_dev_ltc4260_pkg:
+                LTC4260_V_UNIT_SENSE        = 0.0003  --   0.3 mV over Rs for current sense
+                LTC4260_V_UNIT_SOURCE       = 0.4     -- 400   mV supply voltage (e.g +48 V)
+                LTC4260_V_UNIT_ADIN         = 0.01    --  10   mV ADC
+     
+            . From UniBoard unb_sensors.h:
+                SENS_HOT_SWAP_R_SENSE       = 0.005   -- R sense on UniBoard is 5 mOhm (~= 10 mOhm // 10 mOhm)
+                SENS_HOT_SWAP_I_UNIT_SENSE  = LTC4260_V_UNIT_SENSE / SENS_HOT_SWAP_R_SENSE
+                SENS_HOT_SWAP_V_UNIT_SOURCE = LTC4260_V_UNIT_SOURCE
+     
+        ==> 
+            Via all FN and BN:
+            0 = FPGA temperature                 = TInt8(fpga_temp)
+            Only via BN3:
+            1 = UniBoard ETH PHY temperature     = TInt8(eth_temp)
+            2 = UniBoard hot swap supply current = hot_swap_v_sense * SENS_HOT_SWAP_I_UNIT_SENSE
+            3 = UniBoard hot swap supply voltage = hot_swap_v_source * SENS_HOT_SWAP_V_UNIT_SOURCE
+            4 = I2C error status for BN3 sensors access only, 0 = ok"
+    

libraries/base/diag/diag.peripheral.yaml

+schema_name   : args
+schema_version: 1.0
+schema_type   : peripheral
+
+hdl_library_name       : diag
+hdl_library_description: " This is the description for the bf package "
+
+peripherals:
+  - 
+    peripheral_name:  diag_block_gen
+
+    parameters:
+      - { name: g_nof_streams, value: 1 }
+      - { name: g_buf_dat_w  , value: 32 }
+      - { name: g_buf_addr_w , value: 7 }
+
+    slave_ports:
+      - 
+        # actual hdl name: reg_diag_bg 
+        slave_prefix : DIAG 
+        slave_name   : BG  
+        slave_postfix: REG
+        slave_type : REG
+        fields:
+          - 
+            field_name    : Enable
+            width         : 2
+            address_offset: 0x0
+            field_description: |
+                "Bit 0: enable the block generator Bit 1: enable the blok generator on PPS"
+          - 
+            field_name    :     Samples_per_packet
+            width         : 16
+            address_offset: 0x1
+            reset_value   : 256
+            field_description: |
+                "This REG specifies the number samples in a packet"
+          - 
+            field_name    :     Blocks_per_sync
+            width         : 16
+            address_offset: 0x2
+            reset_value   : 781250
+            field_description: |
+                "This REG specifies the number of packets in a sync period"
+          - 
+            field_name    :     Gapsize
+            width         : 16
+            address_offset: 0x3
+            reset_value   : 80
+            field_description: |
+                "This REG specifies the gap in number of clock cycles between two consecutive packets"
+          - 
+            field_name    :     Mem_low_address
+            width         : 8
+            address_offset: 0x4
+            field_description: |
+                "This REG specifies the starting address for reading from the waveform memory"
+          - 
+            field_name    :     Mem_high_address
+            width         : 8
+            address_offset: 0x5
+            field_description: |
+                "This REG specifies the last address to be read when from the waveform memory"
+          - 
+            field_name    :     BSN_init_low
+            address_offset: 0x6
+            field_description: |
+                "This REG specifies the lower(LSB) 32 bits [31:0] of the initialization BSN"
+          - 
+            field_name    :     BSN_init_high
+            address_offset: 0x7
+            field_description: |
+                "This REG specifies the higher(MSB) 32 bits [63:32] of the initialization BSN"
+      - 
+        # actual hdl name: ram_diag_bg
+        slave_prefix : DIAG 
+        slave_name   : BG  
+        slave_postfix: RAM
+        number_of_slaves: g_nof_streams
+        slave_type      : RAM
+        fields:
+          - 
+            field_name: diag_bg
+            width: g_buf_dat_w
+            number_of_fields: 2**g_buf_addr_w
+            field_description  : |
+                "Contains the Waveform data for the data-streams to be send"
+    peripheral_description: |
+        "Block generator"
+  - 
+    peripheral_name: diag_data_buffer
+
+    parameters:
+      -  { name: g_nof_streams , value: 1 }
+      -  { name: g_data_w      , value: 32 }
+      -  { name: g_buf_nof_data, value: 1024 }
+    
+    slave_ports:
+      - 
+        # actual hdl name: reg_diag_data_buffer
+        slave_prefix : DIAG 
+        slave_name   : DATA_BUFFER  
+        slave_postfix: REG
+        slave_type   : REG
+        fields:
+          - 
+            field_name    : Sync_cnt
+            access_mode   : RO
+            address_offset: 0x0
+            field_description: |
+                "Sync_cnt contains the nof times the buffer (ST) has received a sync pulse since the last MM read
+                (cleared when the last data word from the buffer is read)"
+          - 
+            field_name    : Word_cnt
+            access_mode   : RO
+            address_offset: 0x1
+            field_description: |
+                "Word_cnt indicates the number of word currently (ST) written in the buffer. Cleared on (ST) re-write of buffer."
+          - 
+            field_name    : Valid_cnt_arm_ena
+            address_offset: 0x2
+            field_description: |
+                "Valid_cnt contains the number of valid cycles since the last sync pulse. Cleared on every sync pulse.
+                Arm_enable: Write to this REG to arm the system.
+                After the system is armed the next syn pulse will trigger the acquisition of data."
+          - 
+            field_name    : Reg_sync_delay
+            address_offset: 0x3
+            field_description: |
+                "Reg_sync_delay contains the number of valid cycles to delay/wait after an armed-syncpulse,
+                before the data is written to the databuffer."
+          - 
+            field_name    : Version
+            access_mode   : RO
+            address_offset: 0x7
+            field_description: |
+                "Version contains the version number of the databuffer peripheral."
+        slave_description: ""
+      - 
+        # actual hdl name: ram_diag_data_buffer
+        slave_prefix : DIAG 
+        slave_name   : DATA_BUFFER  
+        slave_postfix: RAM    
+        number_of_slaves: g_nof_streams
+        slave_type      : RAM
+        fields:
+          - 
+            field_name    : ram
+            width         : g_data_w
+            number_of_fields: g_buf_nof_data
+            field_description: |
+                "Contains the data that is being captured."
+        slave_description: ""
+
+    peripheral_description: |
+        "Peripheral diag_data_buffer
+        
+        Memory map RAM_DIAG_DATA_BUFFER
+        
+        If there is only one instance then the RAM name is RAM_DIAG_DATA_BUFFER, else it
+        gets an instanceName as post fix so RAM_DIAG_DATA_BUFFER_<instanceName|.
+        
+        The diag_data_buffer can store multiple streams in parallel. For example
+        1024 data words for 16 streams the memory map becomes:      16
+        
+        
+        streamNr = 0:
+        +------------------------------------------------------------+
+        |   byte 3   |   byte 2   |   byte 1   |   byte 0   |   wi   |
+        |------------------------------------------------------------|
+        |                   data_0[31:0]                    |  0     |
+        |                   data_1[31:0]                    |  1     |
+        |                   ...                             |  ..    |
+        |                data_1023[31:0]                    |  1023  |
+        +------------------------------------------------------------+
+        
+        
+        streamNr = 1:                                                                    
+        +------------------------------------------------------------+
+        |   byte 3   |   byte 2   |   byte 1   |   byte 0   |   wi   |
+        |------------------------------------------------------------|
+        |                   data_0[31:0]                    |  1024  |
+        |                   data_1[31:0]                    |  1025  |
+        |                   ...                             |  ..    |
+        |                data_1023[31:0]                    |  2047  |
+        +------------------------------------------------------------+
+        
+        
+        streamNr = 15:                                                                   
+        +------------------------------------------------------------+
+        |   byte 3   |   byte 2   |   byte 1   |   byte 0   |   wi   |
+        |------------------------------------------------------------|
+        |                   data_0[31:0]                    |  15360 |
+        |                   data_1[31:0]                    |  15361 |
+        |                   ...                             |  ..    |
+        |                data_1023[31:0]                    |  16383 |
+        +------------------------------------------------------------+
+        
+        
+        Remarks:
+        - The data buffer stores valid data samples until it is full.
+        - The data buffer fills again after an external sync pulse or after the
+            last data word was read via the MM bus, dependend on whether the generic
+            g_use_in_sync is TRUE or FALSE in diag_data_buffer.vhd.
+        - The actual data width depends on the generic g_data_w in
+            diag_data_buffer.vhd. The value of unused MSBits is undefined.
+        
+        
+        Memory map REG_DIAG_DATA_BUFFER (one for each stream like the RAM above)
+        
+        +----------------------------------------------------------------------------+
+        |   byte 3   |   byte 2   |   byte 1   |   byte 0   |  wi                    |
+        |----------------------------------------------------------------------------|
+        |                  sync_cnt[31:0]                   | 0 RO (Version 0 and 1) |
+        |                  word_cnt[31:0]                   | 1 RO (Version 0 and 1) |
+        |        R = valid_cnt[31:0] W = arm_enable         | 2 RW (Version 1 only)  |
+        |               reg_sync_delay[31:0]                | 3 RW (Version 1 only)  | 
+        |                     RESERVED                      | 4    (Version 1 only)  |
+        |                     RESERVED                      | 5    (Version 1 only)  |
+        |                     RESERVED                      | 6    (Version 1 only)  |
+        |                  version[31:0]                    | 7 RO (Version 1 only)  |
+        +----------------------------------------------------------------------------+
+        
+        
+        There are 3 access_modes of operation of the data_buffer.
+        Version 0 supports access_Mode 1 and access_Mode 2
+        Version 1 supports access_Mode 1, access_Mode 2 and access_Mode 3
+        
+        (1) NON-SYNC access_MODE: g_use_in_sync = FALSE
+        In this access_mode the first g_nof_data valid data input words are stored in the
+        data buffer. A new set of data will be stored when the last word is read
+        from the buffer via the MM interface.
+        
+        (2) SYNC-access_MODE: g_use_in_sync = TRUE and reg_sync_delay = 0
+        On every received sync pulse a number of g_nof_data valid words are written
+        to the databuffer. Data will be overwritten on every new sync pulse. It is
+        up to the user to read out the data in time in between two sync pulses
+        
+        (3) ARM-access_MODE: g_use_in_sync = TRUE and reg_sync_delay | 0
+        First the reg_sync_delay should be written with a desired delay value. Then
+        the arm REG must be written. After being armed the databuffer will wait
+        for the first sync pulse to arrive. When it has arrived it will wait for
+        reg_sync_delay valid cycles before g_nof_data valid words are written to the
+        databuffer. The data can then be read out through the MM interface. New data
+        will only be written if the databuffer is being armed again.
+        
+        - Sync_cnt contains the nof times the buffer (ST) has received a sync pulse
+            since the last MM read (cleared when the last data word from the buffer is
+            read);
+        - Word_cnt indicates the number of word currently (ST) written in the buffer.
+            Cleared on (ST) re-write of buffer.
+        - valid_cnt contains the number of valid cycles since the last sync pulse.
+            Cleared on every sync pulse.
+        - arm_enable. Write to this REG to arm the system. After the system is
+            armed the next syn pulse will truigger the acquisition of data.
+        - reg_sync_delay contains the number of valid cycles to delay/wait after an armed-syncpulse,
+            before the data is written to the databuffer.
+        - version contains the version number of the databuffer peripheral."

libraries/base/dp/dp.peripheral.yaml

+schema_name   : args
+schema_version: 1.0
+schema_type   : peripheral
+
+hdl_library_name       : dp
+hdl_library_description: " This is the description for the dp package "
+
+peripherals:
+  - 
+    peripheral_name: dp_bsn_align
+
+    parameters:
+        - { name: g_nof_input, value : 2 }
+
+    slave_ports:
+      - 
+        # actual hdl name: reg_dp_bsn_align
+        slave_prefix : DP 
+        slave_name   : BSN_ALIGN  
+        slave_postfix: REG
+        number_of_slaves: g_nof_input
+        slave_type      : REG
+        fields:
+          - 
+            field_name       : Enable
+            width            : 1
+            address_offset   : 0x0
+            field_description: |
+                "Input enable register for input 0. If set to 0 the input is discarded from alignment.
+                    If set to 1 the corresopnding input is taken into account."
+        slave_discription: " "
+            
+    peripheral_description: "This is the BSN aligner"
+  
+  - 
+    peripheral_name: dp_fifo_fill
+    parameters:
+        - { name : g_nof_streams, value: 3 }
+
+    slave_ports:
+      - 
+        # actual hdl name: reg_dp_fifo_fill
+        slave_prefix : DP 
+        slave_name   : FIFO_FILL  
+        slave_postfix: REG
+        number_of_slaves: g_nof_streams
+        slave_type      : REG
+        fields:
+          - 
+            field_name       : fifo_used_words
+            access_mode      : RO
+            address_offset   : 0x0
+            field_description: "Register reflects the currently used nof words on the fifo."
+          - 
+            field_name       : fifo_status
+            width            : 2
+            access_mode      : RO
+            address_offset   : 0x1
+            field_description: "Bit 0: fifo_read_empty Bit 1: fifo_wr_full."
+          - 
+            field_name       : max_fifo_used_words
+            access_mode      : RO
+            address_offset   : 0x2
+            field_description: |
+                "Register contains the maximum number of words that have been in the fifo.
+                    Will be cleared after it has been read."
+        slave_discription: ""
+                
+    peripheral_description: "This is the MM slave version of the dp_fifo_fill component."

libraries/dsp/bf/bf.peripheral.yaml

+schema_name   : args
+schema_version: 1.0
+schema_type   : peripheral
+
+hdl_library_name       : bf
+hdl_library_description: " This is the description for the bf package "
+
+peripherals:
+  - peripheral_name: bf_unit
+ 
+    parameters:
+      - { name: g_bf.in_weights_w            , value: 16 }
+      - { name: g_bf.nof_weights             , value: 256 }
+      - { name: g_bf.nof_signal_paths        , value: 64 }   
+      - { name: g_bf.nof_subbands            , value: 24 } 
+      - { name: g_bf.nof_input_streams       , value: 16 }
+      - { name: c_nof_signal_paths_per_stream, value: g_bf.nof_signal_paths / g_bf.nof_input_streams }
+
+    slave_ports:
+      - 
+        # ram_bf_weights
+        slave_prefix : BF 
+        slave_name   : WEIGHTS 
+        slave_postfix: RAM
+        number_of_slaves: g_bf.nof_weights
+        slave_type: RAM
+        fields:
+          - 
+            field_name    : bf_weights 
+            width         : g_bf.in_weights_w * c_nof_complex
+
+            number_of_fields: g_bf.nof_signal_paths
+            field_description: |
+                        "Contains the weights. 
+                        The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part."
+        slave_discription: >
+                " "
+      
+      - 
+        # ram_ss_ss_wide
+        slave_prefix : BF 
+        slave_name   : SS_SS_WIDE
+        slave_postfix: RAM    
+        number_of_slaves: g_bf.nof_weights
+        slave_type: RAM
+        fields:
+          - 
+            field_name      : ss_ss_wide
+            width           : 32
+            number_of_fields: g_bf.nof_subbands * g_bf.nof_input_streams * c_nof_signal_paths_per_stream  # 16*4=64, nof_input_streams*nof_signal_paths_per_stream
+            field_description: |
+                "Contains the addresses to select from the stored subbands."
+        slave_discription: >
+            " "
+      
+      - 
+        # ram_st_sst_bf
+        slave_prefix : BF 
+        slave_name   : ST_SST
+        slave_postfix: RAM
+        number_of_slaves: g_bf.nof_weights
+        slave_type: RAM 
+        fields:
+          - 
+            field_name      : st_sst_bf
+            width           : 56
+            number_of_fields: 512
+            access_mode : RO   
+            field_description: |
+                "Contains the weights.
+                The real and the imaginary parts are concatenated: W_real in Lower part. W_imag in Higher part."
+        slave_discription: >
+      
+      - 
+        # reg_st_sst_bf
+        slave_prefix : BF 
+        slave_name   : ST_SST
+        slave_postfix: REG
+        number_of_slaves: 1
+        slave_type: REG
+        fields:
+          - 
+            field_name    : treshold
+            address_offset: 0x0
+            field_description  : |
+                "When the treshold register is set to 0 the statistics will be auto-correlations.
+                In case the treshold register is set to a non-zero value, it allows to create a sample & hold function
+                for the a-input of the multiplier. 
+                The a-input of the multiplier is updated every treshold clockcycle. Thereby cross statistics can be created."
+        slave_discription: >
+            " "
+    
+    peripheral_description: |
+        "This is the beamformer unit"

libraries/dsp/fringe_stop/fringe_stop.peripheral.yaml

+schema_name   : args
+schema_version: 1.0
+schema_type   : peripheral
+
+hdl_library_name       : fringe_stop
+hdl_library_description: " This is the description for the finge_stop library "
+
+peripherals:
+  - 
+    peripheral_name: fringe_stop_unit
+
+    parameters:
+      - { name: g_nof_channels,  value: 256 }
+      - { name: g_fs_offset_w ,  value: 10 }
+      - { name: g_fs_step_w   ,  value: 17 }
+    
+    slave_ports:
+      - 
+        # actual hdl name: ram_fringe_stop_step
+        slave_prefix : FRINGE_STOP 
+        slave_name   : STEP  
+        slave_postfix: RAM
+        slave_type   : RAM
+        fields:
+          - 
+            field_name  : fringe_stop_step
+            width: g_fs_step_w
+            number_of_fields: g_nof_channels
+            field_description: |
+                "Contains the step size for all nof_channels channels."
+        slave_discription: " "
+
+      - 
+        # actual hdl name: fringe_stop_offset
+        slave_prefix : FRINGE_STOP 
+        slave_name   : OFFSET  
+        slave_postfix: RAM
+        slave_type   : RAM
+        fields:
+          - 
+            field_name:  fringe_stop_offset
+            width: g_fs_offset_w
+            number_of_fields: g_nof_channels
+            field_description: |
+                "Contains the offset for all nof_channels channels."
+        slave_discription: " "
+
+    peripheral_description: |
+        "The fringe stopping peripheral is based on piecewise linear coefficients. The coefficients are indicated as offset and step.
+        The offset and step are used to calculate an index that is used to select a certain phase from a look-up table. The look-up
+        table contains a series of complex values that are based on a sinewave. The length of the look-up table is determined by the
+        width of the offset RAM (offset_w). If offset_w = 10 then the length of the look-up table is 2^offset_w=1024. In that case
+        the look-up table contains 1024 complex values that make one sine-wave period.
+        
+        The index is determined as follows:
+        
+            index(t) = (offset + step*t) MOD 2^offset_w
+        
+        Where t ranges from 0 to Tmax-1. Tmax is the number of samples that fit in the control interval (the sync interval).
+        The fringe stop peripheral is capable to process 1 or more channels in series (nof_channels).
+        
+        Accumulation Register
+        The accumulation register that maintains the accumulated step value is flushed by the sync pulse in the system.
+        The accumulation register in the Apertif case is 31 bit wide. For the additon of the offset and the accumulated step the
+        10 (offset_w) highest bit of the accumulated value are used --> offset(9:0) + step_accumulated(30:21).
+        
+        RAMs
+        The fringe stop interface is facilitated by two RAMs:
+        
+            -RAM_FRINGE_STOP_OFFSET
+            -RAM_FRINGE_STOP_STEP
+        
+        Both RAMs are implemented as dual-page RAMs.The page swap is triggered by the sync-pulse. The VHDL is always accessing
+        the page that is NOT accessible for the software and vice-versa. This means that the values that are written to the RAMs
+        will only be actually used in the following sync-interval:
+        
+        
+        A|         _             T0              _             T1              _            T2 
+        A| sync __| |___________________________| |___________________________| |________________________
+        A|        |    VHDL uses data T0        |    VHDL uses data T1        |    VHDL uses data T2 
+        A|        |    Software writes data T1  |    Software writes data T2  |    Software writes data T3
+        A|        |                             |                             | 
+        A|    page_swap                     page_swap                     page_swap 
+        
+        
+        The software should be sure to write the next set of data before the sync_interval expires. Keeping track of the
+        synchronization with the sync-pulse can be done, using one of the BSN Monitors in the system. In the Apertif system
+        the BSN Monitor at the input of the beamformer can be used.
+        
+        The number_of_fields of both RAMs is determined by the number of unique channels that ought to be processed.
+        
+        RAM_FRINGE_STOP_OFFSET
+        This RAM contains the offset values for all channels, ranging from Channel 0 to Channel Max-1. The width of the RAM is
+        defined by the offset_w.
+        
+        +-----------------------------------------+
+        | RAM_address     | RAM_content           | 
+        |-----------------------------------------|
+        |   0x0           | Offset_Channel_0      |
+        |   0x1           | Offset_Channel_1      |
+        |   0x2           | Offset_Channel_2      |
+        |   0x3           | Offset_Channel_3      |
+        |   ..            |       ..              |
+        |   ..            | Offset_Channel_Max-1  |
+        +-----------------------------------------+
+        
+        RAM_FRINGE_STOP_STEP
+        This RAM contains the step size values for all channels, ranging from Channel 0 to Channel Max-1. The width of the RAM is
+        specified by the step_w.
+        
+        +-----------------------------------------+
+        | RAM_address     | RAM_content           | 
+        |-----------------------------------------|
+        |   0x0           | Step_Channel_0        |
+        |   0x1           | Step_Channel_1        |
+        |   0x2           | Step_Channel_2        |
+        |   0x3           | Step_Channel_3        |
+        |   ..            |       ..              |
+        |   ..            | Step_Channel_Max-1    |
+        +-----------------------------------------+"
+        

libraries/io/epcs/epcs.peripheral.yaml

+schema_name   : args
+schema_version: 1.0
+schema_type   : peripheral
+
+hdl_library_name       : epcs
+hdl_library_description: " This is the description for the epcs package "
+
+peripherals:
+ 
+  # epcs_reg
+  - 
+    peripheral_name: epcs_reg
+
+    parameters:
+      - {name: "g_sim_flash_model", value: TRUE} 
+
+    slave_ports:
+      - 
+        # actual hdl name: epcs_reg
+        slave_prefix : EPCS
+        slave_name   : EPCS
+        slave_postfix: REG
+        slave_type   : REG
+        fields:
+          -
+            field_name    : addr
+            width         : 24
+            access_mode   : WO
+            address_offset: 0x0
+            field_description: " address to write to or read from "
+        
+          -
+            field_name    : rden
+            width         : 1
+            access_mode   : WO
+            address_offset: 0x1
+            field_description: " Read enable bit "
+        
+          -
+            field_name    : read_bit
+            width         : 1
+            access_mode   : WO
+            side_effect   : PW
+            address_offset: 0x2
+            field_description: " Read bit "
+
+          -
+            field_name    : write_bit
+            width         : 1
+            access_mode   : WO
+            side_effect   : PW
+            address_offset: 0x3
+            field_description: " Write bit "
+
+          -
+            field_name    : sector_erase
+            width         : 1
+            access_mode   : WO
+            address_offset: 0x4
+            field_description: " Sector erase bit "
+
+          -
+            field_name    : busy
+            width         : 1
+            access_mode   : RO
+            address_offset: 0x5
+            field_description: " busy "
+
+        slave_description:  " Read and write access to flash "
+
+      # actual hdl name: mms_dp_fifo_to_mm
+      - 
+        slave_prefix : EPCS
+        slave_name   : DPMM_CTRL
+        slave_postfix: REG
+        slave_type   : REG
+        fields:
+          -
+            field_name    : ctrl
+            width         : 32
+            access_mode   : RW
+            address_offset: 0x0
+            field_description: "  "
+      
+      -   
+        slave_prefix : EPCS
+        slave_name   : DPMM_DATA
+        slave_postfix: REG
+        slave_type   : REG
+        fields:
+          -
+            field_name    : data
+            width         : 32
+            access_mode   : RW
+            address_offset: 0x0
+            field_description: "  "
+
+      # actual hdl name: mms_dp_fifo_from_mm
+      - 
+        slave_prefix : EPCS
+        slave_name   : MMDP_CTRL
+        slave_postfix: REG
+        slave_type   : REG
+        fields:
+          -
+            field_name    : ctrl
+            width         : 32
+            access_mode   : RW
+            address_offset: 0x0
+            field_description: "  "
+      
+      -  
+        slave_prefix : EPCS
+        slave_name   : MMDP_DATA
+        slave_postfix: REG
+        slave_type   : REG
+        fields:
+          -
+            field_name    : data
+            width         : 32
+            access_mode   : RW
+            address_offset: 0x0
+            field_description: "  "
+    
+    peripheral_description: |
+        "wi  Bits     SE  R/W Name              Default  Description         |REG_EPCS|                      
+        =============================================================================
+        0   [23..0]      WO  addr              0x0      Address to write to/read from
+        1   [0]          WO  rden              0x0      Read enable
+        2   [0]      PW  WE  read              0x0      Read 
+        3   [0]      PW  WE  write             0x0      Write 
+        4   [0]          WO  sector_erase      0x0      Sector erase
+        5   [0]          RO  busy              0x0      Busy
+        ============================================================================="
+        
\ No newline at end of file

libraries/io/eth/eth.peripheral.yaml

+schema_name   : args
+schema_version: 1.0
+schema_type   : peripheral
+
+hdl_library_name       : eth
+hdl_library_description: " This is the description for the eth package "
+
+peripherals:
+  - 
+    peripheral_name: eth1g
+    
+    parameters:
+      - { name: c_eth_ram_nof_words,  value: 1024 }
+        #g_technology: c_tech_select_default
+        #g_ETH_PHY   : "LVDS" 
+
+    slave_ports:
+      - 
+        # actual hdl name: reg_tse
+        slave_prefix : ETH 
+        slave_name   : TSE  
+        slave_postfix: REG
+        slave_type   : REG
+        fields:
+          - 
+            field_name      : status
+            access_mode     : RO
+            address_offset  : 0x0
+            number_of_fields: 1024
+            field_description: | 
+                " reg tse "
+        slave_description: ""
+      - 
+        # actual hdl name: reg
+        slave_prefix : ETH 
+        slave_name   : REG  
+        slave_postfix: REG
+        slave_type   : REG    
+        fields:
+          - 
+            field_name      : status
+            access_mode     : RO
+            address_offset  : 0x0
+            number_of_fields: 11
+            field_description: " reg registers "
+        slave_description: " "
+      - 
+        # actual hdl name: ram
+        slave_prefix : ETH 
+        slave_name   : RAM  
+        slave_postfix: RAM
+        slave_type   : RAM
+        fields:
+          - 
+            field_name      : ram
+            number_of_fields: c_eth_ram_nof_words
+            field_description: |
+                "Contains the Waveform data for the data-streams to be send"
+        slave_description: " "
+
+    peripheral_description: |
+        "
+        Connect the 1GbE TSE to the microprocessor and to streaming UDP ports. The
+        packets for the streaming channels are directed based on the UDP port
+        number and all other packets are transfered to the default control channel."
+    

libraries/io/ppsh/ppsh.peripheral.yaml

+schema_name   : args
+schema_version: 1.0
+schema_type   : peripheral
+
+hdl_library_name       : ppsh
+hdl_library_description: " This is the description for the finppshge_stop library "
+
+peripherals: 
+  - 
+    peripheral_name: ppsh
+    parameters:
+      - { name: g_cross_clock_domain, value: TRUE }
+      - { name: g_st_clk_freq,        value: 200 * 10**6 }
+    
+    slave_ports:
+      - 
+        # actual hdl name: reg_ppsh
+        slave_prefix : PPSH 
+        slave_name   : PPSH  
+        slave_postfix: REG
+        slave_type   : REG
+        fields:
+          - 
+            field_name    : status
+            access_mode   : RO
+            address_offset: 0x0
+            field_description: " ppsh status "
+          - 
+            field_name    : control
+            address_offset: 0x1
+            field_description: " ppsh control "
+        slave_discription: " "
+    
+    peripheral_description: |
+        "
+        . Report PPS toggle, stable and period capture count
+        . Set dp_clk capture edge for PPS
+          Set expected period capture count for PPS stable
+         +----------------------------------------------------------------------------+
+         |31   (byte3)   24|23   (byte2)   16|15   (byte1)    8|7    (byte0)    0| wi |
+         |-----------------------------------------------------------------------|----| 
+         |toggle[31], stable[30]   xxx                       capture_cnt = [29:0]|  0 |
+         |-----------------------------------------------------------------------|----|
+         |edge[31],                xxx                      expected_cnt = [29:0]|  1 |
+         +----------------------------------------------------------------------------+"
+    

libraries/io/remu/remu.peripheral.yaml

+schema_name   : args
+schema_version: 1.0
+schema_type   : peripheral
+
+hdl_library_name       : remu
+hdl_library_description: " This is the description for the remu package "
+
+peripherals:
+ 
+  # peripheral, remu_reg
+  - 
+    peripheral_name: remu_reg
+
+    parameters:
+      - { name: g_data_w, value: 24 }
+
+    slave_ports:
+      - 
+        # actual hdl name: reg_remu
+        slave_prefix : WORK
+        slave_name   : REMU
+        slave_postfix: REG
+        slave_type   : REG
+        fields:
+          -
+            field_name    : reconfigure_key
+            width         : c_word_w
+            access_mode   : WO
+            address_offset: 0x0
+            field_description: " reconfigure key for safety "
+        
+          -
+            field_name    : param
+            width         : 3
+            access_mode   : WO
+            address_offset: 0x1
+            radix         : unsigned 
+            field_description: " "
+        
+          -
+            field_name    : read_param
+            width         : 1
+            access_mode   : WO
+            side_effect   : PW
+            address_offset: 0x2
+            field_description: " read_param "
+
+          -
+            field_name    : write_param
+            width         : 1
+            access_mode   : WO
+            side_effect   : PW
+            address_offset: 0x3
+            field_description: " write_param "
+
+          -
+            field_name    : data_out
+            width         : g_data_w
+            access_mode   : RO
+            address_offset: 0x4
+            field_description: " data_out "
+
+          -
+            field_name    : data_in
+            width         : g_data_w
+            access_mode   : WO
+            address_offset: 0x5
+            field_description: " data_in "
+
+          -
+            field_name    : busy
+            width         : 1
+            access_mode   : RO
+            address_offset: 0x6
+            field_description: " busy "
+
+        slave_description:  " Remote Upgrade "
+    
+    peripheral_description: |
+        "wi  Bits    R/W  SE  Name              Default  Description             |REG_EPCS|                      
+         =============================================================================
+         0   [31..0] WO       reconfigure_key   0x0
+         1   [2..0]  WO       param
+         2   [0]     WO   PW  read_param
+         3   [0]     WO   PW  write_param 
+         4   [23..0] RO       data_out
+         5   [23..0] WO       data_in
+         6   [0]     RO       busy
+         =============================================================================
+        "