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RTSD
HDL
Commits
4203e433
Commit
4203e433
authored
3 years ago
by
Eric Kooistra
Browse files
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Downloads
Patches
Plain Diff
Made tb self checking.
parent
fb37dfc9
No related branches found
No related tags found
1 merge request
!185
Resolve L2SDP-563
Pipeline
#23275
passed
3 years ago
Stage: simulation
Stage: synthesis
Changes
2
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1
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libraries/technology/jesd204b/hdllib.cfg
+1
-4
1 addition, 4 deletions
libraries/technology/jesd204b/hdllib.cfg
libraries/technology/jesd204b/tb_tech_jesd204b.vhd
+59
-48
59 additions, 48 deletions
libraries/technology/jesd204b/tb_tech_jesd204b.vhd
with
60 additions
and
52 deletions
libraries/technology/jesd204b/hdllib.cfg
+
1
−
4
View file @
4203e433
...
@@ -19,13 +19,10 @@ test_bench_files =
...
@@ -19,13 +19,10 @@ test_bench_files =
tb_tech_jesd204b.vhd
tb_tech_jesd204b.vhd
regression_test_vhdl
=
regression_test_vhdl
=
# FIXME: broken, need fixing
tb_tech_jesd204b.vhd
# tb_tech_jesd204b.vhd
[modelsim_project_file]
[modelsim_project_file]
modelsim_copy_files
=
modelsim_copy_files
=
wave_tb_tech_jesd204b.do
.
wave_tb_tech_jesd204b.do
.
[quartus_project_file]
[quartus_project_file]
This diff is collapsed.
Click to expand it.
libraries/technology/jesd204b/tb_tech_jesd204b.vhd
+
59
−
48
View file @
4203e433
...
@@ -24,12 +24,14 @@
...
@@ -24,12 +24,14 @@
-- Includes 3 JESD transmit sources to test multichannel syncronization
-- Includes 3 JESD transmit sources to test multichannel syncronization
-- Relative delays between TX and RX channels can be varied by editing c_delay_*
-- Relative delays between TX and RX channels can be varied by editing c_delay_*
-- Used default technology e1sg
-- Used default technology e1sg
-- TODO:
-- Remark:
-- Make a tb_tb to run several test cases automatically
-- The self checking is minimal. It only checks that Tx data from the DAC in
-- the tb does come out the JESD Rx. Some more data and strobe testing would
-- be nice, but is not needed because it works on HW.
-- Usage:
-- Usage:
-- Load sim # check that design can load in vsim
-- Load sim # check that design can load in vsim
-- > as 3 # check that the hierarchy for g_design_name is complete (or use do wave_tb_tech_jesd204b.do)
-- > as 3 # check that the hierarchy for g_design_name is complete (or use do wave_tb_tech_jesd204b.do)
-- > run
120us
# enough time to reset and syncronize the JESD IP
-- > run
-a
# enough time to reset and syncronize the JESD IP
LIBRARY
IEEE
,
common_lib
,
dp_lib
;
LIBRARY
IEEE
,
common_lib
,
dp_lib
;
USE
IEEE
.
std_logic_1164
.
ALL
;
USE
IEEE
.
std_logic_1164
.
ALL
;
...
@@ -56,8 +58,9 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
...
@@ -56,8 +58,9 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
CONSTANT
c_nof_streams_jesd204b
:
NATURAL
:
=
12
;
-- number of jesd204b receiver channels
CONSTANT
c_nof_streams_jesd204b
:
NATURAL
:
=
12
;
-- number of jesd204b receiver channels
CONSTANT
c_jesd204b_rx_data_w
:
NATURAL
:
=
32
;
CONSTANT
c_jesd204b_rx_data_w
:
NATURAL
:
=
32
;
CONSTANT
c_jesd204b_rx_framer_data_w
:
NATURAL
:
=
c_jesd204b_rx_data_w
/
2
;
-- IP outputs two samples in parallel
CONSTANT
c_jesd204b_rx_somf_w
:
NATURAL
:
=
c_jesd204b_rx_data_w
/
8
;
-- One somf bit per octet
CONSTANT
c_jesd204b_rx_somf_w
:
NATURAL
:
=
c_jesd204b_rx_data_w
/
8
;
-- One somf bit per octet
CONSTANT
c_jesd204b_rx_framer_data_w
:
NATURAL
:
=
c_jesd204b_rx_data_w
/
2
;
-- IP outputs two samples in parallel
CONSTANT
c_jesd204b_rx_framer_somf_w
:
NATURAL
:
=
c_jesd204b_rx_somf_w
/
2
;
-- IP outputs two samples in parallel
-- Transport delays
-- Transport delays
TYPE
t_time_arr
IS
ARRAY
(
0
TO
c_nof_streams_jesd204b
-1
)
OF
TIME
;
TYPE
t_time_arr
IS
ARRAY
(
0
TO
c_nof_streams_jesd204b
-1
)
OF
TIME
;
...
@@ -87,8 +90,6 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
...
@@ -87,8 +90,6 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
1000
ps
)
;
-- transport delays clock source to adc(tx)
1000
ps
)
;
-- transport delays clock source to adc(tx)
CONSTANT
c_delay_sysreftofpga
:
TIME
:
=
10200
ps
;
CONSTANT
c_delay_sysreftofpga
:
TIME
:
=
10200
ps
;
-- clocks and resets for the jesd204b tx
-- clocks and resets for the jesd204b tx
SIGNAL
txlink_clk
:
STD_LOGIC_VECTOR
(
c_nof_jesd204b_tx
-1
downto
0
);
SIGNAL
txlink_clk
:
STD_LOGIC_VECTOR
(
c_nof_jesd204b_tx
-1
downto
0
);
SIGNAL
dev_sync_n
:
STD_LOGIC_VECTOR
(
c_nof_jesd204b_tx
-1
downto
0
);
SIGNAL
dev_sync_n
:
STD_LOGIC_VECTOR
(
c_nof_jesd204b_tx
-1
downto
0
);
...
@@ -112,6 +113,7 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
...
@@ -112,6 +113,7 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
-- Tb
-- Tb
SIGNAL
tb_end
:
STD_LOGIC
:
=
'0'
;
SIGNAL
tb_end
:
STD_LOGIC
:
=
'0'
;
SIGNAL
tb_timeout
:
STD_LOGIC
:
=
'0'
;
SIGNAL
sim_done
:
STD_LOGIC
:
=
'0'
;
SIGNAL
sim_done
:
STD_LOGIC
:
=
'0'
;
-- mm control buses
-- mm control buses
...
@@ -131,13 +133,15 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
...
@@ -131,13 +133,15 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
SIGNAL
rx_sysref
:
STD_LOGIC
:
=
'0'
;
SIGNAL
rx_sysref
:
STD_LOGIC
:
=
'0'
;
SIGNAL
rx_sosi_arr
:
t_dp_sosi_arr
(
c_nof_streams_jesd204b
-1
DOWNTO
0
);
SIGNAL
rx_sosi_arr
:
t_dp_sosi_arr
(
c_nof_streams_jesd204b
-1
DOWNTO
0
);
-- Debug signals for rx_sosi_arr
SIGNAL
rx_sosi
:
t_dp_sosi
;
SIGNAL
rx_sosi
:
t_dp_sosi
;
SIGNAL
rx_sosi_data
:
STD_LOGIC_VECTOR
(
c_jesd204b_rx_framer_data_w
-1
DOWNTO
0
);
-- 16 bit samples
SIGNAL
rx_sosi_data
:
STD_LOGIC_VECTOR
(
c_jesd204b_rx_framer_data_w
-1
DOWNTO
0
);
-- 16 bit samples
SIGNAL
rx_sosi_channel
:
STD_LOGIC_VECTOR
(
c_jesd204b_rx_somf_w
-1
DOWNTO
0
);
SIGNAL
rx_sosi_channel
:
STD_LOGIC_VECTOR
(
c_jesd204b_rx_
framer_
somf_w
-1
DOWNTO
0
);
-- two samples
SIGNAL
rx_sosi_valid
:
STD_LOGIC
;
SIGNAL
rx_sosi_valid
:
STD_LOGIC
;
SIGNAL
rx_sosi_sync
:
STD_LOGIC
;
SIGNAL
rx_sosi_sync
:
STD_LOGIC
;
SIGNAL
rx_sosi_sop
:
STD_LOGIC
;
SIGNAL
rx_sosi_sop
:
STD_LOGIC
;
SIGNAL
rx_sosi_eop
:
STD_LOGIC
;
SIGNAL
rx_sosi_eop
:
STD_LOGIC
;
SIGNAL
rx_sosi_valid_arr
:
STD_LOGIC_VECTOR
(
c_nof_streams_jesd204b
-1
DOWNTO
0
);
SIGNAL
jesd204b_sampclk_fpga
:
STD_LOGIC
:
=
'1'
;
SIGNAL
jesd204b_sampclk_fpga
:
STD_LOGIC
:
=
'1'
;
SIGNAL
jesd204b_sampclk_adc
:
STD_LOGIC_VECTOR
(
c_nof_streams_jesd204b
-1
DOWNTO
0
);
SIGNAL
jesd204b_sampclk_adc
:
STD_LOGIC_VECTOR
(
c_nof_streams_jesd204b
-1
DOWNTO
0
);
...
@@ -285,45 +289,42 @@ BEGIN
...
@@ -285,45 +289,42 @@ BEGIN
-- Generate test pattern at each ADC
-- Generate test pattern at each ADC
proc_data
:
PROCESS
(
jesd204b_sampclk_adc
(
i
),
mm_rst
)
proc_data
:
PROCESS
(
jesd204b_sampclk_adc
(
i
),
mm_rst
)
VARIABLE
data
:
INTEGER
:
=
0
;
VARIABLE
v_
data
:
INTEGER
:
=
0
;
VARIABLE
even_sample
:
BOOLEAN
:
=
TRUE
;
VARIABLE
v_
even_sample
:
BOOLEAN
:
=
TRUE
;
BEGIN
BEGIN
IF
mm_rst
=
'1'
THEN
IF
mm_rst
=
'1'
THEN
jesd204b_tx_link_data_arr
(
i
)
<=
(
others
=>
'0'
);
jesd204b_tx_link_data_arr
(
i
)
<=
(
others
=>
'0'
);
jesd204b_tx_link_valid
(
i
)
<=
'0'
;
jesd204b_tx_link_valid
(
i
)
<=
'0'
;
txlink_clk
(
i
)
<=
'0'
;
txlink_clk
(
i
)
<=
'0'
;
data
:
=
0
;
v_data
:
=
0
;
even_sample
:
=
TRUE
;
v_even_sample
:
=
TRUE
;
ELSE
ELSIF
rising_edge
(
jesd204b_sampclk_adc
(
i
))
THEN
IF
rising_edge
(
jesd204b_sampclk_adc
(
i
))
THEN
txlink_clk
(
i
)
<=
not
txlink_clk
(
i
);
txlink_clk
(
i
)
<=
not
txlink_clk
(
i
);
jesd204b_sysref_adc_1
(
i
)
<=
jesd204b_sysref_adc
(
i
);
jesd204b_sysref_adc_1
(
i
)
<=
jesd204b_sysref_adc
(
i
);
jesd204b_sysref_adc_2
(
i
)
<=
jesd204b_sysref_adc_1
(
i
);
jesd204b_sysref_adc_2
(
i
)
<=
jesd204b_sysref_adc_1
(
i
);
--generate a positive and negative going pulse after the rising edge of SYSREF
--generate a positive and negative going pulse after the rising edge of SYSREF
IF
(
jesd204b_sysref_adc
(
i
)
=
'1'
and
jesd204b_sysref_adc_1
(
i
)
=
'0'
)
THEN
IF
(
jesd204b_sysref_adc
(
i
)
=
'1'
and
jesd204b_sysref_adc_1
(
i
)
=
'0'
)
THEN
data
:
=
1000
;
v_
data
:
=
1000
;
ELSIF
(
jesd204b_sysref_adc_1
(
i
)
=
'1'
and
jesd204b_sysref_adc_2
(
i
)
=
'0'
)
THEN
ELSIF
(
jesd204b_sysref_adc_1
(
i
)
=
'1'
and
jesd204b_sysref_adc_2
(
i
)
=
'0'
)
THEN
data
:
=
-1000
;
v_
data
:
=
-1000
;
ELSE
ELSE
data
:
=
0
;
v_
data
:
=
0
;
END
IF
;
END
IF
;
-- Frame the data to 32 bits at half the rate
-- Frame the data to 32 bits at half the rate
IF
(
jesd204b_tx_link_ready
(
i
)
=
'0'
)
THEN
IF
(
jesd204b_tx_link_ready
(
i
)
=
'0'
)
THEN
even_sample
:
=
TRUE
;
v_
even_sample
:
=
TRUE
;
ELSE
ELSE
even_sample
:
=
not
even_sample
;
v_
even_sample
:
=
not
v_
even_sample
;
END
IF
;
END
IF
;
IF
(
even_sample
=
TRUE
)
THEN
IF
(
v_
even_sample
=
TRUE
)
THEN
jesd204b_tx_link_data_arr
(
i
)(
15
downto
0
)
<=
TO_SVEC
(
data
,
16
);
jesd204b_tx_link_data_arr
(
i
)(
15
downto
0
)
<=
TO_SVEC
(
v_
data
,
16
);
jesd204b_tx_link_valid
(
i
)
<=
'0'
;
jesd204b_tx_link_valid
(
i
)
<=
'0'
;
ELSE
ELSE
jesd204b_tx_link_data_arr
(
i
)(
31
downto
16
)
<=
TO_SVEC
(
data
,
16
);
jesd204b_tx_link_data_arr
(
i
)(
31
downto
16
)
<=
TO_SVEC
(
v_
data
,
16
);
jesd204b_tx_link_valid
(
i
)
<=
'1'
;
jesd204b_tx_link_valid
(
i
)
<=
'1'
;
END
IF
;
END
IF
;
END
IF
;
END
IF
;
END
IF
;
END
PROCESS
;
END
PROCESS
;
...
@@ -372,20 +373,20 @@ BEGIN
...
@@ -372,20 +373,20 @@ BEGIN
-- clock source process
-- clock source process
-- generate the sysref pulses
-- generate the sysref pulses
proc_sysref
:
PROCESS
(
jesd204b_sampclk
,
mm_rst
)
proc_sysref
:
PROCESS
(
jesd204b_sampclk
,
mm_rst
)
VARIABLE
count
:
NATURAL
:
=
0
;
VARIABLE
v_
count
:
NATURAL
:
=
0
;
BEGIN
BEGIN
IF
mm_rst
=
'1'
THEN
IF
mm_rst
=
'1'
THEN
jesd204b_sysref
<=
'0'
;
jesd204b_sysref
<=
'0'
;
count
:
=
0
;
v_
count
:
=
0
;
ELSE
ELSE
IF
rising_edge
(
jesd204b_sampclk
)
THEN
IF
rising_edge
(
jesd204b_sampclk
)
THEN
IF
(
count
=
c_sysref_period
-1
)
THEN
IF
(
v_
count
=
c_sysref_period
-1
)
THEN
count
:
=
0
;
v_
count
:
=
0
;
ELSE
ELSE
count
:
=
count
+
1
;
v_
count
:
=
v_
count
+
1
;
END
IF
;
END
IF
;
IF
count
>
c_sysref_period
-1
-
c_sysref_pulselength
THEN
IF
v_
count
>
c_sysref_period
-1
-
c_sysref_pulselength
THEN
jesd204b_sysref
<=
'1'
;
jesd204b_sysref
<=
'1'
;
ELSE
ELSE
jesd204b_sysref
<=
'0'
;
jesd204b_sysref
<=
'0'
;
...
@@ -486,14 +487,24 @@ BEGIN
...
@@ -486,14 +487,24 @@ BEGIN
rx_sosi_sop
<=
rx_sosi
.
sop
;
rx_sosi_sop
<=
rx_sosi
.
sop
;
rx_sosi_eop
<=
rx_sosi
.
eop
;
rx_sosi_eop
<=
rx_sosi
.
eop
;
rx_sosi_valid_arr
<=
func_dp_stream_arr_get
(
rx_sosi_arr
,
"VALID"
);
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Simulation end
-- Simulation end
------------------------------------------------------------------------------
------------------------------------------------------------------------------
sim_done
<=
'1'
when
rx_sosi_arr
(
0
)
.
valid
=
'1'
and
rx_sosi_arr
(
1
)
.
valid
=
'1'
and
rx_sosi_arr
(
2
)
.
valid
=
'1'
else
'0'
;
sim_done
<=
'1'
when
rx_sosi_arr
(
0
)
.
valid
=
'1'
and
rx_sosi_arr
(
1
)
.
valid
=
'1'
and
rx_sosi_arr
(
2
)
.
valid
=
'1'
else
'0'
;
tb_end
<=
'0'
,
'1'
after
110
us
;
proc_common_stop_simulation
(
TRUE
,
1000
,
jesd204b_sampclk
,
sim_done
,
tb_end
);
p_tb_end
:
PROCESS
BEGIN
WAIT
FOR
2
*
c_sysref_period
*
c_jesd204b_sampclk_period
;
ASSERT
sim_done
=
'1'
REPORT
"No rx samples were received."
SEVERITY
ERROR
;
WAIT
FOR
10
us
;
tb_end
<=
'1'
;
END
PROCESS
;
proc_common_timeout_failure
(
200
us
,
tb_timeout
);
-- ERROR: end simulation if it fails to end in time
proc_common_stop_simulation
(
tb_end
);
-- OK: end simulation
END
tb
;
END
tb
;
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