From 4203e433298180af96720997c67240ff656fcd47 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Thu, 6 Jan 2022 14:07:10 +0100
Subject: [PATCH] Made tb self checking.
---
libraries/technology/jesd204b/hdllib.cfg | 5 +-
.../technology/jesd204b/tb_tech_jesd204b.vhd | 107 ++++++++++--------
2 files changed, 60 insertions(+), 52 deletions(-)
diff --git a/libraries/technology/jesd204b/hdllib.cfg b/libraries/technology/jesd204b/hdllib.cfg
index c7298b77b1..490134d658 100644
--- a/libraries/technology/jesd204b/hdllib.cfg
+++ b/libraries/technology/jesd204b/hdllib.cfg
@@ -19,13 +19,10 @@ test_bench_files =
tb_tech_jesd204b.vhd
regression_test_vhdl =
-# FIXME: broken, need fixing
-# tb_tech_jesd204b.vhd
+ tb_tech_jesd204b.vhd
-
[modelsim_project_file]
modelsim_copy_files =
wave_tb_tech_jesd204b.do .
-
[quartus_project_file]
diff --git a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
index fa72add31a..8653d132d7 100644
--- a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
@@ -24,12 +24,14 @@
-- Includes 3 JESD transmit sources to test multichannel syncronization
-- Relative delays between TX and RX channels can be varied by editing c_delay_*
-- Used default technology e1sg
--- TODO:
--- Make a tb_tb to run several test cases automatically
+-- Remark:
+-- The self checking is minimal. It only checks that Tx data from the DAC in
+-- the tb does come out the JESD Rx. Some more data and strobe testing would
+-- be nice, but is not needed because it works on HW.
-- Usage:
-- Load sim # check that design can load in vsim
-- > as 3 # check that the hierarchy for g_design_name is complete (or use do wave_tb_tech_jesd204b.do)
--- > run 120us # enough time to reset and syncronize the JESD IP
+-- > run -a # enough time to reset and syncronize the JESD IP
LIBRARY IEEE, common_lib, dp_lib;
USE IEEE.std_logic_1164.ALL;
@@ -56,8 +58,9 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
CONSTANT c_nof_streams_jesd204b : NATURAL := 12; -- number of jesd204b receiver channels
CONSTANT c_jesd204b_rx_data_w : NATURAL :=32;
- CONSTANT c_jesd204b_rx_framer_data_w : NATURAL :=c_jesd204b_rx_data_w/2; -- IP outputs two samples in parallel
CONSTANT c_jesd204b_rx_somf_w : NATURAL :=c_jesd204b_rx_data_w/8; -- One somf bit per octet
+ CONSTANT c_jesd204b_rx_framer_data_w : NATURAL :=c_jesd204b_rx_data_w/2; -- IP outputs two samples in parallel
+ CONSTANT c_jesd204b_rx_framer_somf_w : NATURAL :=c_jesd204b_rx_somf_w/2; -- IP outputs two samples in parallel
-- Transport delays
TYPE t_time_arr IS ARRAY (0 TO c_nof_streams_jesd204b-1) OF TIME;
@@ -87,8 +90,6 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
1000 ps) ; -- transport delays clock source to adc(tx)
CONSTANT c_delay_sysreftofpga : TIME := 10200 ps;
-
-
-- clocks and resets for the jesd204b tx
SIGNAL txlink_clk : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
SIGNAL dev_sync_n : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
@@ -112,6 +113,7 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
-- Tb
SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL tb_timeout : STD_LOGIC := '0';
SIGNAL sim_done : STD_LOGIC := '0';
-- mm control buses
@@ -131,13 +133,15 @@ ARCHITECTURE tb OF tb_tech_jesd204b IS
SIGNAL rx_sysref : STD_LOGIC := '0';
SIGNAL rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+ -- Debug signals for rx_sosi_arr
SIGNAL rx_sosi : t_dp_sosi;
SIGNAL rx_sosi_data : STD_LOGIC_VECTOR(c_jesd204b_rx_framer_data_w-1 DOWNTO 0); -- 16 bit samples
- SIGNAL rx_sosi_channel : STD_LOGIC_VECTOR(c_jesd204b_rx_somf_w-1 DOWNTO 0);
+ SIGNAL rx_sosi_channel : STD_LOGIC_VECTOR(c_jesd204b_rx_framer_somf_w-1 DOWNTO 0); -- two samples
SIGNAL rx_sosi_valid : STD_LOGIC;
SIGNAL rx_sosi_sync : STD_LOGIC;
SIGNAL rx_sosi_sop : STD_LOGIC;
SIGNAL rx_sosi_eop : STD_LOGIC;
+ SIGNAL rx_sosi_valid_arr : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
SIGNAL jesd204b_sampclk_fpga : STD_LOGIC := '1';
SIGNAL jesd204b_sampclk_adc : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
@@ -285,44 +289,41 @@ BEGIN
-- Generate test pattern at each ADC
proc_data : PROCESS (jesd204b_sampclk_adc(i), mm_rst)
- VARIABLE data : INTEGER := 0;
- VARIABLE even_sample : BOOLEAN := TRUE;
+ VARIABLE v_data : INTEGER := 0;
+ VARIABLE v_even_sample : BOOLEAN := TRUE;
BEGIN
IF mm_rst = '1' THEN
jesd204b_tx_link_data_arr(i) <= (others => '0');
jesd204b_tx_link_valid(i) <= '0';
txlink_clk(i) <= '0';
- data := 0;
- even_sample := TRUE;
- ELSE
- IF rising_edge(jesd204b_sampclk_adc(i)) THEN
- txlink_clk(i) <= not txlink_clk(i);
- jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i);
- jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i);
-
- --generate a positive and negative going pulse after the rising edge of SYSREF
- IF (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') THEN
- data := 1000;
- ELSIF (jesd204b_sysref_adc_1(i) = '1' and jesd204b_sysref_adc_2(i) = '0') THEN
- data := -1000;
- ELSE
- data := 0;
- END IF;
-
- -- Frame the data to 32 bits at half the rate
- IF(jesd204b_tx_link_ready(i) = '0') THEN
- even_sample := TRUE;
- ELSE
- even_sample := not even_sample;
- END IF;
- IF (even_sample = TRUE) THEN
- jesd204b_tx_link_data_arr(i)(15 downto 0) <= TO_SVEC(data, 16);
- jesd204b_tx_link_valid(i) <= '0';
- ELSE
- jesd204b_tx_link_data_arr(i)(31 downto 16) <= TO_SVEC(data, 16);
- jesd204b_tx_link_valid(i) <= '1';
- END IF;
+ v_data := 0;
+ v_even_sample := TRUE;
+ ELSIF rising_edge(jesd204b_sampclk_adc(i)) THEN
+ txlink_clk(i) <= not txlink_clk(i);
+ jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i);
+ jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i);
+
+ --generate a positive and negative going pulse after the rising edge of SYSREF
+ IF (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') THEN
+ v_data := 1000;
+ ELSIF (jesd204b_sysref_adc_1(i) = '1' and jesd204b_sysref_adc_2(i) = '0') THEN
+ v_data := -1000;
+ ELSE
+ v_data := 0;
+ END IF;
+ -- Frame the data to 32 bits at half the rate
+ IF(jesd204b_tx_link_ready(i) = '0') THEN
+ v_even_sample := TRUE;
+ ELSE
+ v_even_sample := not v_even_sample;
+ END IF;
+ IF (v_even_sample = TRUE) THEN
+ jesd204b_tx_link_data_arr(i)(15 downto 0) <= TO_SVEC(v_data, 16);
+ jesd204b_tx_link_valid(i) <= '0';
+ ELSE
+ jesd204b_tx_link_data_arr(i)(31 downto 16) <= TO_SVEC(v_data, 16);
+ jesd204b_tx_link_valid(i) <= '1';
END IF;
END IF;
END PROCESS;
@@ -372,20 +373,20 @@ BEGIN
-- clock source process
-- generate the sysref pulses
proc_sysref : PROCESS (jesd204b_sampclk, mm_rst)
- VARIABLE count : NATURAL := 0;
+ VARIABLE v_count : NATURAL := 0;
BEGIN
IF mm_rst = '1' THEN
jesd204b_sysref <= '0';
- count := 0;
+ v_count := 0;
ELSE
IF rising_edge(jesd204b_sampclk) THEN
- IF (count = c_sysref_period-1) THEN
- count := 0;
+ IF (v_count = c_sysref_period-1) THEN
+ v_count := 0;
ELSE
- count := count + 1;
+ v_count := v_count + 1;
END IF;
- IF count > c_sysref_period-1-c_sysref_pulselength THEN
+ IF v_count > c_sysref_period-1-c_sysref_pulselength THEN
jesd204b_sysref <= '1';
ELSE
jesd204b_sysref <= '0';
@@ -486,14 +487,24 @@ BEGIN
rx_sosi_sop <= rx_sosi.sop;
rx_sosi_eop <= rx_sosi.eop;
+ rx_sosi_valid_arr <= func_dp_stream_arr_get(rx_sosi_arr, "VALID");
------------------------------------------------------------------------------
-- Simulation end
------------------------------------------------------------------------------
- sim_done <= '1' when rx_sosi_arr(0).valid = '1' and rx_sosi_arr(1).valid = '1' and rx_sosi_arr(2).valid = '1' else '0';
- tb_end <= '0', '1' after 110 us;
+ sim_done <= '1' when rx_sosi_arr(0).valid = '1' and rx_sosi_arr(1).valid = '1' and rx_sosi_arr(2).valid = '1' else '0';
+
+ p_tb_end : PROCESS
+ BEGIN
+ WAIT FOR 2 * c_sysref_period * c_jesd204b_sampclk_period;
+
+ ASSERT sim_done = '1' REPORT "No rx samples were received." SEVERITY ERROR;
+ WAIT FOR 10 us;
+ tb_end <= '1';
+ END PROCESS;
- proc_common_stop_simulation(TRUE, 1000, jesd204b_sampclk, sim_done, tb_end);
+ proc_common_timeout_failure(200 us, tb_timeout); -- ERROR: end simulation if it fails to end in time
+ proc_common_stop_simulation(tb_end); -- OK: end simulation
END tb;
--
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