From 41fc4776fea45731866a04af906f1dbe0466216d Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Thu, 8 Oct 2020 22:10:26 +0200
Subject: [PATCH] add mm-bus control for bsn_time_offset and add test to
tb_mms_
---
.../base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd | 86 +++++++++++++++----
.../base/dp/src/vhdl/dp_bsn_source_v2.vhd | 58 +++++++------
.../base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd | 53 +++++++-----
.../dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd | 26 +++++-
4 files changed, 158 insertions(+), 65 deletions(-)
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
index 65c0b826c1..eb5600b183 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
@@ -35,7 +35,8 @@
-- [1] WR dp_on_pps 0x0
-- 1 [31..0] WR nof_clk_per_sync 0x0
-- 2 [31..0] RW bsn[31..0] 0x0 write bsn_init, read current bsn
--- 3 [31..0] RW bsn[63..32] 0x0 write bsn_init, read current bsn
+-- 3 [31..0] RW bsn[63..32] 0x0 write bsn_init, read current bsn
+-- 4 [31..0] RW bsn_time_offset 0x0
-- ====================================================================================
LIBRARY IEEE, common_lib;
@@ -50,22 +51,24 @@ ENTITY dp_bsn_source_reg_v2 IS
);
PORT (
-- Clocks and reset
- mm_rst : IN STD_LOGIC; -- reset synchronous with mm_clk
- mm_clk : IN STD_LOGIC; -- memory-mapped bus clock
- st_rst : IN STD_LOGIC; -- reset synchronous with st_clk
- st_clk : IN STD_LOGIC; -- other clock domain clock
+ mm_rst : IN STD_LOGIC; -- reset synchronous with mm_clk
+ mm_clk : IN STD_LOGIC; -- memory-mapped bus clock
+ st_rst : IN STD_LOGIC; -- reset synchronous with st_clk
+ st_clk : IN STD_LOGIC; -- other clock domain clock
-- Memory Mapped Slave in mm_clk domain
- sla_in : IN t_mem_mosi; -- actual ranges defined by c_mm_reg
- sla_out : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
+ sla_in : IN t_mem_mosi; -- actual ranges defined by c_mm_reg
+ sla_out : OUT t_mem_miso; -- actual ranges defined by c_mm_reg
-- MM registers in st_clk domain
- st_on : OUT STD_LOGIC := '1'; -- level
- st_on_pps : OUT STD_LOGIC := '0'; -- level
- st_on_status : IN STD_LOGIC;
- st_nof_clk_per_sync : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- nof block per sync
- st_bsn_init : OUT STD_LOGIC_VECTOR; -- wr init BSN
- st_current_bsn : IN STD_LOGIC_VECTOR -- rd current BSN
+ st_on : OUT STD_LOGIC := '1'; -- level
+ st_on_pps : OUT STD_LOGIC := '0'; -- level
+ st_on_status : IN STD_LOGIC;
+ st_nof_clk_per_sync : OUT STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0); -- nof block per sync
+ st_bsn_init : OUT STD_LOGIC_VECTOR; -- wr init BSN
+ st_current_bsn : IN STD_LOGIC_VECTOR; -- rd current BSN
+ st_bsn_time_offset : OUT STD_LOGIC_VECTOR;
+ st_current_bsn_time_offset : IN STD_LOGIC_VECTOR
);
END dp_bsn_source_reg_v2;
@@ -73,12 +76,13 @@ END dp_bsn_source_reg_v2;
ARCHITECTURE rtl OF dp_bsn_source_reg_v2 IS
CONSTANT c_bsn_w : NATURAL := st_bsn_init'LENGTH;
+ CONSTANT c_bsn_time_offset_w : NATURAL := st_bsn_time_offset'LENGTH;
-- Define the actual size of the MM slave register
CONSTANT c_mm_reg : t_c_mem := (latency => 1,
- adr_w => 2,
+ adr_w => 3,
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
- nof_dat => 2**2,
+ nof_dat => 3**2,
init_sl => '0');
-- Registers in mm_clk domain
@@ -94,6 +98,10 @@ ARCHITECTURE rtl OF dp_bsn_source_reg_v2 IS
SIGNAL mm_bsn_init_wr : STD_LOGIC;
SIGNAL mm_current_bsn : STD_LOGIC_VECTOR(c_longword_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL mm_current_bsn_hi : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := (OTHERS=>'0');
+
+ SIGNAL mm_bsn_time_offset : STD_LOGIC_VECTOR(c_bsn_time_offset_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL mm_bsn_time_offset_wr : STD_LOGIC;
+ SIGNAL mm_current_bsn_time_offset : STD_LOGIC_VECTOR(c_bsn_time_offset_w-1 DOWNTO 0) := (OTHERS=>'0');
-- Registers in st_clk domain
@@ -119,12 +127,15 @@ BEGIN
mm_bsn_init <= (OTHERS=>'0');
mm_bsn_init_wr <= '0';
mm_current_bsn_hi <= (OTHERS=>'0');
+ mm_bsn_time_offset <= (OTHERS=>'0');
+ mm_bsn_time_offset_wr <= '0';
ELSIF rising_edge(mm_clk) THEN
-- Read access defaults
sla_out.rdval <= '0';
-- Access event defaults
mm_bsn_init_wr <= '0';
+ mm_bsn_time_offset_wr <= '0';
-- Write access: set register value
IF sla_in.wr = '1' THEN
@@ -143,6 +154,11 @@ BEGIN
mm_bsn_init(63 DOWNTO 32) <= sla_in.wrdata(31 DOWNTO 0);
mm_bsn_init_wr <= '1';
+ -- write bsn_time_offset
+ WHEN 4 =>
+ mm_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0) <= sla_in.wrdata(c_bsn_time_offset_w-1 DOWNTO 0);
+ mm_bsn_time_offset_wr <= '1';
+
WHEN OTHERS => NULL; -- not used MM addresses
END CASE;
@@ -164,7 +180,11 @@ BEGIN
mm_current_bsn_hi <= mm_current_bsn(63 DOWNTO 32); -- first read low part and preserve high part
WHEN 3 =>
sla_out.rddata(31 DOWNTO 0) <= mm_current_bsn_hi;
-
+
+ -- Read current bsn_time_offset
+ WHEN 4 =>
+ sla_out.rddata(c_bsn_time_offset_w-1 DOWNTO 0) <= mm_current_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0);
+
WHEN OTHERS => NULL; -- not used MM addresses
END CASE;
END IF;
@@ -193,19 +213,25 @@ BEGIN
st_on_pps <= mm_on_pps;
st_nof_clk_per_sync <= mm_nof_clk_per_sync;
st_bsn_init <= mm_bsn_init(c_bsn_w-1 DOWNTO 0);
+ st_bsn_time_offset <= mm_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0);
p_st_clk : PROCESS(st_rst, st_clk)
BEGIN
IF st_rst='1' THEN
st_bsn_init <= TO_UVEC(0, c_bsn_w);
+ st_bsn_time_offset <= TO_UVEC(0, c_bsn_time_offset_w);
ELSIF rising_edge(st_clk) THEN
IF mm_bsn_init_wr='1' THEN
st_bsn_init <= mm_bsn_init(c_bsn_w-1 DOWNTO 0); -- use wr of mm_bsn_init high part for in_new to ensure proper transfer of double word
END IF;
+ IF mm_bsn_time_offset_wr='1' THEN
+ st_bsn_time_offset <= mm_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0); -- use wr of mm_bsn_init high part for in_new to ensure proper transfer of double word
+ END IF;
END IF;
END PROCESS;
mm_current_bsn(c_bsn_w-1 DOWNTO 0) <= st_current_bsn; -- MM user may read current_bsn twice to avoid small chance that the high part of the double word changed (i.e. incremented)
+ mm_current_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0) <= st_current_bsn_time_offset;
END GENERATE; -- no_cross
gen_cross : IF g_cross_clock_domain = TRUE GENERATE
@@ -279,7 +305,35 @@ BEGIN
out_dat => mm_current_bsn(c_bsn_w-1 DOWNTO 0),
out_new => OPEN
);
+
+ -- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
+ u_bsn_time_offset : ENTITY common_lib.common_reg_cross_domain
+ PORT MAP (
+ in_rst => mm_rst,
+ in_clk => mm_clk,
+ in_new => mm_bsn_time_offset_wr, -- use wr of mm_bsn_time_offset high part for in_new to ensure proper transfer of double word
+ in_dat => mm_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0),
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => st_rst,
+ out_clk => st_clk,
+ out_dat => st_bsn_time_offset,
+ out_new => OPEN
+ );
+ -- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
+ u_current_bsn_offset : ENTITY common_lib.common_reg_cross_domain
+ PORT MAP (
+ in_rst => st_rst,
+ in_clk => st_clk,
+ in_new => '1',
+ in_dat => st_current_bsn_time_offset,
+ in_done => OPEN, -- pulses when no more pending in_new
+ out_rst => mm_rst,
+ out_clk => mm_clk,
+ out_dat => mm_current_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0),
+ out_new => OPEN
+ );
+
END GENERATE; -- gen_cross
END rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
index f12b484d05..465e677d3d 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
@@ -46,23 +46,24 @@ ENTITY dp_bsn_source_v2 IS
g_block_size : NATURAL := 256;
g_nof_clk_per_sync : NATURAL := 200 * 10**6;
g_bsn_w : NATURAL := 48;
- g_time_offset_w : NATURAL := 10
+ g_bsn_time_offset_w : NATURAL := 10
);
PORT (
- rst : IN STD_LOGIC;
- clk : IN STD_LOGIC;
- pps : IN STD_LOGIC := '1';
+ rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
+ pps : IN STD_LOGIC := '1';
- dp_on : IN STD_LOGIC;
- dp_on_pps : IN STD_LOGIC;
+ dp_on : IN STD_LOGIC;
+ dp_on_pps : IN STD_LOGIC;
- dp_on_status : OUT STD_LOGIC;
+ dp_on_status : OUT STD_LOGIC;
- bsn_init : IN STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
- nof_clk_per_sync : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := TO_UVEC(g_nof_clk_per_sync, c_word_w);
- bsn_time_offset : IN STD_LOGIC_VECTOR(g_time_offset_w-1 DOWNTO 0) := (OTHERS=>'0');
+ bsn_init : IN STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
+ nof_clk_per_sync : IN STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0) := TO_UVEC(g_nof_clk_per_sync, c_word_w);
+ bsn_time_offset : IN STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0) := (OTHERS=>'0');
+ current_bsn_time_offset : OUT STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
- src_out : OUT t_dp_sosi -- only uses sync, bsn[], valid, sop and eop
+ src_out : OUT t_dp_sosi -- only uses sync, bsn[], valid, sop and eop
);
END dp_bsn_source_v2;
@@ -101,8 +102,11 @@ ARCHITECTURE rtl OF dp_bsn_source_v2 IS
SIGNAL i_dp_on_status : STD_LOGIC;
SIGNAL nxt_dp_on_status : STD_LOGIC;
- SIGNAL nxt_bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_time_offset_w-1 DOWNTO 0);
- SIGNAL bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_time_offset_w-1 DOWNTO 0);
+ SIGNAL nxt_bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
+ SIGNAL bsn_time_offset_cnt : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
+
+ SIGNAL i_current_bsn_time_offset : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
+ SIGNAL nxt_current_bsn_time_offset : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
SIGNAL nxt_clk_cnt : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
SIGNAL clk_cnt : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
@@ -113,20 +117,23 @@ BEGIN
src_out <= i_src_out;
dp_on_status <= i_dp_on_status;
+ current_bsn_time_offset <= i_current_bsn_time_offset;
- p_state : PROCESS(state, prev_state, dp_on, dp_on_pps, pps, block_size_cnt, clk_cnt, bsn_init, i_src_out, i_dp_on_status, bsn_time_offset_cnt)
+ p_state : PROCESS(state, prev_state, dp_on, dp_on_pps, pps, block_size_cnt, clk_cnt, bsn_init, i_src_out, i_dp_on_status, bsn_time_offset_cnt, bsn_time_offset)
BEGIN
- nxt_state <= state;
- nxt_src_out <= i_src_out;
- nxt_src_out.sync <= '0';
- nxt_src_out.valid <= '0';
- nxt_src_out.sop <= '0';
- nxt_src_out.eop <= '0';
- nxt_block_size_cnt <= block_size_cnt;
- nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
- nxt_sync <= sync;
- nxt_dp_on_status <= i_dp_on_status;
- nxt_bsn_time_offset_cnt <= bsn_time_offset_cnt;
+ nxt_state <= state;
+ nxt_src_out <= i_src_out;
+ nxt_src_out.sync <= '0';
+ nxt_src_out.valid <= '0';
+ nxt_src_out.sop <= '0';
+ nxt_src_out.eop <= '0';
+ nxt_block_size_cnt <= block_size_cnt;
+ nxt_clk_cnt <= INCR_UVEC(clk_cnt, 1);
+ nxt_sync <= sync;
+ nxt_dp_on_status <= i_dp_on_status;
+ nxt_bsn_time_offset_cnt <= bsn_time_offset_cnt;
+ nxt_current_bsn_time_offset <= bsn_time_offset;
+
IF UNSIGNED(clk_cnt) = UNSIGNED(nof_clk_per_sync) - 1 THEN
nxt_clk_cnt <= (OTHERS=>'0');
@@ -224,6 +231,7 @@ BEGIN
block_size_cnt <= nxt_block_size_cnt;
i_dp_on_status <= nxt_dp_on_status;
bsn_time_offset_cnt <= nxt_bsn_time_offset_cnt;
+ i_current_bsn_time_offset <= nxt_current_bsn_time_offset;
END IF;
END PROCESS;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
index 3ca46fb3ca..9d096d2a96 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
@@ -34,7 +34,8 @@ ENTITY mms_dp_bsn_source_v2 IS
g_cross_clock_domain : BOOLEAN := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
g_block_size : NATURAL := 256; -- 1024 samples @ 800M / 4 = 256 4 sample words @ 200 M
g_nof_clk_per_sync : NATURAL := 200 * 10**6; -- ;
- g_bsn_w : NATURAL := 48
+ g_bsn_w : NATURAL := 48;
+ g_bsn_time_offset_w : NATURAL := 10
);
PORT (
-- Clocks and reset
@@ -56,16 +57,18 @@ END mms_dp_bsn_source_v2;
ARCHITECTURE str OF mms_dp_bsn_source_v2 IS
- SIGNAL dp_on : STD_LOGIC;
- SIGNAL dp_on_pps : STD_LOGIC;
- SIGNAL nof_clk_per_sync : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
- SIGNAL bsn_init : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ SIGNAL dp_on : STD_LOGIC;
+ SIGNAL dp_on_pps : STD_LOGIC;
+ SIGNAL nof_clk_per_sync : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
+ SIGNAL bsn_init : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ SIGNAL bsn_time_offset : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
- SIGNAL i_bs_sosi : t_dp_sosi;
+ SIGNAL i_bs_sosi : t_dp_sosi;
- SIGNAL dp_on_status : STD_LOGIC;
+ SIGNAL dp_on_status : STD_LOGIC;
- SIGNAL capture_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL capture_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL current_bsn_time_offset : STD_LOGIC_VECTOR(g_bsn_time_offset_w-1 DOWNTO 0);
BEGIN
@@ -88,12 +91,14 @@ BEGIN
sla_out => reg_miso,
-- MM registers in st_clk domain
- st_on => dp_on,
- st_on_pps => dp_on_pps,
- st_on_status => dp_on_status,
- st_nof_clk_per_sync => nof_clk_per_sync,
- st_bsn_init => bsn_init,
- st_current_bsn => capture_bsn
+ st_on => dp_on,
+ st_on_pps => dp_on_pps,
+ st_on_status => dp_on_status,
+ st_nof_clk_per_sync => nof_clk_per_sync,
+ st_bsn_init => bsn_init,
+ st_current_bsn => capture_bsn,
+ st_bsn_time_offset => bsn_time_offset,
+ st_current_bsn_time_offset => current_bsn_time_offset
);
u_bsn_source : ENTITY work.dp_bsn_source_v2
@@ -103,17 +108,19 @@ BEGIN
g_bsn_w => g_bsn_w
)
PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
- pps => dp_pps,
+ rst => dp_rst,
+ clk => dp_clk,
+ pps => dp_pps,
-- MM control
- dp_on => dp_on,
- dp_on_pps => dp_on_pps,
- dp_on_status => dp_on_status,
- bsn_init => bsn_init,
- nof_clk_per_sync => nof_clk_per_sync,
+ dp_on => dp_on,
+ dp_on_pps => dp_on_pps,
+ dp_on_status => dp_on_status,
+ bsn_init => bsn_init,
+ nof_clk_per_sync => nof_clk_per_sync,
+ bsn_time_offset => bsn_time_offset,
+ current_bsn_time_offset => current_bsn_time_offset,
-- Streaming
- src_out => i_bs_sosi
+ src_out => i_bs_sosi
);
--capture_bsn <= i_bs_sosi.bsn; -- capture current BSN
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
index 7d40dff868..22e323b0ac 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
@@ -44,6 +44,8 @@ END tb_mms_dp_bsn_source_v2;
ARCHITECTURE tb OF tb_mms_dp_bsn_source_v2 IS
+ CONSTANT c_bsn_time_offset_w : NATURAL := 10;
+
CONSTANT c_clk_period : TIME := 10 ns;
CONSTANT c_pps_interval : NATURAL := 1000;
@@ -58,6 +60,7 @@ ARCHITECTURE tb OF tb_mms_dp_bsn_source_v2 IS
CONSTANT c_mm_addr_nof_block_per_sync : NATURAL := 1;
CONSTANT c_mm_addr_bsn_lo : NATURAL := 2;
CONSTANT c_mm_addr_bsn_hi : NATURAL := 3;
+ CONSTANT c_mm_addr_bsn_time_offset : NATURAL := 4;
CONSTANT c_mm_dp_off : NATURAL := 0; -- DP off after finishing current block
CONSTANT c_mm_dp_on_immediate : NATURAL := 1; -- DP on immediate by setting bit 0
@@ -73,6 +76,8 @@ ARCHITECTURE tb OF tb_mms_dp_bsn_source_v2 IS
SIGNAL mm_dp_on_status : NATURAL;
SIGNAL mm_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL mm_bsn_prev : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
+
+ SIGNAL mm_bsn_time_offset : STD_LOGIC_VECTOR(c_bsn_time_offset_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL mm_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL mm_miso : t_mem_miso;
@@ -114,7 +119,7 @@ BEGIN
ASSERT mm_dp_on_status=c_mm_dp_on_immediate REPORT "Wrong DP on status, expected DP on immediate." SEVERITY ERROR;
-- Read BSN twice in same PPS interval
- proc_common_wait_some_cycles(clk, 3*c_block_size);
+ proc_common_wait_some_cycles(clk, c_block_size);
proc_mem_mm_bus_rd(c_mm_addr_bsn_lo, clk, mm_miso, mm_mosi);
proc_mem_mm_bus_rd_latency(1, clk);
@@ -152,6 +157,25 @@ BEGIN
proc_common_wait_some_cycles(clk, 1);
ASSERT mm_dp_on_status=c_mm_dp_off REPORT "Wrong DP on status, expected DP off." SEVERITY ERROR;
+ -- Set bsn_time_offset and read back 2 times 0 and 5
+ proc_mem_mm_bus_wr(c_mm_addr_bsn_time_offset, 0, clk, mm_miso, mm_mosi);
+ proc_common_wait_some_cycles(clk, 2*c_cross_clock_domain_latency);
+
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_time_offset, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0) <= mm_miso.rddata(c_bsn_time_offset_w-1 DOWNTO 0);
+ proc_common_wait_some_cycles(clk, 1);
+ ASSERT TO_UINT(mm_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0))=0 REPORT "Wrong offset, expected 0" SEVERITY ERROR;
+
+ proc_mem_mm_bus_wr(c_mm_addr_bsn_time_offset, 5, clk, mm_miso, mm_mosi);
+ proc_common_wait_some_cycles(clk, 2*c_cross_clock_domain_latency);
+
+ proc_mem_mm_bus_rd(c_mm_addr_bsn_time_offset, clk, mm_miso, mm_mosi);
+ proc_mem_mm_bus_rd_latency(1, clk);
+ mm_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0) <= mm_miso.rddata(c_bsn_time_offset_w-1 DOWNTO 0);
+ proc_common_wait_some_cycles(clk, 1);
+ ASSERT TO_UINT(mm_bsn_time_offset(c_bsn_time_offset_w-1 DOWNTO 0))=5 REPORT "Wrong offset, expected 5" SEVERITY ERROR;
+
proc_common_wait_some_cycles(clk, c_sync_interval);
tb_end <= '1';
WAIT;
--
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