Added multi tb for tech_tse.

libraries/technology/tse/hdllib.cfg

@@ -35,9 +35,10 @@ test_bench_files =
     sim_tse.vhd
     tb_tech_tse_pkg.vhd
     tb_tech_tse.vhd
+    tb_tb_tech_tse.vhd
 
 regression_test_vhdl = 
-    tb_tech_tse.vhd
+    tb_tb_tech_tse.vhd
 
 
 [modelsim_project_file]

libraries/technology/tse/tb_tb_tech_tse.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+-- 
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+-- 
+--     http://www.apache.org/licenses/LICENSE-2.0
+-- 
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+-- 
+-- Author: E. Kooistra
+-- Purpose: Multi-testbench for tech_tse
+-- Description:
+--   Verify tech_tse for different data types
+-- Usage:
+--   > as 3
+--   > run -all
+
+LIBRARY IEEE, technology_lib, tech_tse_lib;
+USE IEEE.std_logic_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
+
+
+ENTITY tb_tb_tech_tse IS
+END tb_tb_tech_tse;
+
+
+ARCHITECTURE tb OF tb_tb_tech_tse IS
+
+  CONSTANT c_tech : NATURAL := c_tech_select_default;
+  
+  CONSTANT c_tb_end_vec : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS=>'1');
+  SIGNAL   tb_end_vec   : STD_LOGIC_VECTOR(15 DOWNTO 0) := c_tb_end_vec;  -- sufficiently long to fit all tb instances
+  SIGNAL   tb_end       : STD_LOGIC := '0';
+  
+BEGIN
+
+-- g_technology : NATURAL := c_tech_select_default;
+-- --   g_data_type = c_tb_tech_tse_data_type_symbols  = 0
+-- --   g_data_type = c_tb_tech_tse_data_type_counter  = 1
+-- g_data_type  : NATURAL := c_tb_tech_tse_data_type_symbols;
+-- g_sim        : BOOLEAN := TRUE;
+-- g_sim_level  : NATURAL := 1;    -- 0 = use IP; 1 = use fast serdes model;
+-- g_tb_end     : BOOLEAN := TRUE  -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
+  
+  u_ip           : ENTITY work.tb_tech_tse GENERIC MAP (c_tech, c_tb_tech_tse_data_type_symbols, FALSE, 0, FALSE) PORT MAP (tb_end_vec(0));
+  u_sim_level_0  : ENTITY work.tb_tech_tse GENERIC MAP (c_tech, c_tb_tech_tse_data_type_symbols,  TRUE, 0, FALSE) PORT MAP (tb_end_vec(1));
+  u_sim_level_1  : ENTITY work.tb_tech_tse GENERIC MAP (c_tech, c_tb_tech_tse_data_type_symbols,  TRUE, 1, FALSE) PORT MAP (tb_end_vec(2));
+  
+  tb_end <= '1' WHEN tb_end_vec=c_tb_end_vec ELSE '0';
+  
+  p_tb_end : PROCESS
+  BEGIN
+    WAIT UNTIL tb_end='1';
+    WAIT FOR 1 ns;
+    REPORT "Multi tb simulation finished." SEVERITY FAILURE;
+    WAIT;
+  END PROCESS;
+END tb;