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Commit 4d3f32f1 authored by Eric Kooistra's avatar Eric Kooistra
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Merge branch 'master' of git.astron.nl:desp/hdl

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hdl_lib_name = lofar2_unb2b_adc
hdl_library_clause_name = lofar2_unb2b_adc_lib
hdl_lib_uses_synth = common technology mm unb2b_board dp eth tech_tse tr_10GbE diagnostics diag tech_jesd204b
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
src/vhdl/lofar2_unb2b_adc_pkg.vhd
src/vhdl/mmm_lofar2_unb2b_adc.vhd
src/vhdl/lofar2_unb2b_adc.vhd
test_bench_files =
tb/vhdl/tb_lofar2_unb2b_adc.vhd
[modelsim_project_file]
modelsim_copy_files =
[quartus_project_file]
quartus_copy_files =
#Placeholder
###############################################################################
#
# Copyright (C) 2014
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
hdl_lib_name = lofar2_unb2b_adc_full
hdl_library_clause_name = lofar2_unb2b_adc_full_lib
hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_adc
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
# ../../src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
# ../../src/vhdl/lofar2_unb2b_adc_pkg.vhd
# ../../src/vhdl/mmm_lofar2_unb2b_adc.vhd
# ../../src/vhdl/lofar2_unb2b_adc.vhd
lofar2_unb2b_adc_full.vhd
test_bench_files =
tb_lofar2_unb2b_adc_full.vhd
[modelsim_project_file]
modelsim_copy_files =
# Pinning design only intended for synthesis
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
../../quartus .
../../src/hex hex
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_pre_files =
../../quartus/lofar_unb2b_adc.sdc
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
../../quartus/lofar_unb2b_adc_pins.tcl
quartus_vhdl_files =
quartus_qip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar_unb2b_adc_full/qsys_lofar_unb2b_adc/qsys_lofar_unb2b_adc.qip
quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
ENTITY lofar2_unb2b_adc_full IS
GENERIC (
g_design_name : STRING := "lofar2_unb2b_adc_full";
g_design_note : STRING := "Lofar2 adc with one node";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_revision_id : STRING := "" -- revision ID -- set by QSF
);
PORT (
-- GENERAL
CLK : IN STD_LOGIC; -- System Clock
PPS : IN STD_LOGIC; -- System Sync
WDI : OUT STD_LOGIC; -- Watchdog Clear
INTA : INOUT STD_LOGIC; -- FPGA interconnect line
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
SENS_SC : INOUT STD_LOGIC;
SENS_SD : INOUT STD_LOGIC;
PMBUS_SC : INOUT STD_LOGIC;
PMBUS_SD : INOUT STD_LOGIC;
PMBUS_ALERT : IN STD_LOGIC := '0';
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
-- back transceivers
BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
-- jesd204b syncronization signals
JESD204B_SYSREF : IN STD_LOGIC;
JESD204B_SYNC : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0)
);
END lofar2_unb2b_adc_full;
ARCHITECTURE str OF lofar2_unb2b_adc_full IS
BEGIN
u_revision : ENTITY lofar2_unb2b_adc_lib.lofar2_unb2b_adc
GENERIC MAP (
g_design_name => g_design_name,
g_design_note => g_design_note,
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time,
g_revision_id => g_revision_id
)
PORT MAP (
-- GENERAL
CLK => CLK,
PPS => PPS,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- Others
VERSION => VERSION,
ID => ID,
TESTIO => TESTIO,
-- I2C Interface to Sensors
SENS_SC => SENS_SC,
SENS_SD => SENS_SD,
PMBUS_SC => PMBUS_SC,
PMBUS_SD => PMBUS_SD,
PMBUS_ALERT => PMBUS_ALERT,
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT,
-- LEDs
QSFP_LED => QSFP_LED,
-- back transceivers
BCK_RX => BCK_RX,
BCK_REF_CLK => BCK_REF_CLK,
-- jesd204b syncronization signals
JESD204B_SYSREF => JESD204B_SYSREF,
JESD204B_SYNC => JESD204B_SYNC
);
END str;
-------------------------------------------------------------------------------
--
-- Copyright (C) 2018
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Author: Jonathan Hargreaves
-- Purpose: Tb to show that lofar2_unb2b_adc_full can simulate
-- Description:
-- Must use c_sim = TRUE to speed up simulation
-- This is a compile-only test bench
-- Usage:
-- Load sim # check that design can load in vsim
-- > as 10 # check that the hierarchy for g_design_name is complete
-- > run -a # check that design can simulate some us without error
LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
ENTITY tb_lofar2_unb2b_adc_full IS
END tb_lofar2_unb2b_adc_full;
ARCHITECTURE tb OF tb_lofar2_unb2b_adc_full IS
CONSTANT c_sim : BOOLEAN := TRUE;
CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
CONSTANT c_node_nr : NATURAL := 0; -- Back node 3
CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
CONSTANT c_ext_clk_period : TIME := 5 ns;
CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
CONSTANT c_pps_period : NATURAL := 1000;
-- Tb
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL sim_done : STD_LOGIC := '0';
-- DUT
SIGNAL ext_clk : STD_LOGIC := '0';
SIGNAL pps : STD_LOGIC := '0';
SIGNAL pps_rst : STD_LOGIC := '0';
SIGNAL WDI : STD_LOGIC;
SIGNAL INTA : STD_LOGIC;
SIGNAL INTB : STD_LOGIC;
SIGNAL eth_clk : STD_LOGIC := '0';
SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC;
SIGNAL pmbus_scl : STD_LOGIC;
SIGNAL pmbus_sda : STD_LOGIC;
-- back transceivers
SIGNAL bck_rx : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL bck_ref_clk : STD_LOGIC := '1';
-- jesd204b syncronization signals
SIGNAL jesd204b_sysref : STD_LOGIC;
SIGNAL jesd204b_sync : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
BEGIN
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
bck_ref_clk <= NOT bck_ref_clk AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
sens_scl <= 'H'; -- pull up
sens_sda <= 'H'; -- pull up
pmbus_scl <= 'H'; -- pull up
pmbus_sda <= 'H'; -- pull up
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
jesd204b_sysref <= pps;
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc_full : ENTITY work.lofar2_unb2b_adc_full
GENERIC MAP (
g_sim => c_sim,
g_sim_unb_nr => c_unb_nr,
g_sim_node_nr => c_node_nr
)
PORT MAP (
-- GENERAL
CLK => ext_clk,
PPS => pps,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- Others
VERSION => c_version,
ID => c_id,
TESTIO => open,
-- I2C Interface to Sensors
SENS_SC => sens_scl,
SENS_SD => sens_sda,
PMBUS_SC => pmbus_scl,
PMBUS_SD => pmbus_sda,
PMBUS_ALERT => open,
-- 1GbE Control Interface
ETH_CLK => eth_clk,
ETH_SGIN => eth_rxp,
ETH_SGOUT => eth_txp,
-- LEDs
QSFP_LED => open,
-- back transceivers
BCK_RX => bck_rx,
BCK_REF_CLK => bck_ref_clk,
-- jesd204b syncronization signals
JESD204B_SYSREF => jesd204b_sysref,
JESD204B_SYNC => jesd204b_sync
);
------------------------------------------------------------------------------
-- Simulation end
------------------------------------------------------------------------------
sim_done <= '0', '1' AFTER 1 us;
proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
END tb;
\ No newline at end of file
hdl_lib_name = lofar2_unb2b_adc_one_node
hdl_library_clause_name = lofar2_unb2b_adc_one_node_lib
hdl_lib_uses_synth = common mm technology unb2b_board lofar2_unb2b_adc
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
synth_files =
# ../../src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
# ../../src/vhdl/lofar2_unb2b_adc_pkg.vhd
# ../../src/vhdl/mmm_lofar2_unb2b_adc.vhd
# ../../src/vhdl/lofar2_unb2b_adc.vhd
lofar2_unb2b_adc_one_node.vhd
test_bench_files =
tb_lofar2_unb2b_adc_one_node.vhd
[modelsim_project_file]
modelsim_copy_files =
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
../../quartus .
../../src/hex hex
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_pre_files =
../../quartus/lofar_unb2b_adc.sdc
quartus_sdc_files =
$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
../../quartus/lofar_unb2b_adc_pins.tcl
quartus_vhdl_files =
quartus_qip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar_unb2b_adc_one_node/qsys_lofar_unb2b_adc/qsys_lofar_unb2b_adc.qip
quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
ENTITY lofar2_unb2b_adc_one_node IS
GENERIC (
g_design_name : STRING := "lofar2_unb2b_adc_one_node";
g_design_note : STRING := "Lofar2 adc with one node";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_revision_id : STRING := "" -- revision ID -- set by QSF
);
PORT (
-- GENERAL
CLK : IN STD_LOGIC; -- System Clock
PPS : IN STD_LOGIC; -- System Sync
WDI : OUT STD_LOGIC; -- Watchdog Clear
INTA : INOUT STD_LOGIC; -- FPGA interconnect line
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
SENS_SC : INOUT STD_LOGIC;
SENS_SD : INOUT STD_LOGIC;
PMBUS_SC : INOUT STD_LOGIC;
PMBUS_SD : INOUT STD_LOGIC;
PMBUS_ALERT : IN STD_LOGIC := '0';
-- 1GbE Control Interface
ETH_CLK : IN STD_LOGIC;
ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
-- LEDs
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0);
-- back transceivers
BCK_RX : IN STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
BCK_REF_CLK : IN STD_LOGIC; -- Use as JESD204B_REFCLK
-- jesd204b syncronization signals
JESD204B_SYSREF : IN STD_LOGIC;
JESD204B_SYNC : OUT STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0)
);
END lofar2_unb2b_adc_one_node;
ARCHITECTURE str OF lofar2_unb2b_adc_one_node IS
BEGIN
u_revision : ENTITY lofar2_unb2b_adc_lib.lofar2_unb2b_adc
GENERIC MAP (
g_design_name => g_design_name,
g_design_note => g_design_note,
g_sim => g_sim,
g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => g_sim_node_nr,
g_stamp_date => g_stamp_date,
g_stamp_time => g_stamp_time,
g_revision_id => g_revision_id
)
PORT MAP (
-- GENERAL
CLK => CLK,
PPS => PPS,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- Others
VERSION => VERSION,
ID => ID,
TESTIO => TESTIO,
-- I2C Interface to Sensors
SENS_SC => SENS_SC,
SENS_SD => SENS_SD,
PMBUS_SC => PMBUS_SC,
PMBUS_SD => PMBUS_SD,
PMBUS_ALERT => PMBUS_ALERT,
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT,
-- LEDs
QSFP_LED => QSFP_LED,
-- back transceivers
BCK_RX => BCK_RX,
BCK_REF_CLK => BCK_REF_CLK,
-- jesd204b syncronization signals
JESD204B_SYSREF => JESD204B_SYSREF,
JESD204B_SYNC => JESD204B_SYNC
);
END str;
-------------------------------------------------------------------------------
--
-- Copyright (C) 2018
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Author: Jonathan Hargreaves
-- Purpose: Tb to show that lofar2_unb2b_adc_one_node can simulate
-- Description:
-- Must use c_sim = TRUE to speed up simulation
-- This is a compile-only test bench
-- Usage:
-- Load sim # check that design can load in vsim
-- > as 10 # check that the hierarchy for g_design_name is complete
-- > run -a # check that design can simulate some us without error
LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
ENTITY tb_lofar2_unb2b_adc_one_node IS
END tb_lofar2_unb2b_adc_one_node;
ARCHITECTURE tb OF tb_lofar2_unb2b_adc_one_node IS
CONSTANT c_sim : BOOLEAN := TRUE;
CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
CONSTANT c_node_nr : NATURAL := 0; -- Back node 3
CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
CONSTANT c_ext_clk_period : TIME := 5 ns;
CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
CONSTANT c_pps_period : NATURAL := 1000;
-- Tb
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL sim_done : STD_LOGIC := '0';
-- DUT
SIGNAL ext_clk : STD_LOGIC := '0';
SIGNAL pps : STD_LOGIC := '0';
SIGNAL pps_rst : STD_LOGIC := '0';
SIGNAL WDI : STD_LOGIC;
SIGNAL INTA : STD_LOGIC;
SIGNAL INTB : STD_LOGIC;
SIGNAL eth_clk : STD_LOGIC := '0';
SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC;
SIGNAL pmbus_scl : STD_LOGIC;
SIGNAL pmbus_sda : STD_LOGIC;
-- back transceivers
SIGNAL bck_rx : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL bck_ref_clk : STD_LOGIC := '1';
-- jesd204b syncronization signals
SIGNAL jesd204b_sysref : STD_LOGIC;
SIGNAL jesd204b_sync : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
BEGIN
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
bck_ref_clk <= NOT bck_ref_clk AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
sens_scl <= 'H'; -- pull up
sens_sda <= 'H'; -- pull up
pmbus_scl <= 'H'; -- pull up
pmbus_sda <= 'H'; -- pull up
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
jesd204b_sysref <= pps;
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc_one_node : ENTITY work.lofar2_unb2b_adc_one_node
GENERIC MAP (
g_sim => c_sim,
g_sim_unb_nr => c_unb_nr,
g_sim_node_nr => c_node_nr
)
PORT MAP (
-- GENERAL
CLK => ext_clk,
PPS => pps,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- Others
VERSION => c_version,
ID => c_id,
TESTIO => open,
-- I2C Interface to Sensors
SENS_SC => sens_scl,
SENS_SD => sens_sda,
PMBUS_SC => pmbus_scl,
PMBUS_SD => pmbus_sda,
PMBUS_ALERT => open,
-- 1GbE Control Interface
ETH_CLK => eth_clk,
ETH_SGIN => eth_rxp,
ETH_SGOUT => eth_txp,
-- LEDs
QSFP_LED => open,
-- back transceivers
BCK_RX => bck_rx,
BCK_REF_CLK => bck_ref_clk,
-- jesd204b syncronization signals
JESD204B_SYSREF => jesd204b_sysref,
JESD204B_SYNC => jesd204b_sync
);
------------------------------------------------------------------------------
-- Simulation end
------------------------------------------------------------------------------
sim_done <= '0', '1' AFTER 1 us;
proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
END tb;
\ No newline at end of file
This diff is collapsed.
--------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--------------------------------------------------------------------------------
LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
PACKAGE lofar2_unb2b_adc_pkg IS
-----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
TYPE t_lofar2_unb2b_adc_config IS RECORD
nof_streams_jesd204b : NATURAL;
nof_streams_db : NATURAL;
nof_streams_input : NATURAL;
END RECORD;
-- nofjesd, nofdb, nofinput
CONSTANT c_one_node : t_lofar2_unb2b_adc_config := ( 12, 2, 1 );
CONSTANT c_full : t_lofar2_unb2b_adc_config := ( 12, 2, 12 );
-- Function to select the revision configuration.
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2b_adc_config;
END lofar2_unb2b_adc_pkg;
PACKAGE BODY lofar2_unb2b_adc_pkg IS
FUNCTION func_sel_revision_rec(g_design_name : STRING) RETURN t_lofar2_unb2b_adc_config IS
BEGIN
IF g_design_name = "lofar2_unb2b_adc_one_node" THEN RETURN c_one_node;
ELSIF g_design_name = "lofar2_unb2b_adc_full" THEN RETURN c_full;
ELSE RETURN c_one_node;
END IF;
END;
END lofar2_unb2b_adc_pkg;
-------------------------------------------------------------------------------
--
-- Copyright (C) 2015
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
LIBRARY IEEE, common_lib, unb2b_board_lib, mm_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
USE mm_lib.mm_file_pkg.ALL;
USE mm_lib.mm_file_unb_pkg.ALL;
USE work.qsys_lofar2_unb2b_adc_pkg.ALL;
ENTITY mmm_lofar2_unb2b_adc IS
GENERIC (
g_sim : BOOLEAN := FALSE; --FALSE: use QSYS; TRUE: use mm_file I/O
g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0
);
PORT (
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
pout_wdi : OUT STD_LOGIC;
-- Manual WDI override
reg_wdi_mosi : OUT t_mem_mosi;
reg_wdi_miso : IN t_mem_miso;
-- system_info
reg_unb_system_info_mosi : OUT t_mem_mosi;
reg_unb_system_info_miso : IN t_mem_miso;
rom_unb_system_info_mosi : OUT t_mem_mosi;
rom_unb_system_info_miso : IN t_mem_miso;
-- UniBoard I2C sensors
reg_unb_sens_mosi : OUT t_mem_mosi;
reg_unb_sens_miso : IN t_mem_miso;
reg_fpga_temp_sens_mosi : OUT t_mem_mosi;
reg_fpga_temp_sens_miso : IN t_mem_miso;
reg_fpga_voltage_sens_mosi: OUT t_mem_mosi;
reg_fpga_voltage_sens_miso: IN t_mem_miso;
reg_unb_pmbus_mosi : OUT t_mem_mosi;
reg_unb_pmbus_miso : IN t_mem_miso;
-- PPSH
reg_ppsh_mosi : OUT t_mem_mosi;
reg_ppsh_miso : IN t_mem_miso;
-- eth1g
eth1g_mm_rst : OUT STD_LOGIC;
eth1g_tse_mosi : OUT t_mem_mosi;
eth1g_tse_miso : IN t_mem_miso;
eth1g_reg_mosi : OUT t_mem_mosi;
eth1g_reg_miso : IN t_mem_miso;
eth1g_reg_interrupt : IN STD_LOGIC;
eth1g_ram_mosi : OUT t_mem_mosi;
eth1g_ram_miso : IN t_mem_miso;
-- EPCS read
reg_dpmm_data_mosi : OUT t_mem_mosi;
reg_dpmm_data_miso : IN t_mem_miso;
reg_dpmm_ctrl_mosi : OUT t_mem_mosi;
reg_dpmm_ctrl_miso : IN t_mem_miso;
-- EPCS write
reg_mmdp_data_mosi : OUT t_mem_mosi;
reg_mmdp_data_miso : IN t_mem_miso;
reg_mmdp_ctrl_mosi : OUT t_mem_mosi;
reg_mmdp_ctrl_miso : IN t_mem_miso;
-- EPCS status/control
reg_epcs_mosi : OUT t_mem_mosi;
reg_epcs_miso : IN t_mem_miso;
-- Remote Update
reg_remu_mosi : OUT t_mem_mosi;
reg_remu_miso : IN t_mem_miso;
-- Jesd control
jesd204b_mosi : OUT t_mem_mosi;
jesd204b_miso : IN t_mem_miso;
-- JESD databuffer
ram_diag_data_buf_jesd_mosi : OUT t_mem_mosi;
ram_diag_data_buf_jesd_miso : IN t_mem_miso;
reg_diag_data_buf_jesd_mosi : OUT t_mem_mosi;
reg_diag_data_buf_jesd_miso : IN t_mem_miso
);
END mmm_lofar2_unb2b_adc;
ARCHITECTURE str OF mmm_lofar2_unb2b_adc IS
CONSTANT c_sim_node_nr : NATURAL := g_sim_node_nr;
CONSTANT c_sim_node_type : STRING(1 TO 2):= "FN";
SIGNAL i_reset_n : STD_LOGIC;
BEGIN
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
u_mm_file_reg_unb_pmbus : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_PMBUS")
PORT MAP(mm_rst, mm_clk, reg_unb_pmbus_mosi, reg_unb_pmbus_miso );
u_mm_file_reg_fpga_temp_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_TEMP_SENS")
PORT MAP(mm_rst, mm_clk, reg_fpga_temp_sens_mosi, reg_fpga_temp_sens_miso );
u_mm_file_reg_fpga_voltage_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_FPGA_VOLTAGE_SENS")
PORT MAP(mm_rst, mm_clk, reg_fpga_voltage_sens_mosi, reg_fpga_voltage_sens_miso );
u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
END GENERATE;
i_reset_n <= NOT mm_rst;
----------------------------------------------------------------------------
-- QSYS for synthesis
----------------------------------------------------------------------------
gen_qsys : IF g_sim = FALSE GENERATE
u_qsys : qsys_lofar2_unb2b_adc
PORT MAP (
clk_clk => mm_clk,
reset_reset_n => i_reset_n,
-- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
pio_wdi_external_connection_export => pout_wdi,
avs_eth_0_reset_export => eth1g_mm_rst,
avs_eth_0_clk_export => OPEN,
avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
avs_eth_0_tse_write_export => eth1g_tse_mosi.wr,
avs_eth_0_tse_read_export => eth1g_tse_mosi.rd,
avs_eth_0_tse_writedata_export => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
avs_eth_0_tse_readdata_export => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
avs_eth_0_tse_waitrequest_export => eth1g_tse_miso.waitrequest,
avs_eth_0_reg_address_export => eth1g_reg_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
avs_eth_0_reg_write_export => eth1g_reg_mosi.wr,
avs_eth_0_reg_read_export => eth1g_reg_mosi.rd,
avs_eth_0_reg_writedata_export => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
avs_eth_0_reg_readdata_export => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
avs_eth_0_ram_address_export => eth1g_ram_mosi.address(c_unb2b_board_peripherals_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
avs_eth_0_ram_write_export => eth1g_ram_mosi.wr,
avs_eth_0_ram_read_export => eth1g_ram_mosi.rd,
avs_eth_0_ram_writedata_export => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
avs_eth_0_ram_readdata_export => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
avs_eth_0_irq_export => eth1g_reg_interrupt,
reg_unb_sens_reset_export => OPEN,
reg_unb_sens_clk_export => OPEN,
reg_unb_sens_address_export => reg_unb_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
reg_unb_sens_write_export => reg_unb_sens_mosi.wr,
reg_unb_sens_writedata_export => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_unb_sens_read_export => reg_unb_sens_mosi.rd,
reg_unb_sens_readdata_export => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
reg_unb_pmbus_reset_export => OPEN,
reg_unb_pmbus_clk_export => OPEN,
reg_unb_pmbus_address_export => reg_unb_pmbus_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_pmbus_adr_w-1 DOWNTO 0),
reg_unb_pmbus_write_export => reg_unb_pmbus_mosi.wr,
reg_unb_pmbus_writedata_export => reg_unb_pmbus_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_unb_pmbus_read_export => reg_unb_pmbus_mosi.rd,
reg_unb_pmbus_readdata_export => reg_unb_pmbus_miso.rddata(c_word_w-1 DOWNTO 0),
reg_fpga_temp_sens_reset_export => OPEN,
reg_fpga_temp_sens_clk_export => OPEN,
reg_fpga_temp_sens_address_export => reg_fpga_temp_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_temp_sens_adr_w-1 DOWNTO 0),
reg_fpga_temp_sens_write_export => reg_fpga_temp_sens_mosi.wr,
reg_fpga_temp_sens_writedata_export => reg_fpga_temp_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_fpga_temp_sens_read_export => reg_fpga_temp_sens_mosi.rd,
reg_fpga_temp_sens_readdata_export => reg_fpga_temp_sens_miso.rddata(c_word_w-1 DOWNTO 0),
reg_fpga_voltage_sens_reset_export => OPEN,
reg_fpga_voltage_sens_clk_export => OPEN,
reg_fpga_voltage_sens_address_export => reg_fpga_voltage_sens_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_fpga_voltage_sens_adr_w-1 DOWNTO 0),
reg_fpga_voltage_sens_write_export => reg_fpga_voltage_sens_mosi.wr,
reg_fpga_voltage_sens_writedata_export => reg_fpga_voltage_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_fpga_voltage_sens_read_export => reg_fpga_voltage_sens_mosi.rd,
reg_fpga_voltage_sens_readdata_export => reg_fpga_voltage_sens_miso.rddata(c_word_w-1 DOWNTO 0),
rom_system_info_reset_export => OPEN,
rom_system_info_clk_export => OPEN,
rom_system_info_address_export => rom_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
rom_system_info_write_export => rom_unb_system_info_mosi.wr,
rom_system_info_writedata_export => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
rom_system_info_read_export => rom_unb_system_info_mosi.rd,
rom_system_info_readdata_export => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
pio_system_info_reset_export => OPEN,
pio_system_info_clk_export => OPEN,
pio_system_info_address_export => reg_unb_system_info_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
pio_system_info_write_export => reg_unb_system_info_mosi.wr,
pio_system_info_writedata_export => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
pio_system_info_read_export => reg_unb_system_info_mosi.rd,
pio_system_info_readdata_export => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
pio_pps_reset_export => OPEN,
pio_pps_clk_export => OPEN,
pio_pps_address_export => reg_ppsh_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_ppsh_adr_w-1 DOWNTO 0),
pio_pps_write_export => reg_ppsh_mosi.wr,
pio_pps_writedata_export => reg_ppsh_mosi.wrdata(c_word_w-1 DOWNTO 0),
pio_pps_read_export => reg_ppsh_mosi.rd,
pio_pps_readdata_export => reg_ppsh_miso.rddata(c_word_w-1 DOWNTO 0),
reg_wdi_reset_export => OPEN,
reg_wdi_clk_export => OPEN,
reg_wdi_address_export => reg_wdi_mosi.address(0 DOWNTO 0),
reg_wdi_write_export => reg_wdi_mosi.wr,
reg_wdi_writedata_export => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_wdi_read_export => reg_wdi_mosi.rd,
reg_wdi_readdata_export => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
reg_remu_reset_export => OPEN,
reg_remu_clk_export => OPEN,
reg_remu_address_export => reg_remu_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_remu_adr_w-1 DOWNTO 0),
reg_remu_write_export => reg_remu_mosi.wr,
reg_remu_writedata_export => reg_remu_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_remu_read_export => reg_remu_mosi.rd,
reg_remu_readdata_export => reg_remu_miso.rddata(c_word_w-1 DOWNTO 0),
jesd204b_reset_export => OPEN,
jesd204b_clk_export => OPEN,
jesd204b_address_export => jesd204b_mosi.address(11 DOWNTO 0),
jesd204b_write_export => jesd204b_mosi.wr,
jesd204b_writedata_export => jesd204b_mosi.wrdata(c_word_w-1 DOWNTO 0),
jesd204b_read_export => jesd204b_mosi.rd,
jesd204b_readdata_export => jesd204b_miso.rddata(c_word_w-1 DOWNTO 0),
reg_epcs_reset_export => OPEN,
reg_epcs_clk_export => OPEN,
reg_epcs_address_export => reg_epcs_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_epcs_adr_w-1 DOWNTO 0),
reg_epcs_write_export => reg_epcs_mosi.wr,
reg_epcs_writedata_export => reg_epcs_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_epcs_read_export => reg_epcs_mosi.rd,
reg_epcs_readdata_export => reg_epcs_miso.rddata(c_word_w-1 DOWNTO 0),
reg_dpmm_ctrl_reset_export => OPEN,
reg_dpmm_ctrl_clk_export => OPEN,
reg_dpmm_ctrl_address_export => reg_dpmm_ctrl_mosi.address(0 DOWNTO 0),
reg_dpmm_ctrl_write_export => reg_dpmm_ctrl_mosi.wr,
reg_dpmm_ctrl_writedata_export => reg_dpmm_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_dpmm_ctrl_read_export => reg_dpmm_ctrl_mosi.rd,
reg_dpmm_ctrl_readdata_export => reg_dpmm_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
reg_mmdp_data_reset_export => OPEN,
reg_mmdp_data_clk_export => OPEN,
reg_mmdp_data_address_export => reg_mmdp_data_mosi.address(0 DOWNTO 0),
reg_mmdp_data_write_export => reg_mmdp_data_mosi.wr,
reg_mmdp_data_writedata_export => reg_mmdp_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_mmdp_data_read_export => reg_mmdp_data_mosi.rd,
reg_mmdp_data_readdata_export => reg_mmdp_data_miso.rddata(c_word_w-1 DOWNTO 0),
reg_dpmm_data_reset_export => OPEN,
reg_dpmm_data_clk_export => OPEN,
reg_dpmm_data_address_export => reg_dpmm_data_mosi.address(0 DOWNTO 0),
reg_dpmm_data_read_export => reg_dpmm_data_mosi.rd,
reg_dpmm_data_readdata_export => reg_dpmm_data_miso.rddata(c_word_w-1 DOWNTO 0),
reg_dpmm_data_write_export => reg_dpmm_data_mosi.wr,
reg_dpmm_data_writedata_export => reg_dpmm_data_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_mmdp_ctrl_reset_export => OPEN,
reg_mmdp_ctrl_clk_export => OPEN,
reg_mmdp_ctrl_address_export => reg_mmdp_ctrl_mosi.address(0 DOWNTO 0),
reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buf_jesd_clk_export => OPEN,
ram_diag_data_buf_jesd_reset_export => OPEN,
ram_diag_data_buf_jesd_address_export => ram_diag_data_buf_jesd_mosi.address(17-1 DOWNTO 0),
ram_diag_data_buf_jesd_write_export => ram_diag_data_buf_jesd_mosi.wr,
ram_diag_data_buf_jesd_writedata_export => ram_diag_data_buf_jesd_mosi.wrdata(c_word_w-1 DOWNTO 0),
ram_diag_data_buf_jesd_read_export => ram_diag_data_buf_jesd_mosi.rd,
ram_diag_data_buf_jesd_readdata_export => ram_diag_data_buf_jesd_miso.rddata(c_word_w-1 DOWNTO 0),
reg_diag_data_buf_jesd_reset_export => OPEN,
reg_diag_data_buf_jesd_clk_export => OPEN,
reg_diag_data_buf_jesd_address_export => reg_diag_data_buf_jesd_mosi.address(12-1 DOWNTO 0),
reg_diag_data_buf_jesd_write_export => reg_diag_data_buf_jesd_mosi.wr,
reg_diag_data_buf_jesd_writedata_export => reg_diag_data_buf_jesd_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_diag_data_buf_jesd_read_export => reg_diag_data_buf_jesd_mosi.rd,
reg_diag_data_buf_jesd_readdata_export => reg_diag_data_buf_jesd_miso.rddata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
END str;
-------------------------------------------------------------------------------
--
-- Copyright (C) 2018
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-- Author: Jonathan Hargreaves
-- Purpose: Tb to show that lofar2_unb2b_adc can simulate
-- Description:
-- Must use c_sim = TRUE to speed up simulation
-- This is a compile-only test bench
-- Usage:
-- Load sim # check that design can load in vsim
-- > as 10 # check that the hierarchy for g_design_name is complete
-- > run -a # check that design can simulate some us without error
LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE unb2b_board_lib.unb2b_board_pkg.ALL;
USE common_lib.tb_common_pkg.ALL;
ENTITY tb_lofar2_unb2b_adc IS
END tb_lofar2_unb2b_adc;
ARCHITECTURE tb OF tb_lofar2_unb2b_adc IS
CONSTANT c_sim : BOOLEAN := TRUE;
CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
CONSTANT c_node_nr : NATURAL := 0; -- Back node 3
CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
CONSTANT c_ext_clk_period : TIME := 5 ns;
CONSTANT c_bck_ref_clk_period : TIME := 5 ns;
CONSTANT c_pps_period : NATURAL := 1000;
-- Tb
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL sim_done : STD_LOGIC := '0';
-- DUT
SIGNAL ext_clk : STD_LOGIC := '0';
SIGNAL pps : STD_LOGIC := '0';
SIGNAL pps_rst : STD_LOGIC := '0';
SIGNAL WDI : STD_LOGIC;
SIGNAL INTA : STD_LOGIC;
SIGNAL INTB : STD_LOGIC;
SIGNAL eth_clk : STD_LOGIC := '0';
SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
SIGNAL sens_scl : STD_LOGIC;
SIGNAL sens_sda : STD_LOGIC;
SIGNAL pmbus_scl : STD_LOGIC;
SIGNAL pmbus_sda : STD_LOGIC;
-- back transceivers
SIGNAL bck_rx : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
SIGNAL bck_ref_clk : STD_LOGIC := '1';
-- jesd204b syncronization signals
SIGNAL jesd204b_sysref : STD_LOGIC;
SIGNAL jesd204b_sync : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
BEGIN
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
bck_ref_clk <= NOT bck_ref_clk AFTER c_bck_ref_clk_period/2; -- JESD sample clock (200MHz)
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
sens_scl <= 'H'; -- pull up
sens_sda <= 'H'; -- pull up
pmbus_scl <= 'H'; -- pull up
pmbus_sda <= 'H'; -- pull up
------------------------------------------------------------------------------
-- External PPS
------------------------------------------------------------------------------
proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
jesd204b_sysref <= pps;
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_lofar_unb2b_adc : ENTITY work.lofar2_unb2b_adc
GENERIC MAP (
g_design_name => "lofar2_unb2b_adc_one_node",
g_design_note => "Lofar2 adc with one node",
g_sim => c_sim,
g_sim_unb_nr => c_unb_nr,
g_sim_node_nr => c_node_nr
)
PORT MAP (
-- GENERAL
CLK => ext_clk,
PPS => pps,
WDI => WDI,
INTA => INTA,
INTB => INTB,
-- Others
VERSION => c_version,
ID => c_id,
TESTIO => open,
-- I2C Interface to Sensors
SENS_SC => sens_scl,
SENS_SD => sens_sda,
PMBUS_SC => pmbus_scl,
PMBUS_SD => pmbus_sda,
PMBUS_ALERT => open,
-- 1GbE Control Interface
ETH_CLK => eth_clk,
ETH_SGIN => eth_rxp,
ETH_SGOUT => eth_txp,
-- LEDs
QSFP_LED => open,
-- back transceivers
BCK_RX => bck_rx,
BCK_REF_CLK => bck_ref_clk,
-- jesd204b syncronization signals
JESD204B_SYSREF => jesd204b_sysref,
JESD204B_SYNC => jesd204b_sync
);
------------------------------------------------------------------------------
-- Simulation end
------------------------------------------------------------------------------
sim_done <= '0', '1' AFTER 1 us;
proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
END tb;
\ No newline at end of file
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
<interface name="board" port="kernel_stream_snk_10GbE" type="streamsink" width="72" chan_id="kernel_output_10GbE"/> <interface name="board" port="kernel_stream_snk_10GbE" type="streamsink" width="72" chan_id="kernel_output_10GbE"/>
<interface name="board" port="kernel_stream_src_40GbE" type="streamsource" width="264" chan_id="kernel_input_40GbE"/> <interface name="board" port="kernel_stream_src_40GbE" type="streamsource" width="264" chan_id="kernel_input_40GbE"/>
<interface name="board" port="kernel_stream_snk_40GbE" type="streamsink" width="264" chan_id="kernel_output_40GbE"/> <interface name="board" port="kernel_stream_snk_40GbE" type="streamsink" width="264" chan_id="kernel_output_40GbE"/>
<interface name="board" port="kernel_stream_src_ADC" type="streamsource" width="16" chan_id="kernel_input_ADC"/>
</channels> </channels>
<host> <host>
......
...@@ -22,6 +22,7 @@ source ctrl_unb2_board.tcl ...@@ -22,6 +22,7 @@ source ctrl_unb2_board.tcl
source ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.tcl source ip/ta2_unb2b_1GbE_mc/ta2_unb2b_1GbE_mc.tcl
source ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.tcl source ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.tcl
source ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.tcl source ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.tcl
source ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.tcl
#============================================================ #============================================================
# Files and basic settings # Files and basic settings
#============================================================ #============================================================
...@@ -256,6 +257,11 @@ set_instance_assignment -name IO_STANDARD LVDS -to SA_CLK ...@@ -256,6 +257,11 @@ set_instance_assignment -name IO_STANDARD LVDS -to SA_CLK
# internal termination should be enabled. # internal termination should be enabled.
set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to SA_CLK set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to SA_CLK
set_location_assignment PIN_V9 -to BCK_REF_CLK
set_location_assignment PIN_V10 -to "BCK_REF_CLK(n)"
set_instance_assignment -name IO_STANDARD LVDS -to BCK_REF_CLK
set_instance_assignment -name IO_STANDARD LVDS -to "BCK_REF_CLK(n)"
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
### QSFP_0 ### QSFP_0
...@@ -460,6 +466,33 @@ set_location_assignment PIN_AD44 -to QSFP_1_TX[1] ...@@ -460,6 +466,33 @@ set_location_assignment PIN_AD44 -to QSFP_1_TX[1]
set_location_assignment PIN_AF44 -to QSFP_1_TX[2] set_location_assignment PIN_AF44 -to QSFP_1_TX[2]
set_location_assignment PIN_AG42 -to QSFP_1_TX[3] set_location_assignment PIN_AG42 -to QSFP_1_TX[3]
set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to BCK_RX[0]
set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to BCK_RX[0]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to BCK_RX[0]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to BCK_RX[0]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to BCK_RX[0]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to BCK_RX[0]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to BCK_RX[0]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to BCK_RX[0]
set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to BCK_RX[0]
set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to BCK_RX[0]
set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_12 -to BCK_RX[0]
set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to BCK_RX[0]
set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_3 -to BCK_RX[0]
set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to BCK_RX[0]
set_location_assignment PIN_BA7 -to BCK_RX[0]
set_location_assignment PIN_V12 -to JESD204B_SYSREF
set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYSREF
set_location_assignment PIN_U12 -to JESD204B_SYNC[0]
set_instance_assignment -name IO_STANDARD "1.8 V" -to JESD204B_SYNC[0]
set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_40GbE.ip set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_40GbE.ip
set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_10GbE.ip set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_10GbE.ip
set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_1GbE_mc.ip set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_1GbE_mc.ip
set_global_assignment -name IP_FILE ip/board/board_ta2_unb2b_jesd204b.ip
...@@ -38,6 +38,9 @@ module freeze_wrapper( ...@@ -38,6 +38,9 @@ module freeze_wrapper(
input [7:0] board_kernel_cra_byteenable, input [7:0] board_kernel_cra_byteenable,
input board_kernel_cra_debugaccess, input board_kernel_cra_debugaccess,
input wire [15:0] board_kernel_stream_src_ADC_data,
input wire board_kernel_stream_src_ADC_valid,
output wire board_kernel_stream_src_ADC_ready,
input wire [39:0] board_kernel_stream_src_1GbE_data, input wire [39:0] board_kernel_stream_src_1GbE_data,
input wire board_kernel_stream_src_1GbE_valid, input wire board_kernel_stream_src_1GbE_valid,
...@@ -203,7 +206,9 @@ pr_region pr_region_inst ...@@ -203,7 +206,9 @@ pr_region pr_region_inst
.kernel_stream_snk_1GbE_data(board_kernel_stream_snk_1GbE_data), .kernel_stream_snk_1GbE_data(board_kernel_stream_snk_1GbE_data),
.kernel_stream_snk_1GbE_ready(board_kernel_stream_snk_1GbE_ready), .kernel_stream_snk_1GbE_ready(board_kernel_stream_snk_1GbE_ready),
.kernel_stream_snk_1GbE_valid(board_kernel_stream_snk_1GbE_valid), .kernel_stream_snk_1GbE_valid(board_kernel_stream_snk_1GbE_valid),
.kernel_stream_src_ADC_data(board_kernel_stream_src_ADC_data),
.kernel_stream_src_ADC_ready(board_kernel_stream_src_ADC_ready),
.kernel_stream_src_ADC_valid(board_kernel_stream_src_ADC_valid),
.kernel_register_mem_address(board_kernel_register_mem_address), .kernel_register_mem_address(board_kernel_register_mem_address),
.kernel_register_mem_clken(board_kernel_register_mem_clken), .kernel_register_mem_clken(board_kernel_register_mem_clken),
.kernel_register_mem_chipselect(board_kernel_register_mem_chipselect), .kernel_register_mem_chipselect(board_kernel_register_mem_chipselect),
......
...@@ -43,6 +43,10 @@ module pr_region ( ...@@ -43,6 +43,10 @@ module pr_region (
output wire [255:0] kernel_register_mem_writedata, output wire [255:0] kernel_register_mem_writedata,
output wire [31:0] kernel_register_mem_byteenable, output wire [31:0] kernel_register_mem_byteenable,
input wire [15:0] kernel_stream_src_ADC_data,
input wire kernel_stream_src_ADC_valid,
output wire kernel_stream_src_ADC_ready,
input wire [39:0] kernel_stream_src_1GbE_data, input wire [39:0] kernel_stream_src_1GbE_data,
input wire kernel_stream_src_1GbE_valid, input wire kernel_stream_src_1GbE_valid,
output wire kernel_stream_src_1GbE_ready, output wire kernel_stream_src_1GbE_ready,
...@@ -190,7 +194,12 @@ kernel_system kernel_system_inst ...@@ -190,7 +194,12 @@ kernel_system kernel_system_inst
.kernel_output_1GbE_data(kernel_stream_snk_1GbE_data), .kernel_output_1GbE_data(kernel_stream_snk_1GbE_data),
.kernel_output_1GbE_ready(kernel_stream_snk_1GbE_ready), .kernel_output_1GbE_ready(kernel_stream_snk_1GbE_ready),
.kernel_output_1GbE_valid(kernel_stream_snk_1GbE_valid) .kernel_output_1GbE_valid(kernel_stream_snk_1GbE_valid),
.kernel_input_ADC_data(kernel_stream_src_ADC_data),
.kernel_input_ADC_ready(kernel_stream_src_ADC_ready),
.kernel_input_ADC_valid(kernel_stream_src_ADC_valid)
// .kernel_mem0_address(pipelined_kernel_mem0_s0_address), // .kernel_mem0_address(pipelined_kernel_mem0_s0_address),
// .kernel_mem0_read(pipelined_kernel_mem0_s0_read), // .kernel_mem0_read(pipelined_kernel_mem0_s0_read),
......
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