cleaned up the code

libraries/technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd

@@ -236,10 +236,11 @@ BEGIN
     g_nof_channels   => g_nof_channels
   )
   PORT MAP (
-   mm_clk              => mm_clk,
-   mm_rst              => mm_rst, 
-   reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi =>  reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi,
-   reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso =>  reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso,
+    mm_clk              => mm_clk,
+    mm_rst              => mm_rst, 
+
+    reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi =>  reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi,
+    reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso =>  reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso,
 
     -- Transceiver PLL reference clock
     tr_ref_clk_644     => tr_ref_clk_644,