From 3f10247c84251b84dd5e0487182322356d09c835 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Fri, 18 Aug 2017 07:48:51 +0000
Subject: [PATCH] cleaned up the code
---
.../technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/libraries/technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd b/libraries/technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd
index 895226b7c0..6c32d7e75d 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd
@@ -236,10 +236,11 @@ BEGIN
g_nof_channels => g_nof_channels
)
PORT MAP (
- mm_clk => mm_clk,
- mm_rst => mm_rst,
- reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi,
- reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso => reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso,
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi => reg_ip_arria10_e3sge3_phy_10gbase_r_24_mosi,
+ reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso => reg_ip_arria10_e3sge3_phy_10gbase_r_24_miso,
-- Transceiver PLL reference clock
tr_ref_clk_644 => tr_ref_clk_644,
--
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