Use hdl_lib_include and unb*_board to include the 25M and 200M PLL IP for unb1...

Use hdl_lib_include and unb*_board to include the 25M and 200M PLL IP for unb1 and the 125M and 200M PLL IP for unb2, unb2a

boards/uniboard1/libraries/unb1_board/hdllib.cfg

@@ -4,6 +4,8 @@ hdl_lib_uses_synth = common dp diag uth ppsh i2c tr_nonbonded eth remu technolog
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_stratixiv
 hdl_lib_include_ip = ip_stratixiv_tse_sgmii_lvds
+                     ip_stratixiv_pll
+                     ip_stratixiv_pll_clk25
 
 synth_files =
     src/vhdl/unb1_board_pkg.vhd

boards/uniboard2/libraries/unb2_board/hdllib.cfg

@@ -4,6 +4,11 @@ hdl_lib_uses_synth = common dp ppsh i2c eth remu technology tech_clkbuf tech_pll
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10
 hdl_lib_include_ip = ip_arria10_tse_sgmii_lvds
+                     ip_arria10_fractional_pll_clk200
+                     ip_arria10_fractional_pll_clk125
+                     #ip_arria10_pll_clk200
+                     #ip_arria10_pll_clk25
+                     #ip_arria10_pll_clk125
 
 synth_files =
     src/vhdl/unb2_board_pkg.vhd

boards/uniboard2a/libraries/unb2a_board/hdllib.cfg

@@ -4,6 +4,11 @@ hdl_lib_uses_synth = common dp ppsh i2c eth remu technology tech_clkbuf tech_pll
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e3sge3
 hdl_lib_include_ip = ip_arria10_e3sge3_tse_sgmii_lvds
+                     ip_arria10_e3sge3_fractional_pll_clk200
+                     ip_arria10_e3sge3_fractional_pll_clk125
+                     #ip_arria10_e3sge3_pll_clk200
+                     #ip_arria10_e3sge3_pll_clk25
+                     #ip_arria10_e3sge3_pll_clk125
 
 synth_files =
     src/vhdl/unb2_board_pkg.vhd

libraries/technology/fractional_pll/hdllib.cfg

 hdl_lib_name = tech_fractional_pll
 hdl_library_clause_name = tech_fractional_pll_lib
-hdl_lib_uses_synth = technology ip_arria10_fractional_pll_clk200 ip_arria10_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk200 ip_arria10_e3sge3_fractional_pll_clk125 common
+hdl_lib_uses_synth = technology common
+hdl_lib_uses_ip = ip_arria10_fractional_pll_clk200 ip_arria10_e3sge3_fractional_pll_clk200
+                  ip_arria10_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk125
 hdl_lib_uses_sim = 
 hdl_lib_technology = 
 

libraries/technology/pll/hdllib.cfg

 hdl_lib_name = tech_pll
 hdl_library_clause_name = tech_pll_lib
-hdl_lib_uses_synth = technology 
-                     ip_stratixiv_pll
-                     ip_arria10_pll_xgmii_mac_clocks
-                     ip_arria10_pll_clk200
-                     ip_arria10_pll_clk25
-                     ip_stratixiv_pll_clk25
-                     ip_arria10_pll_clk125
-                     ip_arria10_e3sge3_pll_xgmii_mac_clocks
-                     ip_arria10_e3sge3_pll_clk200
-                     ip_arria10_e3sge3_pll_clk25
-                     ip_arria10_e3sge3_pll_clk125
-                     common
+hdl_lib_uses_synth = technology common ip_arria10_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks
+hdl_lib_uses_ip = ip_stratixiv_pll       ip_arria10_pll_clk200           ip_arria10_e3sge3_pll_clk200
+                  ip_stratixiv_pll_clk25 ip_arria10_pll_clk25            ip_arria10_e3sge3_pll_clk25
+                                         ip_arria10_pll_clk125           ip_arria10_e3sge3_pll_clk125
 hdl_lib_uses_sim = 
 hdl_lib_technology =