From 3e0c09984fb2de812d7d0f4fa8e56d4666d4487d Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 28 Apr 2016 14:26:54 +0000
Subject: [PATCH] Use hdl_lib_include and unb*_board to include the 25M and
200M PLL IP for unb1 and the 125M and 200M PLL IP for unb2, unb2a
---
boards/uniboard1/libraries/unb1_board/hdllib.cfg | 2 ++
boards/uniboard2/libraries/unb2_board/hdllib.cfg | 5 +++++
.../uniboard2a/libraries/unb2a_board/hdllib.cfg | 5 +++++
libraries/technology/fractional_pll/hdllib.cfg | 4 +++-
libraries/technology/pll/hdllib.cfg | 16 ++++------------
5 files changed, 19 insertions(+), 13 deletions(-)
diff --git a/boards/uniboard1/libraries/unb1_board/hdllib.cfg b/boards/uniboard1/libraries/unb1_board/hdllib.cfg
index 88fe5199cb..2b2a2d30eb 100644
--- a/boards/uniboard1/libraries/unb1_board/hdllib.cfg
+++ b/boards/uniboard1/libraries/unb1_board/hdllib.cfg
@@ -4,6 +4,8 @@ hdl_lib_uses_synth = common dp diag uth ppsh i2c tr_nonbonded eth remu technolog
hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
hdl_lib_include_ip = ip_stratixiv_tse_sgmii_lvds
+ ip_stratixiv_pll
+ ip_stratixiv_pll_clk25
synth_files =
src/vhdl/unb1_board_pkg.vhd
diff --git a/boards/uniboard2/libraries/unb2_board/hdllib.cfg b/boards/uniboard2/libraries/unb2_board/hdllib.cfg
index 8e2b31afa9..7a50752cd4 100644
--- a/boards/uniboard2/libraries/unb2_board/hdllib.cfg
+++ b/boards/uniboard2/libraries/unb2_board/hdllib.cfg
@@ -4,6 +4,11 @@ hdl_lib_uses_synth = common dp ppsh i2c eth remu technology tech_clkbuf tech_pll
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10
hdl_lib_include_ip = ip_arria10_tse_sgmii_lvds
+ ip_arria10_fractional_pll_clk200
+ ip_arria10_fractional_pll_clk125
+ #ip_arria10_pll_clk200
+ #ip_arria10_pll_clk25
+ #ip_arria10_pll_clk125
synth_files =
src/vhdl/unb2_board_pkg.vhd
diff --git a/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg b/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg
index 1b94bb3bcd..95c5c1ab40 100644
--- a/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg
+++ b/boards/uniboard2a/libraries/unb2a_board/hdllib.cfg
@@ -4,6 +4,11 @@ hdl_lib_uses_synth = common dp ppsh i2c eth remu technology tech_clkbuf tech_pll
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e3sge3
hdl_lib_include_ip = ip_arria10_e3sge3_tse_sgmii_lvds
+ ip_arria10_e3sge3_fractional_pll_clk200
+ ip_arria10_e3sge3_fractional_pll_clk125
+ #ip_arria10_e3sge3_pll_clk200
+ #ip_arria10_e3sge3_pll_clk25
+ #ip_arria10_e3sge3_pll_clk125
synth_files =
src/vhdl/unb2_board_pkg.vhd
diff --git a/libraries/technology/fractional_pll/hdllib.cfg b/libraries/technology/fractional_pll/hdllib.cfg
index e9cc301c17..45a623dcb0 100644
--- a/libraries/technology/fractional_pll/hdllib.cfg
+++ b/libraries/technology/fractional_pll/hdllib.cfg
@@ -1,6 +1,8 @@
hdl_lib_name = tech_fractional_pll
hdl_library_clause_name = tech_fractional_pll_lib
-hdl_lib_uses_synth = technology ip_arria10_fractional_pll_clk200 ip_arria10_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk200 ip_arria10_e3sge3_fractional_pll_clk125 common
+hdl_lib_uses_synth = technology common
+hdl_lib_uses_ip = ip_arria10_fractional_pll_clk200 ip_arria10_e3sge3_fractional_pll_clk200
+ ip_arria10_fractional_pll_clk125 ip_arria10_e3sge3_fractional_pll_clk125
hdl_lib_uses_sim =
hdl_lib_technology =
diff --git a/libraries/technology/pll/hdllib.cfg b/libraries/technology/pll/hdllib.cfg
index 25b1d8f50a..c3a56f5f93 100644
--- a/libraries/technology/pll/hdllib.cfg
+++ b/libraries/technology/pll/hdllib.cfg
@@ -1,17 +1,9 @@
hdl_lib_name = tech_pll
hdl_library_clause_name = tech_pll_lib
-hdl_lib_uses_synth = technology
- ip_stratixiv_pll
- ip_arria10_pll_xgmii_mac_clocks
- ip_arria10_pll_clk200
- ip_arria10_pll_clk25
- ip_stratixiv_pll_clk25
- ip_arria10_pll_clk125
- ip_arria10_e3sge3_pll_xgmii_mac_clocks
- ip_arria10_e3sge3_pll_clk200
- ip_arria10_e3sge3_pll_clk25
- ip_arria10_e3sge3_pll_clk125
- common
+hdl_lib_uses_synth = technology common ip_arria10_pll_xgmii_mac_clocks ip_arria10_e3sge3_pll_xgmii_mac_clocks
+hdl_lib_uses_ip = ip_stratixiv_pll ip_arria10_pll_clk200 ip_arria10_e3sge3_pll_clk200
+ ip_stratixiv_pll_clk25 ip_arria10_pll_clk25 ip_arria10_e3sge3_pll_clk25
+ ip_arria10_pll_clk125 ip_arria10_e3sge3_pll_clk125
hdl_lib_uses_sim =
hdl_lib_technology =
--
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