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Commit 3db7f083 authored by Reinier van der Walle's avatar Reinier van der Walle
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removed constant usage for Vivado IP packager

parent 3ed294cf
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1 merge request!327Resolve HPR-85
Pipeline #48090 passed
Stage: linting
Stage: simulation
Stage: synthesis
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libraries/io/eth/src/vhdl/eth_tester_axi4_wrapper.vhd
+ 70
− 70
View file @ 3db7f083
......@@ -31,7 +31,7 @@ USE axi4_lib.axi4_lite_pkg.ALL;
USE work.eth_pkg.ALL;
USE work.eth_tester_pkg.ALL;
ENTITY eth_tester_axi4_wrapper IS
ENTITY eth_tester_axi4_wrapper IS
PORT (
-- Clocks and reset
mm_clk : IN STD_LOGIC;
......@@ -39,9 +39,9 @@ ENTITY eth_tester_axi4_wrapper IS
st_pps : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
-- UDP transmit interface
eth_src_mac : IN STD_LOGIC_VECTOR(c_network_eth_mac_addr_w-1 DOWNTO 0);
ip_src_addr : IN STD_LOGIC_VECTOR(c_network_ip_addr_w-1 DOWNTO 0);
udp_src_port : IN STD_LOGIC_VECTOR(c_network_udp_port_w-1 DOWNTO 0);
eth_src_mac : IN STD_LOGIC_VECTOR(6*8-1 DOWNTO 0);
ip_src_addr : IN STD_LOGIC_VECTOR(4*8-1 DOWNTO 0);
udp_src_port : IN STD_LOGIC_VECTOR(2*8-1 DOWNTO 0);
tx_fifo_rd_emp_arr : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
......@@ -51,13 +51,13 @@ ENTITY eth_tester_axi4_wrapper IS
-- Source Out and Sink In
tx_udp_tvalid : OUT STD_LOGIC;
tx_udp_tdata : OUT STD_LOGIC_VECTOR(c_axi4_stream_data_w-1 DOWNTO 0);
tx_udp_tstrb : OUT STD_LOGIC_VECTOR(c_axi4_stream_strb_w-1 DOWNTO 0);
tx_udp_tkeep : OUT STD_LOGIC_VECTOR(c_axi4_stream_keep_w-1 DOWNTO 0);
tx_udp_tdata : OUT STD_LOGIC_VECTOR(512-1 DOWNTO 0);
tx_udp_tstrb : OUT STD_LOGIC_VECTOR(512/8-1 DOWNTO 0);
tx_udp_tkeep : OUT STD_LOGIC_VECTOR(512/8-1 DOWNTO 0);
tx_udp_tlast : OUT STD_LOGIC;
tx_udp_tid : OUT STD_LOGIC_VECTOR(c_axi4_stream_tid_w-1 DOWNTO 0);
tx_udp_tdest : OUT STD_LOGIC_VECTOR(c_axi4_stream_dest_w-1 DOWNTO 0);
tx_udp_tuser : OUT STD_LOGIC_VECTOR(c_axi4_stream_user_w-1 DOWNTO 0);
tx_udp_tid : OUT STD_LOGIC_VECTOR(4-1 DOWNTO 0);
tx_udp_tdest : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0);
tx_udp_tuser : OUT STD_LOGIC_VECTOR(70-1 DOWNTO 0);
-- rx_udp
-- Source In and Sink Out
......@@ -65,150 +65,150 @@ ENTITY eth_tester_axi4_wrapper IS
-- Source Out and Sink In
rx_udp_tvalid : IN STD_LOGIC;
rx_udp_tdata : IN STD_LOGIC_VECTOR(c_axi4_stream_data_w-1 DOWNTO 0);
rx_udp_tstrb : IN STD_LOGIC_VECTOR(c_axi4_stream_strb_w-1 DOWNTO 0);
rx_udp_tkeep : IN STD_LOGIC_VECTOR(c_axi4_stream_keep_w-1 DOWNTO 0);
rx_udp_tdata : IN STD_LOGIC_VECTOR(512-1 DOWNTO 0);
rx_udp_tstrb : IN STD_LOGIC_VECTOR(512/8-1 DOWNTO 0);
rx_udp_tkeep : IN STD_LOGIC_VECTOR(512/8-1 DOWNTO 0);
rx_udp_tlast : IN STD_LOGIC;
rx_udp_tid : IN STD_LOGIC_VECTOR(c_axi4_stream_tid_w-1 DOWNTO 0);
rx_udp_tdest : IN STD_LOGIC_VECTOR(c_axi4_stream_dest_w-1 DOWNTO 0);
rx_udp_tuser : IN STD_LOGIC_VECTOR(c_axi4_stream_user_w-1 DOWNTO 0);
rx_udp_tid : IN STD_LOGIC_VECTOR(4-1 DOWNTO 0);
rx_udp_tdest : IN STD_LOGIC_VECTOR(32-1 DOWNTO 0);
rx_udp_tuser : IN STD_LOGIC_VECTOR(70-1 DOWNTO 0);
-- reg_bg_ctrl
-- copi
reg_bg_ctrl_awaddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
reg_bg_ctrl_awprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
reg_bg_ctrl_awaddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_bg_ctrl_awprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_bg_ctrl_awvalid : IN STD_LOGIC;
reg_bg_ctrl_wdata : IN STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
reg_bg_ctrl_wstrb : IN STD_LOGIC_VECTOR((c_axi4_lite_data_w/c_byte_w)-1 downto 0);
reg_bg_ctrl_wdata : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_bg_ctrl_wstrb : IN STD_LOGIC_VECTOR((32/8)-1 downto 0);
reg_bg_ctrl_wvalid : IN STD_LOGIC;
reg_bg_ctrl_bready : IN STD_LOGIC;
reg_bg_ctrl_araddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
reg_bg_ctrl_arprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
reg_bg_ctrl_araddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_bg_ctrl_arprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_bg_ctrl_arvalid : IN STD_LOGIC;
reg_bg_ctrl_rready : IN STD_LOGIC;
-- cipo
reg_bg_ctrl_awready : OUT STD_LOGIC;
reg_bg_ctrl_wready : OUT STD_LOGIC;
reg_bg_ctrl_bresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
reg_bg_ctrl_bresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_bg_ctrl_bvalid : OUT STD_LOGIC;
reg_bg_ctrl_arready : OUT STD_LOGIC;
reg_bg_ctrl_rdata : OUT STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
reg_bg_ctrl_rresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
reg_bg_ctrl_rdata : OUT STD_LOGIC_VECTOR(32-1 downto 0);
reg_bg_ctrl_rresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_bg_ctrl_rvalid : OUT STD_LOGIC;
-- reg_hdr_dat
-- copi
reg_hdr_dat_awaddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
reg_hdr_dat_awprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
reg_hdr_dat_awaddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_hdr_dat_awprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_hdr_dat_awvalid : IN STD_LOGIC;
reg_hdr_dat_wdata : IN STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
reg_hdr_dat_wstrb : IN STD_LOGIC_VECTOR((c_axi4_lite_data_w/c_byte_w)-1 downto 0);
reg_hdr_dat_wdata : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_hdr_dat_wstrb : IN STD_LOGIC_VECTOR((32/8)-1 downto 0);
reg_hdr_dat_wvalid : IN STD_LOGIC;
reg_hdr_dat_bready : IN STD_LOGIC;
reg_hdr_dat_araddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
reg_hdr_dat_arprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
reg_hdr_dat_araddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_hdr_dat_arprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_hdr_dat_arvalid : IN STD_LOGIC;
reg_hdr_dat_rready : IN STD_LOGIC;
-- cipo
reg_hdr_dat_awready : OUT STD_LOGIC;
reg_hdr_dat_wready : OUT STD_LOGIC;
reg_hdr_dat_bresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
reg_hdr_dat_bresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_hdr_dat_bvalid : OUT STD_LOGIC;
reg_hdr_dat_arready : OUT STD_LOGIC;
reg_hdr_dat_rdata : OUT STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
reg_hdr_dat_rresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
reg_hdr_dat_rdata : OUT STD_LOGIC_VECTOR(32-1 downto 0);
reg_hdr_dat_rresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_hdr_dat_rvalid : OUT STD_LOGIC;
-- reg_bsn_monitor_v2_tx
-- copi
reg_bsn_monitor_v2_tx_awaddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
reg_bsn_monitor_v2_tx_awprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
reg_bsn_monitor_v2_tx_awaddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_bsn_monitor_v2_tx_awprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_bsn_monitor_v2_tx_awvalid : IN STD_LOGIC;
reg_bsn_monitor_v2_tx_wdata : IN STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
reg_bsn_monitor_v2_tx_wstrb : IN STD_LOGIC_VECTOR((c_axi4_lite_data_w/c_byte_w)-1 downto 0);
reg_bsn_monitor_v2_tx_wdata : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_bsn_monitor_v2_tx_wstrb : IN STD_LOGIC_VECTOR((32/8)-1 downto 0);
reg_bsn_monitor_v2_tx_wvalid : IN STD_LOGIC;
reg_bsn_monitor_v2_tx_bready : IN STD_LOGIC;
reg_bsn_monitor_v2_tx_araddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
reg_bsn_monitor_v2_tx_arprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
reg_bsn_monitor_v2_tx_araddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_bsn_monitor_v2_tx_arprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_bsn_monitor_v2_tx_arvalid : IN STD_LOGIC;
reg_bsn_monitor_v2_tx_rready : IN STD_LOGIC;
-- cipo
reg_bsn_monitor_v2_tx_awready : OUT STD_LOGIC;
reg_bsn_monitor_v2_tx_wready : OUT STD_LOGIC;
reg_bsn_monitor_v2_tx_bresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
reg_bsn_monitor_v2_tx_bresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_bsn_monitor_v2_tx_bvalid : OUT STD_LOGIC;
reg_bsn_monitor_v2_tx_arready : OUT STD_LOGIC;
reg_bsn_monitor_v2_tx_rdata : OUT STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
reg_bsn_monitor_v2_tx_rresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
reg_bsn_monitor_v2_tx_rdata : OUT STD_LOGIC_VECTOR(32-1 downto 0);
reg_bsn_monitor_v2_tx_rresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_bsn_monitor_v2_tx_rvalid : OUT STD_LOGIC;
-- reg_strobe_total_count_tx
-- copi
reg_strobe_total_count_tx_awaddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
reg_strobe_total_count_tx_awprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
reg_strobe_total_count_tx_awaddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_strobe_total_count_tx_awprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_strobe_total_count_tx_awvalid : IN STD_LOGIC;
reg_strobe_total_count_tx_wdata : IN STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
reg_strobe_total_count_tx_wstrb : IN STD_LOGIC_VECTOR((c_axi4_lite_data_w/c_byte_w)-1 downto 0);
reg_strobe_total_count_tx_wdata : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_strobe_total_count_tx_wstrb : IN STD_LOGIC_VECTOR((32/8)-1 downto 0);
reg_strobe_total_count_tx_wvalid : IN STD_LOGIC;
reg_strobe_total_count_tx_bready : IN STD_LOGIC;
reg_strobe_total_count_tx_araddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
reg_strobe_total_count_tx_arprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
reg_strobe_total_count_tx_araddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_strobe_total_count_tx_arprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_strobe_total_count_tx_arvalid : IN STD_LOGIC;
reg_strobe_total_count_tx_rready : IN STD_LOGIC;
-- cipo
reg_strobe_total_count_tx_awready : OUT STD_LOGIC;
reg_strobe_total_count_tx_wready : OUT STD_LOGIC;
reg_strobe_total_count_tx_bresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
reg_strobe_total_count_tx_bresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_strobe_total_count_tx_bvalid : OUT STD_LOGIC;
reg_strobe_total_count_tx_arready : OUT STD_LOGIC;
reg_strobe_total_count_tx_rdata : OUT STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
reg_strobe_total_count_tx_rresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
reg_strobe_total_count_tx_rdata : OUT STD_LOGIC_VECTOR(32-1 downto 0);
reg_strobe_total_count_tx_rresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_strobe_total_count_tx_rvalid : OUT STD_LOGIC;
-- reg_bsn_monitor_v2_rx
-- copi
reg_bsn_monitor_v2_rx_awaddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
reg_bsn_monitor_v2_rx_awprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
reg_bsn_monitor_v2_rx_awaddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_bsn_monitor_v2_rx_awprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_bsn_monitor_v2_rx_awvalid : IN STD_LOGIC;
reg_bsn_monitor_v2_rx_wdata : IN STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
reg_bsn_monitor_v2_rx_wstrb : IN STD_LOGIC_VECTOR((c_axi4_lite_data_w/c_byte_w)-1 downto 0);
reg_bsn_monitor_v2_rx_wdata : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_bsn_monitor_v2_rx_wstrb : IN STD_LOGIC_VECTOR((32/8)-1 downto 0);
reg_bsn_monitor_v2_rx_wvalid : IN STD_LOGIC;
reg_bsn_monitor_v2_rx_bready : IN STD_LOGIC;
reg_bsn_monitor_v2_rx_araddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
reg_bsn_monitor_v2_rx_arprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
reg_bsn_monitor_v2_rx_araddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_bsn_monitor_v2_rx_arprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_bsn_monitor_v2_rx_arvalid : IN STD_LOGIC;
reg_bsn_monitor_v2_rx_rready : IN STD_LOGIC;
-- cipo
reg_bsn_monitor_v2_rx_awready : OUT STD_LOGIC;
reg_bsn_monitor_v2_rx_wready : OUT STD_LOGIC;
reg_bsn_monitor_v2_rx_bresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
reg_bsn_monitor_v2_rx_bresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_bsn_monitor_v2_rx_bvalid : OUT STD_LOGIC;
reg_bsn_monitor_v2_rx_arready : OUT STD_LOGIC;
reg_bsn_monitor_v2_rx_rdata : OUT STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
reg_bsn_monitor_v2_rx_rresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
reg_bsn_monitor_v2_rx_rdata : OUT STD_LOGIC_VECTOR(32-1 downto 0);
reg_bsn_monitor_v2_rx_rresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_bsn_monitor_v2_rx_rvalid : OUT STD_LOGIC;
-- reg_strobe_total_count_rx
-- copi
reg_strobe_total_count_rx_awaddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
reg_strobe_total_count_rx_awprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
reg_strobe_total_count_rx_awaddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_strobe_total_count_rx_awprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_strobe_total_count_rx_awvalid : IN STD_LOGIC;
reg_strobe_total_count_rx_wdata : IN STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
reg_strobe_total_count_rx_wstrb : IN STD_LOGIC_VECTOR((c_axi4_lite_data_w/c_byte_w)-1 downto 0);
reg_strobe_total_count_rx_wdata : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_strobe_total_count_rx_wstrb : IN STD_LOGIC_VECTOR((32/8)-1 downto 0);
reg_strobe_total_count_rx_wvalid : IN STD_LOGIC;
reg_strobe_total_count_rx_bready : IN STD_LOGIC;
reg_strobe_total_count_rx_araddr : IN STD_LOGIC_VECTOR(c_axi4_lite_address_w-1 downto 0);
reg_strobe_total_count_rx_arprot : IN STD_LOGIC_VECTOR(c_axi4_lite_prot_w-1 downto 0);
reg_strobe_total_count_rx_araddr : IN STD_LOGIC_VECTOR(32-1 downto 0);
reg_strobe_total_count_rx_arprot : IN STD_LOGIC_VECTOR(3-1 downto 0);
reg_strobe_total_count_rx_arvalid : IN STD_LOGIC;
reg_strobe_total_count_rx_rready : IN STD_LOGIC;
-- cipo
reg_strobe_total_count_rx_awready : OUT STD_LOGIC;
reg_strobe_total_count_rx_wready : OUT STD_LOGIC;
reg_strobe_total_count_rx_bresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
reg_strobe_total_count_rx_bresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_strobe_total_count_rx_bvalid : OUT STD_LOGIC;
reg_strobe_total_count_rx_arready : OUT STD_LOGIC;
reg_strobe_total_count_rx_rdata : OUT STD_LOGIC_VECTOR(c_axi4_lite_data_w-1 downto 0);
reg_strobe_total_count_rx_rresp : OUT STD_LOGIC_VECTOR(c_axi4_lite_resp_w-1 downto 0);
reg_strobe_total_count_rx_rdata : OUT STD_LOGIC_VECTOR(32-1 downto 0);
reg_strobe_total_count_rx_rresp : OUT STD_LOGIC_VECTOR(2-1 downto 0);
reg_strobe_total_count_rx_rvalid : OUT STD_LOGIC
);
......
libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
+ 0
− 19
View file @ 3db7f083
......@@ -90,15 +90,11 @@ BEGIN
WRITE_PROTECT => 1 -- DECIMAL
)
port map (
dbiterra => OPEN, -- 1-bit output: Status signal to indicate double bit error occurrence
-- on the data output of port A.
dbiterrb => OPEN, -- 1-bit output: Status signal to indicate double bit error occurrence
-- on the data output of port A.
doutb => q, -- READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
sbiterra => OPEN, -- 1-bit output: Status signal to indicate single bit error occurrence
-- on the data output of port A.
sbiterrb => OPEN, -- 1-bit output: Status signal to indicate single bit error occurrence
-- on the data output of port B.
......@@ -125,28 +121,13 @@ BEGIN
-- ECC enabled (Error injection capability is not available in
-- "decode_only" mode).
injectdbiterrb => '0', -- 1-bit input: Controls double bit error injection on input data when
-- ECC enabled (Error injection capability is not available in
-- "decode_only" mode).
injectsbiterra => '0', -- 1-bit input: Controls single bit error injection on input data when
-- ECC enabled (Error injection capability is not available in
-- "decode_only" mode).
injectsbiterrb => '0', -- 1-bit input: Controls single bit error injection on input data when
-- ECC enabled (Error injection capability is not available in
-- "decode_only" mode).
regcea => '1', -- 1-bit input: Clock Enable for the last register stage on the output
-- data path.
regceb => '1', -- 1-bit input: Clock Enable for the last register stage on the output
-- data path.
rsta => '0', -- 1-bit input: Reset signal for the final port A output register
-- stage. Synchronously resets output port douta to the value specified
-- by parameter READ_RESET_VALUE_A.
rstb => '0', -- 1-bit input: Reset signal for the final port B output register
-- stage. Synchronously resets output port doutb to the value specified
-- by parameter READ_RESET_VALUE_B.
......
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