Added dedicated mem constant.

libraries/dsp/si/src/vhdl/si_arr.vhd

@@ -56,13 +56,15 @@ END si_arr;
 
 ARCHITECTURE str OF si_arr IS
 
-  SIGNAL reg_si_en : STD_LOGIC_VECTOR(c_mem_reg.dat_w*c_mem_reg.nof_dat-1 DOWNTO 0);
+  CONSTANT c_si_mem_reg : t_c_mem := (c_mem_reg_rd_latency, 1, 1, 1, '0');
+
+  SIGNAL reg_si_en : STD_LOGIC_VECTOR(c_si_mem_reg.dat_w*c_si_mem_reg.nof_dat-1 DOWNTO 0);
 
 BEGIN
 
   u_mms_common_reg : ENTITY common_lib.mms_common_reg
   GENERIC MAP (
-    g_mm_reg       => c_mem_reg
+    g_mm_reg       => c_si_mem_reg
   )
   PORT MAP (
     mm_rst         => mm_rst,