Added si_arr.vhd

libraries/dsp/si/hdllib.cfg

@@ -6,6 +6,7 @@ hdl_lib_technology =
 
 synth_files = 
     src/vhdl/si.vhd 
+    src/vhdl/si_arr.vhd 
  
 test_bench_files = 
     tb/vhdl/tb_si.vhd 

libraries/dsp/si/src/vhdl/si_arr.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author: R. van der Walle
+-- Purpose: Array wrapper for Spectral inversion.
+-- Description:
+-- . Adds array support and Memory Mapped enable interface to si.vhd. 
+-- Remark:
+-- . See si.vhd for more detail.
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY si_arr IS
+  GENERIC (
+    g_nof_streams : NATURAL := 1;
+    g_pipeline    : NATURAL := 1;   -- 0 for wires, 1 for output pipeline
+    g_dat_w       : NATURAL := 18
+  );
+  PORT (
+    in_sosi_arr  : IN  t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+    out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+    
+    reg_si_mosi  : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_si_miso  : OUT t_mem_miso;    
+
+    mm_rst       : IN  STD_LOGIC;
+    mm_clk       : IN  STD_LOGIC;
+    dp_clk       : IN  STD_LOGIC;
+    dp_rst       : IN  STD_LOGIC
+  );
+END si_arr;
+
+ARCHITECTURE str OF si_arr IS
+
+  SIGNAL reg_si_en : STD_LOGIC_VECTOR(c_mem_reg.dat_w*c_mem_reg.nof_dat-1 DOWNTO 0);
+
+BEGIN
+
+  u_mms_common_reg : ENTITY common_lib.mms_common_reg
+  GENERIC MAP (
+    g_mm_reg       => c_mem_reg
+  )
+  PORT MAP (
+    mm_rst         => mm_rst,
+    mm_clk         => mm_clk,
+    st_rst         => dp_rst,
+    st_clk         => dp_clk,
+
+    reg_mosi       => reg_si_mosi,
+    reg_miso       => reg_si_miso,
+
+    in_reg         => reg_si_en,
+    out_reg        => reg_si_en   
+  );
+
+  gen_nof_streams : FOR I in 0 TO g_nof_streams-1 GENERATE
+    u_si : ENTITY work.si
+    GENERIC MAP (
+      g_pipeline => g_pipeline,
+      g_dat_w    => g_dat_w
+    )
+    PORT MAP (
+      in_sosi   => in_sosi_arr(I), 
+      out_sosi  => out_sosi_arr(I), 
+      si_en     => reg_si_en(0), 
+      clk       => dp_clk,
+      rst       => dp_rst
+    );
+  END GENERATE;
+
+END str;