diff --git a/libraries/technology/ddr/tech_ddr_pkg.vhd b/libraries/technology/ddr/tech_ddr_pkg.vhd
index 853f266f3017bc3c108d0e40d018fb4b2c396cb6..e0609ff1880c4e336568c27e5c75260e524f0e5c 100644
--- a/libraries/technology/ddr/tech_ddr_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_pkg.vhd
@@ -26,54 +26,68 @@ USE common_lib.common_pkg.ALL;
PACKAGE tech_ddr_pkg IS
- -- DDR3
- TYPE t_c_tech_ddr_phy IS RECORD
- a_w : NATURAL; -- = 16;
- a_row_w : NATURAL; -- = 16; -- = a_w, row address width, via a_w lines
- a_col_w : NATURAL; -- = 10; -- <= a_w, col address width, via a_w lines
- ba_w : NATURAL; -- = 3;
- dq_w : NATURAL; -- = 64;
- dqs_w : NATURAL; -- = 8; -- = dq_w / nof_dq_per_dqs;
- dm_w : NATURAL; -- = 8;
- cs_w : NATURAL; -- = 2;
- clk_w : NATURAL; -- = 2;
- terminationcontrol_w : NATURAL; -- = 14;
+ -- Gather all parameters in one record
+ TYPE t_c_tech_ddr IS RECORD
+ -- PHY variant within a technology
+ mts : NATURAL; -- = 800 access rate in mega transfers per second
+ master : BOOLEAN; -- = TRUE TRUE = uniphy master, FALSE = uniphy slave regarding OCT and terminationcontrol for DDR3
+ -- PHY external FPGA IO
+ a_w : NATURAL; -- = 16
+ a_row_w : NATURAL; -- = 16 = a_w, row address width, via a_w lines
+ a_col_w : NATURAL; -- = 10 <= a_w, col address width, via a_w lines
+ ba_w : NATURAL; -- = 3
+ dq_w : NATURAL; -- = 64
+ dqs_w : NATURAL; -- = 8 = dq_w / nof_dq_per_dqs;
+ dm_w : NATURAL; -- = 8
+ cs_w : NATURAL; -- = 2
+ clk_w : NATURAL; -- = 2
+ -- PHY internal FPGA IO
+ terminationcontrol_w : NATURAL; -- = 14 internal bus in FPGA
+ -- Controller
+ rsl : NATURAL; -- = 4 = 2 (use both PHY clock edges) * 2 (PHY transfer at double rate), resolution
+ rsl_w : NATURAL; -- = 2 = ceil_log2(rsl)
+ address_w : NATURAL; -- = 32 = (2**32)*c_tech_ddr_phy.dq_w/c_byte_w bytes
+ data_w : NATURAL; -- = 256 = rsl * c_tech_ddr_phy.dq_w
+ maxburstsize : NATURAL; -- = 64
+ maxburstsize_w : NATURAL; -- = 7 = ceil_log2(maxburstsize+1)
END RECORD;
-
- CONSTANT c_tech_ddr_phy : t_c_tech_ddr_phy := (16, 16, 10, 3, 64, 8, 8, 2, 2, 14);
- CONSTANT c_tech_ddr_phy_4g : t_c_tech_ddr_phy := (15, 15, 10, 3, 64, 8, 8, 2, 2, 14);
-
+
+ CONSTANT c_tech_ddr_max : t_c_tech_ddr := ( 800, TRUE, 16, 16, 10, 3, 64, 8, 8, 2, 2, 14, 4, 2, 32, 256, 64, 7); -- maximum ranges for record field definitions
+ CONSTANT c_tech_ddr_4g_800m : t_c_tech_ddr := ( 800, TRUE, 15, 15, 10, 3, 64, 8, 8, 2, 2, 14, 4, 2, 32, 256, 64, 7);
+ CONSTANT c_tech_ddr_4g_800m_slave : t_c_tech_ddr := ( 800, FALSE, 15, 15, 10, 3, 64, 8, 8, 2, 2, 14, 4, 2, 32, 256, 64, 7);
+
+ -- PHY in, inout and out signal records
TYPE t_tech_ddr_phy_in IS RECORD
evt : STD_LOGIC; -- event signal is Not Connected to DDR3 PHY
oct_rup : STD_LOGIC; -- only master DDR3 PHY has On Chip Termination OCT inputs
oct_rdn : STD_LOGIC; -- only master DDR3 PHY has On Chip Termination OCT inputs
- seriesterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_phy.terminationcontrol_w-1 DOWNTO 0); -- termination control to slave from master DDR3 PHY
- parallelterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_phy.terminationcontrol_w-1 DOWNTO 0); -- termination control to slave from master DDR3 PHY
+ seriesterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_max.terminationcontrol_w-1 DOWNTO 0); -- termination control to slave from master DDR3 PHY (internal signal in FPGA)
+ parallelterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_max.terminationcontrol_w-1 DOWNTO 0); -- termination control to slave from master DDR3 PHY (internal signal in FPGA)
END RECORD;
TYPE t_tech_ddr_phy_io IS RECORD
- dq : STD_LOGIC_VECTOR(c_tech_ddr_phy.dq_w-1 DOWNTO 0); -- data bus
- dqs : STD_LOGIC_VECTOR(c_tech_ddr_phy.dqs_w-1 DOWNTO 0); -- data strobe bus
- dqs_n : STD_LOGIC_VECTOR(c_tech_ddr_phy.dqs_w-1 DOWNTO 0);
- clk : STD_LOGIC_VECTOR(c_tech_ddr_phy.clk_w-1 DOWNTO 0); -- clock, positive edge clock
- clk_n : STD_LOGIC_VECTOR(c_tech_ddr_phy.clk_w-1 DOWNTO 0); -- clock, negative edge clock
+ dq : STD_LOGIC_VECTOR(c_tech_ddr_max.dq_w-1 DOWNTO 0); -- data bus
+ dqs : STD_LOGIC_VECTOR(c_tech_ddr_max.dqs_w-1 DOWNTO 0); -- data strobe bus
+ dqs_n : STD_LOGIC_VECTOR(c_tech_ddr_max.dqs_w-1 DOWNTO 0);
+ clk : STD_LOGIC_VECTOR(c_tech_ddr_max.clk_w-1 DOWNTO 0); -- clock, positive edge clock
+ clk_n : STD_LOGIC_VECTOR(c_tech_ddr_max.clk_w-1 DOWNTO 0); -- clock, negative edge clock
scl : STD_LOGIC; -- I2C
sda : STD_LOGIC;
END RECORD;
TYPE t_tech_ddr_phy_ou IS RECORD
- a : STD_LOGIC_VECTOR(c_tech_ddr_phy.a_w-1 DOWNTO 0); -- row and column address
- ba : STD_LOGIC_VECTOR(c_tech_ddr_phy.ba_w-1 DOWNTO 0); -- bank address
- dm : STD_LOGIC_VECTOR(c_tech_ddr_phy.dm_w-1 DOWNTO 0); -- data mask bus
+ a : STD_LOGIC_VECTOR(c_tech_ddr_max.a_w-1 DOWNTO 0); -- row and column address
+ ba : STD_LOGIC_VECTOR(c_tech_ddr_max.ba_w-1 DOWNTO 0); -- bank address
+ dm : STD_LOGIC_VECTOR(c_tech_ddr_max.dm_w-1 DOWNTO 0); -- data mask bus
cas_n : STD_LOGIC; -- column address strobe
ras_n : STD_LOGIC; -- row address strobe
we_n : STD_LOGIC; -- write enable signal
reset_n : STD_LOGIC; -- reset signal
- odt : STD_LOGIC_VECTOR(c_tech_ddr_phy.cs_w-1 DOWNTO 0); -- on-die termination control signal
- cke : STD_LOGIC_VECTOR(c_tech_ddr_phy.cs_w-1 DOWNTO 0); -- clock enable
- cs_n : STD_LOGIC_VECTOR(c_tech_ddr_phy.cs_w-1 DOWNTO 0); -- chip select
- seriesterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_phy.terminationcontrol_w-1 DOWNTO 0); -- termination control from master to slave DDR3 PHY
- parallelterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_phy.terminationcontrol_w-1 DOWNTO 0); -- termination control from master to slave DDR3 PHY
+ odt : STD_LOGIC_VECTOR(c_tech_ddr_max.cs_w-1 DOWNTO 0); -- on-die termination control signal
+ cke : STD_LOGIC_VECTOR(c_tech_ddr_max.cs_w-1 DOWNTO 0); -- clock enable
+ cs_n : STD_LOGIC_VECTOR(c_tech_ddr_max.cs_w-1 DOWNTO 0); -- chip select
+ seriesterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_max.terminationcontrol_w-1 DOWNTO 0); -- termination control from master to slave DDR3 PHY (internal signal in FPGA)
+ parallelterminationcontrol : STD_LOGIC_VECTOR(c_tech_ddr_max.terminationcontrol_w-1 DOWNTO 0); -- termination control from master to slave DDR3 PHY (internal signal in FPGA)
END RECORD;
CONSTANT c_tech_ddr_phy_in_rst : t_tech_ddr_phy_in := ('0', 'X', 'X', (OTHERS=>'X'), (OTHERS=>'X'));
@@ -84,46 +98,37 @@ PACKAGE tech_ddr_pkg IS
TYPE t_tech_ddr_phy_io_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_io;
TYPE t_tech_ddr_phy_ou_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_phy_ou;
+ -- PHY address signal record
TYPE t_tech_ddr_addr IS RECORD
- chip : STD_LOGIC_VECTOR(ceil_log2(c_tech_ddr_phy.cs_w) -1 DOWNTO 0); -- Use ceil_log2() because the controller interprets the chip address as logical address (NOT individual chip select lines)
- bank : STD_LOGIC_VECTOR( c_tech_ddr_phy.ba_w -1 DOWNTO 0);
- row : STD_LOGIC_VECTOR( c_tech_ddr_phy.a_row_w-1 DOWNTO 0);
- column : STD_LOGIC_VECTOR( c_tech_ddr_phy.a_col_w-1 DOWNTO 0);
+ chip : STD_LOGIC_VECTOR(ceil_log2(c_tech_ddr_max.cs_w) -1 DOWNTO 0); -- Use ceil_log2() because the controller interprets the chip address as logical address (NOT individual chip select lines)
+ bank : STD_LOGIC_VECTOR( c_tech_ddr_max.ba_w -1 DOWNTO 0);
+ row : STD_LOGIC_VECTOR( c_tech_ddr_max.a_row_w-1 DOWNTO 0);
+ column : STD_LOGIC_VECTOR( c_tech_ddr_max.a_col_w-1 DOWNTO 0);
END RECORD;
TYPE t_tech_ddr_addr_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_addr;
-
- TYPE t_c_tech_ddr_ctlr IS RECORD -- DDR3
- rsl : NATURAL; -- = 4 = 2 (use both PHY clock edges) * 2 (PHY transfer at double rate), resolution
- rsl_w : NATURAL; -- = 2 = ceil_log2(rsl)
- address_w : NATURAL; -- = 32 = (2**32)*c_tech_ddr_phy.dq_w/c_byte_w bytes
- data_w : NATURAL; -- = 256 = rsl * c_tech_ddr_phy.dq_w
- maxburstsize : NATURAL; -- = 64
- maxburstsize_w : NATURAL; -- = 7 = ceil_log2(maxburstsize+1)
- END RECORD;
-
- CONSTANT c_tech_ddr_ctlr : t_c_tech_ddr_ctlr := (4, 2, 32, 256, 64, 7);
CONSTANT c_tech_ddr_ctrl_nof_latent_reads : NATURAL := 100; -- Due to having a command cue, even after de-asserting read requests, the PHY keeps processing the cued read requests.
- -- This makes sure 100 words are still available in the read FIFO after it de-asserted its siso.ready signal towards the ddr3 read side.
+ -- This makes sure 100 words are still available in the read FIFO after it de-asserted its siso.ready signal towards the ddr3 read side.
- CONSTANT c_tech_ddr_addr_lo : t_tech_ddr_addr := ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'));
- CONSTANT c_tech_ddr_addr_hi_4gb : t_tech_ddr_addr := ((OTHERS=>'1'), (OTHERS=>'1'), (OTHERS=>'1'), TO_UVEC(2**c_tech_ddr_phy_4g.a_col_w - c_tech_ddr_ctlr.rsl, c_tech_ddr_phy_4g.a_col_w));
- CONSTANT c_tech_ddr_addr_hi_sim : t_tech_ddr_addr := ((OTHERS=>'0'), (OTHERS=>'0'), TO_UVEC(3, c_tech_ddr_phy.a_row_w), TO_UVEC(2**c_tech_ddr_phy_4g.a_col_w - c_tech_ddr_ctlr.rsl, c_tech_ddr_phy_4g.a_col_w));
+ CONSTANT c_tech_ddr_addr_lo : t_tech_ddr_addr := ((OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'), (OTHERS=>'0'));
+ CONSTANT c_tech_ddr_addr_hi_4gb_800m : t_tech_ddr_addr := ((OTHERS=>'1'), (OTHERS=>'1'), (OTHERS=>'1'), TO_UVEC(2**c_tech_ddr_4g_800m.a_col_w - c_tech_ddr_4g_800m.rsl, c_tech_ddr_4g_800m.a_col_w));
+ CONSTANT c_tech_ddr_addr_hi_sim : t_tech_ddr_addr := ((OTHERS=>'0'), (OTHERS=>'0'), TO_UVEC(3, c_tech_ddr_4g_800m.a_row_w), TO_UVEC(2**c_tech_ddr_4g_800m.a_col_w - c_tech_ddr_4g_800m.rsl, c_tech_ddr_4g_800m.a_col_w));
+ -- PHY MM access signal record
TYPE t_tech_ddr_miso IS RECORD
- rddata : STD_LOGIC_VECTOR(c_tech_ddr_ctlr.data_w-1 DOWNTO 0);
+ rddata : STD_LOGIC_VECTOR(c_tech_ddr_max.data_w-1 DOWNTO 0);
rdval : STD_LOGIC;
waitrequest_n : STD_LOGIC;
END RECORD;
TYPE t_tech_ddr_mosi IS RECORD
- address : STD_LOGIC_VECTOR(c_tech_ddr_ctlr.address_w-1 DOWNTO 0);
- wrdata : STD_LOGIC_VECTOR(c_tech_ddr_ctlr.data_w-1 DOWNTO 0);
+ address : STD_LOGIC_VECTOR(c_tech_ddr_max.address_w-1 DOWNTO 0);
+ wrdata : STD_LOGIC_VECTOR(c_tech_ddr_max.data_w-1 DOWNTO 0);
wr : STD_LOGIC;
rd : STD_LOGIC;
burstbegin : STD_LOGIC;
- burstsize : STD_LOGIC_VECTOR(c_tech_ddr_ctlr.maxburstsize_w-1 DOWNTO 0);
+ burstsize : STD_LOGIC_VECTOR(c_tech_ddr_max.maxburstsize_w-1 DOWNTO 0);
END RECORD;
END tech_ddr_pkg;
diff --git a/libraries/technology/ddr3/tech_ddr3.vhd b/libraries/technology/ddr3/tech_ddr3.vhd
index 8c38c491fe98ead82d6eab7831fc777dbeaa4c1d..fa8dd8a7eee33b895a004bd33d97a74d3719963f 100644
--- a/libraries/technology/ddr3/tech_ddr3.vhd
+++ b/libraries/technology/ddr3/tech_ddr3.vhd
@@ -29,9 +29,7 @@ USE tech_ddr_lib.tech_ddr_pkg.ALL;
ENTITY tech_ddr3 IS
GENERIC (
g_technology : NATURAL := c_tech_select_default;
- g_master : BOOLEAN := TRUE;
- g_ddr_phy : t_c_tech_ddr_phy;
- g_ddr_ctlr : t_c_tech_ddr_ctlr
+ g_ddr : t_c_tech_ddr
);
PORT (
-- PLL reference clock
@@ -63,7 +61,7 @@ BEGIN
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
u0 : ENTITY work.tech_ddr3_stratixiv
- GENERIC MAP (g_master, g_ddr_phy, g_ddr_ctlr)
+ GENERIC MAP (g_ddr)
PORT MAP (ctlr_ref_clk, ctlr_ref_rst,
ctlr_gen_clk, ctlr_gen_rst, ctlr_gen_clk_2x, ctlr_gen_rst_2x,
ctlr_init_done,
diff --git a/libraries/technology/ddr3/tech_ddr3_stratixiv.vhd b/libraries/technology/ddr3/tech_ddr3_stratixiv.vhd
index 3b847387c8042ef2e80e75c8a6104b8be3c64ab0..2444e87fe1ab420578ef93050a759d252f437fdc 100644
--- a/libraries/technology/ddr3/tech_ddr3_stratixiv.vhd
+++ b/libraries/technology/ddr3/tech_ddr3_stratixiv.vhd
@@ -32,9 +32,7 @@ USE work.tech_ddr3_component_pkg.ALL;
ENTITY tech_ddr3_stratixiv IS
GENERIC (
- g_master : BOOLEAN := TRUE;
- g_ddr_phy : t_c_tech_ddr_phy;
- g_ddr_ctlr : t_c_tech_ddr_ctlr
+ g_ddr : t_c_tech_ddr
);
PORT (
-- PLL reference clock
@@ -67,105 +65,105 @@ ARCHITECTURE str OF tech_ddr3_stratixiv IS
BEGIN
- gen_master : IF g_master=TRUE GENERATE
+ gen_master : IF g_ddr.master=TRUE GENERATE
u_ip_stratixiv_ddr3_uphy_4g_800_master : ip_stratixiv_ddr3_uphy_4g_800_master
PORT MAP (
- pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk.clk
- global_reset_n => ctlr_ref_rst, -- global_reset.reset_n
- soft_reset_n => '0', -- soft_reset.reset_n
- afi_clk => ctlr_gen_clk, -- afi_clk.clk
- afi_half_clk => OPEN, -- afi_half_clk.clk
- afi_reset_n => ctlr_gen_rst, -- afi_reset.reset_n
- mem_a => phy_ou.a(g_ddr_phy.a_w-1 DOWNTO 0), -- memory.mem_a
- mem_ba => phy_ou.ba(g_ddr_phy.ba_w-1 DOWNTO 0), -- .mem_ba
- mem_ck => phy_io.clk(g_ddr_phy.clk_w-1 DOWNTO 0), -- .mem_ck
- mem_ck_n => phy_io.clk_n(g_ddr_phy.clk_w-1 DOWNTO 0), -- .mem_ck_n
- mem_cke => phy_ou.cke(g_ddr_phy.clk_w-1 DOWNTO 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_ddr_phy.cs_w-1 DOWNTO 0), -- .mem_cs_n
- mem_dm => phy_ou.dm(g_ddr_phy.dm_w-1 DOWNTO 0), -- .mem_dm
- mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
- mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
- mem_we_n => phy_ou.we_n, -- .mem_we_n
- mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
- mem_dq => phy_io.dq(g_ddr_phy.dq_w-1 DOWNTO 0), -- .mem_dq
- mem_dqs => phy_io.dqs(g_ddr_phy.dqs_w-1 DOWNTO 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_ddr_phy.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
- mem_odt => phy_ou.odt(g_ddr_phy.cs_w-1 DOWNTO 0), -- .mem_odt
- avl_ready => ctrl_miso.waitrequest_n, -- avl.waitrequest_n
- avl_burstbegin => ctrl_mosi.burstbegin, -- .beginbursttransfer
- avl_addr => ctrl_mosi.address(g_ddr_ctlr.address_w-1 DOWNTO 0), -- .address
- avl_rdata_valid => ctrl_miso.rdval, -- .readdatavalid
- avl_rdata => ctrl_miso.rddata(g_ddr_ctlr.data_w-1 DOWNTO 0), -- .readdata
- avl_wdata => ctrl_mosi.wrdata(g_ddr_ctlr.data_w-1 DOWNTO 0), -- .writedata
- avl_be => (OTHERS=>'1'), -- .byteenable
- avl_read_req => ctrl_mosi.rd, -- .read
- avl_write_req => ctrl_mosi.wr, -- .write
- avl_size => ctrl_mosi.burstsize(g_ddr_ctlr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
- local_init_done => ctlr_init_done, -- status.local_init_done
- local_cal_success => OPEN, -- .local_cal_success
- local_cal_fail => OPEN, -- .local_cal_fail
- oct_rdn => phy_in.oct_rdn, -- oct.rdn
- oct_rup => phy_in.oct_rup, -- .rup
- seriesterminationcontrol => phy_ou.seriesterminationcontrol(g_ddr_phy.terminationcontrol_w-1 DOWNTO 0), -- oct_sharing.seriesterminationcontrol
- parallelterminationcontrol => phy_ou.parallelterminationcontrol(g_ddr_phy.terminationcontrol_w-1 DOWNTO 0), -- .parallelterminationcontrol
- pll_mem_clk => i_ctlr_gen_clk_2x, -- pll_sharing.pll_mem_clk
- pll_write_clk => OPEN, -- .pll_write_clk
- pll_write_clk_pre_phy_clk => OPEN, -- .pll_write_clk_pre_phy_clk
- pll_addr_cmd_clk => OPEN, -- .pll_addr_cmd_clk
- pll_locked => OPEN, -- .pll_locked
- pll_avl_clk => OPEN, -- .pll_avl_clk
- pll_config_clk => OPEN, -- .pll_config_clk
- dll_delayctrl => OPEN -- dll_sharing.dll_delayctrl
+ pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk.clk
+ global_reset_n => ctlr_ref_rst, -- global_reset.reset_n
+ soft_reset_n => '0', -- soft_reset.reset_n
+ afi_clk => ctlr_gen_clk, -- afi_clk.clk
+ afi_half_clk => OPEN, -- afi_half_clk.clk
+ afi_reset_n => ctlr_gen_rst, -- afi_reset.reset_n
+ mem_a => phy_ou.a(g_ddr.a_w-1 DOWNTO 0), -- memory.mem_a
+ mem_ba => phy_ou.ba(g_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
+ mem_ck => phy_io.clk(g_ddr.clk_w-1 DOWNTO 0), -- .mem_ck
+ mem_ck_n => phy_io.clk_n(g_ddr.clk_w-1 DOWNTO 0), -- .mem_ck_n
+ mem_cke => phy_ou.cke(g_ddr.clk_w-1 DOWNTO 0), -- .mem_cke
+ mem_cs_n => phy_ou.cs_n(g_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
+ mem_dm => phy_ou.dm(g_ddr.dm_w-1 DOWNTO 0), -- .mem_dm
+ mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
+ mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
+ mem_we_n => phy_ou.we_n, -- .mem_we_n
+ mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
+ mem_dq => phy_io.dq(g_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
+ mem_dqs => phy_io.dqs(g_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
+ mem_dqs_n => phy_io.dqs_n(g_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
+ mem_odt => phy_ou.odt(g_ddr.cs_w-1 DOWNTO 0), -- .mem_odt
+ avl_ready => ctrl_miso.waitrequest_n, -- avl.waitrequest_n
+ avl_burstbegin => ctrl_mosi.burstbegin, -- .beginbursttransfer
+ avl_addr => ctrl_mosi.address(g_ddr.address_w-1 DOWNTO 0), -- .address
+ avl_rdata_valid => ctrl_miso.rdval, -- .readdatavalid
+ avl_rdata => ctrl_miso.rddata(g_ddr.data_w-1 DOWNTO 0), -- .readdata
+ avl_wdata => ctrl_mosi.wrdata(g_ddr.data_w-1 DOWNTO 0), -- .writedata
+ avl_be => (OTHERS=>'1'), -- .byteenable
+ avl_read_req => ctrl_mosi.rd, -- .read
+ avl_write_req => ctrl_mosi.wr, -- .write
+ avl_size => ctrl_mosi.burstsize(g_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
+ local_init_done => ctlr_init_done, -- status.local_init_done
+ local_cal_success => OPEN, -- .local_cal_success
+ local_cal_fail => OPEN, -- .local_cal_fail
+ oct_rdn => phy_in.oct_rdn, -- oct.rdn
+ oct_rup => phy_in.oct_rup, -- .rup
+ seriesterminationcontrol => phy_ou.seriesterminationcontrol(g_ddr.terminationcontrol_w-1 DOWNTO 0), -- oct_sharing.seriesterminationcontrol
+ parallelterminationcontrol => phy_ou.parallelterminationcontrol(g_ddr.terminationcontrol_w-1 DOWNTO 0), -- .parallelterminationcontrol
+ pll_mem_clk => i_ctlr_gen_clk_2x, -- pll_sharing.pll_mem_clk
+ pll_write_clk => OPEN, -- .pll_write_clk
+ pll_write_clk_pre_phy_clk => OPEN, -- .pll_write_clk_pre_phy_clk
+ pll_addr_cmd_clk => OPEN, -- .pll_addr_cmd_clk
+ pll_locked => OPEN, -- .pll_locked
+ pll_avl_clk => OPEN, -- .pll_avl_clk
+ pll_config_clk => OPEN, -- .pll_config_clk
+ dll_delayctrl => OPEN -- dll_sharing.dll_delayctrl
);
END GENERATE;
- gen_slave : IF g_master=FALSE GENERATE
+ gen_slave : IF g_ddr.master=FALSE GENERATE
u_ip_stratixiv_ddr3_uphy_4g_800_slave : ip_stratixiv_ddr3_uphy_4g_800_slave
PORT MAP (
- pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk.clk
- global_reset_n => ctlr_ref_rst, -- global_reset.reset_n
- soft_reset_n => '0', -- soft_reset.reset_n
- afi_clk => ctlr_gen_clk, -- afi_clk.clk
- afi_half_clk => OPEN, -- afi_half_clk.clk
- afi_reset_n => ctlr_gen_rst, -- afi_reset.reset_n
- mem_a => phy_ou.a(g_ddr_phy.a_w-1 DOWNTO 0), -- memory.mem_a
- mem_ba => phy_ou.ba(g_ddr_phy.ba_w-1 DOWNTO 0), -- .mem_ba
- mem_ck => phy_io.clk(g_ddr_phy.clk_w-1 DOWNTO 0), -- .mem_ck
- mem_ck_n => phy_io.clk_n(g_ddr_phy.clk_w-1 DOWNTO 0), -- .mem_ck_n
- mem_cke => phy_ou.cke(g_ddr_phy.clk_w-1 DOWNTO 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(g_ddr_phy.cs_w-1 DOWNTO 0), -- .mem_cs_n
- mem_dm => phy_ou.dm(g_ddr_phy.dm_w-1 DOWNTO 0), -- .mem_dm
- mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
- mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
- mem_we_n => phy_ou.we_n, -- .mem_we_n
- mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
- mem_dq => phy_io.dq(g_ddr_phy.dq_w-1 DOWNTO 0), -- .mem_dq
- mem_dqs => phy_io.dqs(g_ddr_phy.dqs_w-1 DOWNTO 0), -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n(g_ddr_phy.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
- mem_odt => phy_ou.odt(g_ddr_phy.cs_w-1 DOWNTO 0), -- .mem_odt
- avl_ready => ctrl_miso.waitrequest_n, -- avl.waitrequest_n
- avl_burstbegin => ctrl_mosi.burstbegin, -- .beginbursttransfer
- avl_addr => ctrl_mosi.address(g_ddr_ctlr.address_w-1 DOWNTO 0), -- .address
- avl_rdata_valid => ctrl_miso.rdval, -- .readdatavalid
- avl_rdata => ctrl_miso.rddata(g_ddr_ctlr.data_w-1 DOWNTO 0), -- .readdata
- avl_wdata => ctrl_mosi.wrdata(g_ddr_ctlr.data_w-1 DOWNTO 0), -- .writedata
- avl_be => (OTHERS=>'1'), -- .byteenable
- avl_read_req => ctrl_mosi.rd, -- .read
- avl_write_req => ctrl_mosi.wr, -- .write
- avl_size => ctrl_mosi.burstsize(g_ddr_ctlr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
- local_init_done => ctlr_init_done, -- status.local_init_done
- local_cal_success => OPEN, -- .local_cal_success
- local_cal_fail => OPEN, -- .local_cal_fail
- seriesterminationcontrol => phy_in.seriesterminationcontrol(g_ddr_phy.terminationcontrol_w-1 DOWNTO 0), -- oct_sharing.seriesterminationcontrol
- parallelterminationcontrol => phy_in.parallelterminationcontrol(g_ddr_phy.terminationcontrol_w-1 DOWNTO 0), -- .parallelterminationcontrol
- pll_mem_clk => i_ctlr_gen_clk_2x, -- pll_sharing.pll_mem_clk
- pll_write_clk => OPEN, -- .pll_write_clk
- pll_write_clk_pre_phy_clk => OPEN, -- .pll_write_clk_pre_phy_clk
- pll_addr_cmd_clk => OPEN, -- .pll_addr_cmd_clk
- pll_locked => OPEN, -- .pll_locked
- pll_avl_clk => OPEN, -- .pll_avl_clk
- pll_config_clk => OPEN, -- .pll_config_clk
- dll_delayctrl => OPEN -- dll_sharing.dll_delayctrl
+ pll_ref_clk => ctlr_ref_clk, -- pll_ref_clk.clk
+ global_reset_n => ctlr_ref_rst, -- global_reset.reset_n
+ soft_reset_n => '0', -- soft_reset.reset_n
+ afi_clk => ctlr_gen_clk, -- afi_clk.clk
+ afi_half_clk => OPEN, -- afi_half_clk.clk
+ afi_reset_n => ctlr_gen_rst, -- afi_reset.reset_n
+ mem_a => phy_ou.a(g_ddr.a_w-1 DOWNTO 0), -- memory.mem_a
+ mem_ba => phy_ou.ba(g_ddr.ba_w-1 DOWNTO 0), -- .mem_ba
+ mem_ck => phy_io.clk(g_ddr.clk_w-1 DOWNTO 0), -- .mem_ck
+ mem_ck_n => phy_io.clk_n(g_ddr.clk_w-1 DOWNTO 0), -- .mem_ck_n
+ mem_cke => phy_ou.cke(g_ddr.clk_w-1 DOWNTO 0), -- .mem_cke
+ mem_cs_n => phy_ou.cs_n(g_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
+ mem_dm => phy_ou.dm(g_ddr.dm_w-1 DOWNTO 0), -- .mem_dm
+ mem_ras_n => phy_ou.ras_n, -- .mem_ras_n
+ mem_cas_n => phy_ou.cas_n, -- .mem_cas_n
+ mem_we_n => phy_ou.we_n, -- .mem_we_n
+ mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
+ mem_dq => phy_io.dq(g_ddr.dq_w-1 DOWNTO 0), -- .mem_dq
+ mem_dqs => phy_io.dqs(g_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs
+ mem_dqs_n => phy_io.dqs_n(g_ddr.dqs_w-1 DOWNTO 0), -- .mem_dqs_n
+ mem_odt => phy_ou.odt(g_ddr.cs_w-1 DOWNTO 0), -- .mem_odt
+ avl_ready => ctrl_miso.waitrequest_n, -- avl.waitrequest_n
+ avl_burstbegin => ctrl_mosi.burstbegin, -- .beginbursttransfer
+ avl_addr => ctrl_mosi.address(g_ddr.address_w-1 DOWNTO 0), -- .address
+ avl_rdata_valid => ctrl_miso.rdval, -- .readdatavalid
+ avl_rdata => ctrl_miso.rddata(g_ddr.data_w-1 DOWNTO 0), -- .readdata
+ avl_wdata => ctrl_mosi.wrdata(g_ddr.data_w-1 DOWNTO 0), -- .writedata
+ avl_be => (OTHERS=>'1'), -- .byteenable
+ avl_read_req => ctrl_mosi.rd, -- .read
+ avl_write_req => ctrl_mosi.wr, -- .write
+ avl_size => ctrl_mosi.burstsize(g_ddr.maxburstsize_w-1 DOWNTO 0), -- .burstcount
+ local_init_done => ctlr_init_done, -- status.local_init_done
+ local_cal_success => OPEN, -- .local_cal_success
+ local_cal_fail => OPEN, -- .local_cal_fail
+ seriesterminationcontrol => phy_in.seriesterminationcontrol(g_ddr.terminationcontrol_w-1 DOWNTO 0), -- oct_sharing.seriesterminationcontrol
+ parallelterminationcontrol => phy_in.parallelterminationcontrol(g_ddr.terminationcontrol_w-1 DOWNTO 0), -- .parallelterminationcontrol
+ pll_mem_clk => i_ctlr_gen_clk_2x, -- pll_sharing.pll_mem_clk
+ pll_write_clk => OPEN, -- .pll_write_clk
+ pll_write_clk_pre_phy_clk => OPEN, -- .pll_write_clk_pre_phy_clk
+ pll_addr_cmd_clk => OPEN, -- .pll_addr_cmd_clk
+ pll_locked => OPEN, -- .pll_locked
+ pll_avl_clk => OPEN, -- .pll_avl_clk
+ pll_config_clk => OPEN, -- .pll_config_clk
+ dll_delayctrl => OPEN -- dll_sharing.dll_delayctrl
);
END GENERATE;