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Commit 3c68991a authored by Eric Kooistra's avatar Eric Kooistra
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More clearly separate clock generation for XAUI (Stratix IV) and for 10GBASE-R (Arria10).

parent 3ac2a5c5
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...@@ -220,11 +220,23 @@ BEGIN ...@@ -220,11 +220,23 @@ BEGIN
rx_siso_arr(0) <= rx_siso; rx_siso_arr(0) <= rx_siso;
rx_sosi <= rx_sosi_arr(0); rx_sosi <= rx_sosi_arr(0);
tr_ref_clk_644 <= NOT tr_ref_clk_644 AFTER g_ref_clk_644_period/2; -- Connect the clocks from test bench top level (down such that they have their rising_edge() aligned without any delta-delay)
gen_tb_clocks_xaui : IF g_technology=c_tech_stratixiv GENERATE
tr_ref_clk_644 <= 'X';
tr_ref_clk_156 <= NOT tr_ref_clk_156 AFTER g_ref_clk_156_period/2; tr_ref_clk_156 <= NOT tr_ref_clk_156 AFTER g_ref_clk_156_period/2;
tr_ref_rst_156 <= '0' AFTER g_ref_clk_156_period*5; tr_ref_rst_156 <= '0' AFTER g_ref_clk_156_period*5;
tb_ref_clk_156 <= tr_ref_clk_156;
tb_ref_rst_156 <= tr_ref_rst_156;
tb_tx_clk <= tr_ref_clk_156;
tb_rx_clk <= rx_clk_arr_out(0);
tb_tx_rst <= tx_rst_arr(0);
tb_rx_rst <= rx_rst_arr(0);
END GENERATE;
gen_tb_clocks_10gbase_r : IF g_technology=c_tech_arria10 GENERATE
tr_ref_clk_644 <= NOT tr_ref_clk_644 AFTER g_ref_clk_644_period/2;
pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
GENERIC MAP ( GENERIC MAP (
g_technology => g_technology g_technology => g_technology
...@@ -237,17 +249,6 @@ BEGIN ...@@ -237,17 +249,6 @@ BEGIN
rst_312 => OPEN rst_312 => OPEN
); );
-- Connect the clocks from test bench top level (down such that they have their rising_edge() aligned without any delta-delay)
gen_tb_clocks_xaui : IF g_technology=c_tech_stratixiv GENERATE
tb_ref_clk_156 <= tr_ref_clk_156;
tb_ref_rst_156 <= tr_ref_rst_156;
tb_tx_clk <= tr_ref_clk_156;
tb_rx_clk <= rx_clk_arr_out(0);
tb_tx_rst <= tx_rst_arr(0);
tb_rx_rst <= rx_rst_arr(0);
END GENERATE;
gen_tb_clocks_10gbase_r : IF g_technology=c_tech_arria10 GENERATE
tb_ref_clk_644 <= tr_ref_clk_644; tb_ref_clk_644 <= tr_ref_clk_644;
tb_clk_312 <= clk_312; tb_clk_312 <= clk_312;
tb_clk_156 <= clk_156; tb_clk_156 <= clk_156;
......
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