diff --git a/libraries/technology/eth_10g/tb_tech_eth_10g.vhd b/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
index 0108639b0aea81736561e234a392b7eea26433e7..48f6e909ca727fd10876ec2dce0e961351d59381 100644
--- a/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
+++ b/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
@@ -220,25 +220,12 @@ BEGIN
   rx_siso_arr(0) <= rx_siso;
   rx_sosi        <= rx_sosi_arr(0);
   
-  tr_ref_clk_644 <= NOT tr_ref_clk_644 AFTER g_ref_clk_644_period/2;
-  tr_ref_clk_156 <= NOT tr_ref_clk_156 AFTER g_ref_clk_156_period/2;
-
-  tr_ref_rst_156 <= '0' AFTER g_ref_clk_156_period*5;
-  
-  pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
-  GENERIC MAP (
-    g_technology => g_technology
-  )
-  PORT MAP (
-    refclk_644 => tr_ref_clk_644,
-    clk_156    => clk_156,
-    clk_312    => clk_312,
-    rst_156    => rst_156,
-    rst_312    => OPEN
-  );
-  
   -- Connect the clocks from test bench top level (down such that they have their rising_edge() aligned without any delta-delay)
   gen_tb_clocks_xaui : IF g_technology=c_tech_stratixiv GENERATE
+    tr_ref_clk_644 <= 'X';
+    tr_ref_clk_156 <= NOT tr_ref_clk_156 AFTER g_ref_clk_156_period/2;
+    tr_ref_rst_156 <= '0' AFTER g_ref_clk_156_period*5;
+    
     tb_ref_clk_156 <= tr_ref_clk_156;
     tb_ref_rst_156 <= tr_ref_rst_156;
     tb_tx_clk      <= tr_ref_clk_156;
@@ -248,6 +235,20 @@ BEGIN
   END GENERATE;
     
   gen_tb_clocks_10gbase_r : IF g_technology=c_tech_arria10 GENERATE
+    tr_ref_clk_644 <= NOT tr_ref_clk_644 AFTER g_ref_clk_644_period/2;
+  
+    pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
+    GENERIC MAP (
+      g_technology => g_technology
+    )
+    PORT MAP (
+      refclk_644 => tr_ref_clk_644,
+      clk_156    => clk_156,
+      clk_312    => clk_312,
+      rst_156    => rst_156,
+      rst_312    => OPEN
+    );
+  
     tb_ref_clk_644 <= tr_ref_clk_644;
     tb_clk_312     <= clk_312;
     tb_clk_156     <= clk_156;