add key to hdllib.cfg

libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg

@@ -19,3 +19,8 @@ modelsim_compile_ip_files =
 quartus_qip_files =
     generated/ip_arria10_tse_sgmii_lvds.qip
 
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_tse_sgmii_lvds.qsys
+

libraries/technology/ip_arria10/voltage_sense/hdllib.cfg

@@ -17,3 +17,8 @@ test_bench_files =
 
 [quartus_project_file]
 quartus_qip_files = generated/ip_arria10_voltage_sense.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_voltage_sense.qsys
+

libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_e1sg_clkbuf_global.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_clkbuf_global.qsys
+

libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_e1sg_complex_mult.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_complex_mult.qsys
+

libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg

@@ -20,3 +20,9 @@ modelsim_compile_ip_files =
 quartus_qip_files =
     generated/ip_arria10_e1sg_ddio_in_1.qip
     generated/ip_arria10_e1sg_ddio_out_1.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_ddio_in_1.qsys
+    ip_arria10_e1sg_ddio_out_1.qsys
+

libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_e1sg_ddr4_4g_1600.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_ddr4_4g_1600.qsys
+

libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_e1sg_ddr4_4g_2000.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_ddr4_4g_2000.qsys
+

libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg

@@ -18,3 +18,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_e1sg_ddr4_8g_1600.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_ddr4_8g_1600.qsys
+

libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_e1sg_ddr4_8g_2400.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_ddr4_8g_2400.qsys
+

libraries/technology/ip_arria10_e1sg/fifo/hdllib.cfg

@@ -17,3 +17,10 @@ test_bench_files =
 
 [quartus_project_file]
 
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_fifo_sc.qsys
+    ip_arria10_e1sg_fifo_dc.qsys
+    ip_arria10_e1sg_fifo_dc_mixed_widths.qsys
+

libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_e1sg_asmi_parallel.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_asmi_parallel.qsys
+

libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_e1sg_remote_update.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_remote_update.qsys
+

libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_e1sg_fractional_pll_clk125.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_fractional_pll_clk125.qsys
+

libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_e1sg_fractional_pll_clk200.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_fractional_pll_clk200.qsys
+

libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg

@@ -20,3 +20,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_e1sg_mac_10g.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_mac_10g.qsys
+

libraries/technology/ip_arria10_e1sg/mult_add4/hdllib.cfg

@@ -14,3 +14,8 @@ test_bench_files =
 
 
 [quartus_project_file]
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_mult_add4.qsys
+

libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_e1sg_phy_10gbase_r.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_phy_10gbase_r.qsys
+

libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_e1sg_phy_10gbase_r_12.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_phy_10gbase_r_12.qsys
+

libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_e1sg_phy_10gbase_r_24.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_phy_10gbase_r_24.qsys
+

libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg

@@ -17,3 +17,8 @@ modelsim_compile_ip_files =
 [quartus_project_file]
 quartus_qip_files =
     generated/ip_arria10_e1sg_phy_10gbase_r_4.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files = 
+    ip_arria10_e1sg_phy_10gbase_r_4.qsys
+